teensy-4.x: update pikron-bb configuration with PMSM control abilities

This commit updates configuration pikron-bb (configuration for open
hardware experimental board) to support permanent magnet sychnronous
motor control. This includes setup of PWM, GPIO and ADC peripherals.

Required follow up changes are done to pinout definition.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit is contained in:
Michal Lenc 2023-02-11 01:11:40 +01:00 committed by Xiang Xiao
parent 00e87962fd
commit fd91af4f70
6 changed files with 83 additions and 19 deletions

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@ -39,4 +39,14 @@ config NET_USE_OTP_ETHERNET_MAC
(the vendor ID of 'PJRC.COM, LLC') when this feature is enabled. (the vendor ID of 'PJRC.COM, LLC') when this feature is enabled.
It may also be used with other boards that have the OCOTP programmed with a valid MAC. It may also be used with other boards that have the OCOTP programmed with a valid MAC.
if TEENSY_41
config TEENSY_41_PIKRON_BB
bool "Base board for Teensy 4.1 configuration"
---help---
Configuration pikron-bb contains setup for open hardware based board fo Teensy 4.1. This option
sets up HW pinout as ADC channels for example.
endif
endif endif

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@ -7,7 +7,12 @@
# #
# CONFIG_ARCH_LEDS is not set # CONFIG_ARCH_LEDS is not set
# CONFIG_NSH_DISABLE_DATE is not set # CONFIG_NSH_DISABLE_DATE is not set
# CONFIG_NSH_DISABLE_MB is not set
# CONFIG_NSH_DISABLE_MH is not set
# CONFIG_NSH_DISABLE_MW is not set
CONFIG_ADC=y
CONFIG_ALLOW_GPL_COMPONENTS=y CONFIG_ALLOW_GPL_COMPONENTS=y
CONFIG_ANALOG=y
CONFIG_ARCH="arm" CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="teensy-4.x" CONFIG_ARCH_BOARD="teensy-4.x"
CONFIG_ARCH_BOARD_TEENSY_4X=y CONFIG_ARCH_BOARD_TEENSY_4X=y
@ -29,12 +34,12 @@ CONFIG_CANCELLATION_POINTS=y
CONFIG_CANUTILS_CANDUMP=y CONFIG_CANUTILS_CANDUMP=y
CONFIG_CANUTILS_CANSEND=y CONFIG_CANUTILS_CANSEND=y
CONFIG_CAN_FD=y CONFIG_CAN_FD=y
CONFIG_DEV_GPIO=y
CONFIG_DEV_LOOP=y CONFIG_DEV_LOOP=y
CONFIG_DEV_ZERO=y CONFIG_DEV_ZERO=y
CONFIG_DRIVERS_VIDEO=y
CONFIG_ELF=y CONFIG_ELF=y
CONFIG_ENC1_XIE=y
CONFIG_ETH0_PHY_DP83825I=y CONFIG_ETH0_PHY_DP83825I=y
CONFIG_EXAMPLES_FB=y
CONFIG_EXECFUNCS_HAVE_SYMTAB=y CONFIG_EXECFUNCS_HAVE_SYMTAB=y
CONFIG_EXECFUNCS_SYSTEM_SYMTAB=y CONFIG_EXECFUNCS_SYSTEM_SYMTAB=y
CONFIG_FAT_LCNAMES=y CONFIG_FAT_LCNAMES=y
@ -48,23 +53,33 @@ CONFIG_FS_PROCFS_REGISTER=y
CONFIG_FS_ROMFS=y CONFIG_FS_ROMFS=y
CONFIG_FS_TMPFS=y CONFIG_FS_TMPFS=y
CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_IMXRT_ADC2=y
CONFIG_IMXRT_ADC2_ETC=54
CONFIG_IMXRT_ENC1=y
CONFIG_IMXRT_ENET=y CONFIG_IMXRT_ENET=y
CONFIG_IMXRT_ENET_NRXBUFFERS=16
CONFIG_IMXRT_ENET_NTXBUFFERS=8
CONFIG_IMXRT_FLEXCAN1=y CONFIG_IMXRT_FLEXCAN1=y
CONFIG_IMXRT_FLEXCAN2=y CONFIG_IMXRT_FLEXCAN2=y
CONFIG_IMXRT_FLEXCAN3=y CONFIG_IMXRT_FLEXCAN3=y
CONFIG_IMXRT_FLEXCAN3_AS_CAN0=y CONFIG_IMXRT_FLEXCAN3_AS_CAN0=y
CONFIG_IMXRT_FLEXCAN_TXMB=1 CONFIG_IMXRT_FLEXCAN_TXMB=1
CONFIG_IMXRT_LPSPI4=y CONFIG_IMXRT_FLEXPWM1=y
CONFIG_IMXRT_FLEXPWM1_MOD4=y
CONFIG_IMXRT_FLEXPWM1_MOD4_TRIG=y
CONFIG_IMXRT_FLEXPWM2=y
CONFIG_IMXRT_FLEXPWM2_MOD3=y
CONFIG_IMXRT_FLEXPWM2_MOD3_SYNC_SRC=43
CONFIG_IMXRT_FLEXPWM3=y
CONFIG_IMXRT_FLEXPWM3_MOD2=y
CONFIG_IMXRT_FLEXPWM3_MOD2_SYNC_SRC=43
CONFIG_IMXRT_FLEXPWM4=y
CONFIG_IMXRT_FLEXPWM4_MOD3=y
CONFIG_IMXRT_FLEXPWM4_MOD3_SYNC_SRC=43
CONFIG_IMXRT_FLEXPWM4_MOD3_TRIG=y
CONFIG_IMXRT_FLEXPWM4_MOD3_TRIG_DUTY=y
CONFIG_IMXRT_LPUART1=y CONFIG_IMXRT_LPUART1=y
CONFIG_IMXRT_SNVS_LPSRTC=y CONFIG_IMXRT_SNVS_LPSRTC=y
CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INTELHEX_BINARY=y CONFIG_INTELHEX_BINARY=y
CONFIG_LCD=y
CONFIG_LCD_FRAMEBUFFER=y
CONFIG_LCD_PORTRAIT=y
CONFIG_LCD_ST7789=y
CONFIG_LIBC_DLFCN=y CONFIG_LIBC_DLFCN=y
CONFIG_LIBC_ENVPATH=y CONFIG_LIBC_ENVPATH=y
CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_EXECFUNCS=y
@ -84,6 +99,7 @@ CONFIG_NET_ARP_SEND=y
CONFIG_NET_BROADCAST=y CONFIG_NET_BROADCAST=y
CONFIG_NET_CAN=y CONFIG_NET_CAN=y
CONFIG_NET_CAN_SOCK_OPTS=y CONFIG_NET_CAN_SOCK_OPTS=y
CONFIG_NET_ETH_PKTSIZE=1518
CONFIG_NET_ICMP=y CONFIG_NET_ICMP=y
CONFIG_NET_ICMP_SOCKET=y CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_ICMPv6=y CONFIG_NET_ICMPv6=y
@ -122,18 +138,20 @@ CONFIG_PTHREAD_CLEANUP=y
CONFIG_PTHREAD_MUTEX_DEFAULT_PRIO_INHERIT=y CONFIG_PTHREAD_MUTEX_DEFAULT_PRIO_INHERIT=y
CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_PTHREAD_MUTEX_TYPES=y
CONFIG_PTHREAD_STACK_MIN=1024 CONFIG_PTHREAD_STACK_MIN=1024
CONFIG_PWM=y
CONFIG_RAM_SIZE=1048576 CONFIG_RAM_SIZE=1048576
CONFIG_RAM_START=0x20200000 CONFIG_RAM_START=0x20200000
CONFIG_READLINE_CMD_HISTORY=y CONFIG_READLINE_CMD_HISTORY=y
CONFIG_RR_INTERVAL=10 CONFIG_RR_INTERVAL=10
CONFIG_SCHED_CPULOAD=y CONFIG_SCHED_CPULOAD=y
CONFIG_SCHED_CPULOAD_EXTCLK=y
CONFIG_SCHED_LPWORK=y CONFIG_SCHED_LPWORK=y
CONFIG_SCHED_TICKLESS=y
CONFIG_SCHED_TICKLESS_ALARM=y
CONFIG_SCHED_USER_IDENTITY=y CONFIG_SCHED_USER_IDENTITY=y
CONFIG_SCHED_WAITPID=y CONFIG_SCHED_WAITPID=y
CONFIG_SENSORS=y
CONFIG_SENSORS_QENCODER=y
CONFIG_SERIAL_TERMIOS=y CONFIG_SERIAL_TERMIOS=y
CONFIG_SPI=y
CONFIG_SPI_CMDDATA=y
CONFIG_START_DAY=14 CONFIG_START_DAY=14
CONFIG_START_MONTH=3 CONFIG_START_MONTH=3
CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYMTAB_ORDEREDBYNAME=y
@ -145,5 +163,4 @@ CONFIG_SYSTEM_PING6=y
CONFIG_SYSTEM_PING=y CONFIG_SYSTEM_PING=y
CONFIG_SYSTEM_TEE=y CONFIG_SYSTEM_TEE=y
CONFIG_TEENSY_41=y CONFIG_TEENSY_41=y
CONFIG_USEC_PER_TICK=1000 CONFIG_TEENSY_41_PIKRON_BB=y
CONFIG_VIDEO_FB=y

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@ -281,6 +281,14 @@
#define GPIO_FLEXPWM2_MOD1_A (GPIO_FLEXPWM2_PWMA00_1|IOMUX_PWM_DEFAULT) /* GPIO_EMC_06 */ #define GPIO_FLEXPWM2_MOD1_A (GPIO_FLEXPWM2_PWMA00_1|IOMUX_PWM_DEFAULT) /* GPIO_EMC_06 */
#define GPIO_FLEXPWM2_MOD2_A (GPIO_FLEXPWM2_PWMA01_1|IOMUX_PWM_DEFAULT) /* GPIO_EMC_08 */ #define GPIO_FLEXPWM2_MOD2_A (GPIO_FLEXPWM2_PWMA01_1|IOMUX_PWM_DEFAULT) /* GPIO_EMC_08 */
/* FlexPWM setup for PMSM control - used in pikron-bb configuration */
#define GPIO_FLEXPWM3_MOD2_A (GPIO_FLEXPWM3_PWMA01_1 | IOMUX_PWM_DEFAULT) /* GPIO_EMC_31 */
#define GPIO_FLEXPWM2_MOD3_A (GPIO_FLEXPWM2_PWMA02_2 | IOMUX_PWM_DEFAULT) /* GPIO_B0_10 */
#define GPIO_FLEXPWM1_MOD4_A (GPIO_FLEXPWM1_PWMA03_5 | IOMUX_PWM_DEFAULT) /* GPIO_B1_00 */
#define GPIO_FLEXPWM4_MOD3_A (IOMUX_PWM_DEFAULT) /* PWM: ADC Trigger */
/**************************************************************************** /****************************************************************************
* Public Types * Public Types
****************************************************************************/ ****************************************************************************/

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@ -40,7 +40,11 @@
/* channels 1 and 2 have the same number of pins on Teensy */ /* channels 1 and 2 have the same number of pins on Teensy */
#ifdef CONFIG_TEENSY_41_PIKRON_BB
#define ADC_NCHANNELS 3
#else
#define ADC_NCHANNELS 16 #define ADC_NCHANNELS 16
#endif
/**************************************************************************** /****************************************************************************
* Private Data * Private Data
@ -48,7 +52,11 @@
static const uint8_t g_chanlist[ADC_NCHANNELS] = static const uint8_t g_chanlist[ADC_NCHANNELS] =
{ {
#ifdef CONFIG_TEENSY_41_PIKRON_BB
4, 2, 9
#else
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15
#endif
}; };
/**************************************************************************** /****************************************************************************

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@ -92,6 +92,8 @@ static const struct gpio_operations_s gpout_ops =
static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = static const uint32_t g_gpioinputs[BOARD_NGPIOIN] =
{ {
GPIO_IN1, GPIO_IN1,
GPIO_IN2,
GPIO_IN3,
}; };
static struct imxrtgpio_dev_s g_gpin[BOARD_NGPIOIN]; static struct imxrtgpio_dev_s g_gpin[BOARD_NGPIOIN];
@ -103,6 +105,9 @@ static struct imxrtgpio_dev_s g_gpin[BOARD_NGPIOIN];
static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] =
{ {
GPIO_OUT1, GPIO_OUT1,
GPIO_OUT2,
GPIO_OUT3,
GPIO_OUT4,
}; };
static struct imxrtgpio_dev_s g_gpout[BOARD_NGPIOOUT]; static struct imxrtgpio_dev_s g_gpout[BOARD_NGPIOOUT];

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@ -118,14 +118,30 @@
#define GPIO_ENC1_PHASE_B (GPIO_XBAR1_INOUT08_1|IOMUX_ENC_DEFAULT|PADMUX_MUXMODE_ALT3) /* EMC_06 */ #define GPIO_ENC1_PHASE_B (GPIO_XBAR1_INOUT08_1|IOMUX_ENC_DEFAULT|PADMUX_MUXMODE_ALT3) /* EMC_06 */
#define GPIO_ENC1_INDEX (GPIO_XBAR1_INOUT10_1|IOMUX_ENC_DEFAULT|PADMUX_MUXMODE_ALT1) /* B0_12 */ #define GPIO_ENC1_INDEX (GPIO_XBAR1_INOUT10_1|IOMUX_ENC_DEFAULT|PADMUX_MUXMODE_ALT1) /* B0_12 */
/* GPIO pins used by the GPIO subsystem */ /* GPIO pins used by the GPIO subsystem
* The following GPIOs are used for PMSM control in pikron-bb configuration.
*/
#define BOARD_NGPIOIN 1 /* Amount of GPIO input pins */ #define BOARD_NGPIOIN 3 /* Amount of GPIO input pins */
#define BOARD_NGPIOOUT 1 /* Amount of GPIO output pins */ #define BOARD_NGPIOOUT 4 /* Amount of GPIO output pins */
#define GPIO_IN1 (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN4) /* EMC_04 */
#define GPIO_OUT1 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \ #define GPIO_OUT1 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \
GPIO_PORT4 | GPIO_PIN5) /* EMC_05 */ GPIO_PORT3 | GPIO_PIN18) /* EMC_32 */
#define GPIO_OUT2 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \
GPIO_PORT2 | GPIO_PIN11) /* B0_11 */
#define GPIO_OUT3 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \
GPIO_PORT2 | GPIO_PIN17) /* B1_01 */
#define GPIO_OUT4 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \
GPIO_PORT4 | GPIO_PIN5) /* EMC_05 */
#define GPIO_IN1 (GPIO_INPUT| GPIO_PORT2 | GPIO_PIN19 | IOMUX_PULL_UP_100K | \
_IOMUX_PULL_ENABLE) /* B1_03 */
#define GPIO_IN2 (GPIO_INPUT| GPIO_PORT2 | GPIO_PIN18 | IOMUX_PULL_UP_100K | \
_IOMUX_PULL_ENABLE) /* B1_02 */
#define GPIO_IN3 (GPIO_INPUT| GPIO_PORT2 | GPIO_PIN0 | IOMUX_PULL_UP_100K | \
_IOMUX_PULL_ENABLE) /* B0_00 */
#define GPIO_IN4 (GPIO_INPUT| GPIO_PORT2 | GPIO_PIN2 | IOMUX_PULL_UP_100K | \
_IOMUX_PULL_ENABLE) /* B0_0 */
/**************************************************************************** /****************************************************************************
* Public Types * Public Types