From fdb149ddb0297f184cdce0d5911c772f58fbc579 Mon Sep 17 00:00:00 2001 From: Nathan Hartman <59230071+hartmannathan@users.noreply.github.com> Date: Tue, 31 Jan 2023 19:30:39 -0500 Subject: [PATCH] Kconfig: Improve help text related to *_SERIALBRK_BSDCOMPAT * arch/arm/src/gd32f4/Kconfig (GD32F4_SERIALBRK_BSDCOMPAT): Improve help text. * arch/arm/src/stm32/Kconfig (STM32_SERIALBRK_BSDCOMPAT): Improve help text. * arch/arm/src/stm32f7/Kconfig (STM32F7_SERIALBRK_BSDCOMPAT): Improve help text. * arch/arm/src/stm32h7/Kconfig (STM32H7_SERIALBRK_BSDCOMPAT): Improve help text. * arch/arm/src/stm32l4/Kconfig (STM32L4_SERIALBRK_BSDCOMPAT): Improve help text. * arch/arm/src/stm32l5/Kconfig (STM32L5_SERIALBRK_BSDCOMPAT): Improve help text. * arch/arm/src/stm32u5/Kconfig (STM32U5_SERIALBRK_BSDCOMPAT): Improve help text. * arch/arm/src/stm32wb/Kconfig (STM32WB_SERIALBRK_BSDCOMPAT): Improve help text. --- arch/arm/src/gd32f4/Kconfig | 7 ++++--- arch/arm/src/stm32/Kconfig | 7 ++++--- arch/arm/src/stm32f7/Kconfig | 7 ++++--- arch/arm/src/stm32h7/Kconfig | 7 ++++--- arch/arm/src/stm32l4/Kconfig | 7 ++++--- arch/arm/src/stm32l5/Kconfig | 7 ++++--- arch/arm/src/stm32u5/Kconfig | 7 ++++--- arch/arm/src/stm32wb/Kconfig | 7 ++++--- 8 files changed, 32 insertions(+), 24 deletions(-) diff --git a/arch/arm/src/gd32f4/Kconfig b/arch/arm/src/gd32f4/Kconfig index 7490a75c80..439a14e22e 100644 --- a/arch/arm/src/gd32f4/Kconfig +++ b/arch/arm/src/gd32f4/Kconfig @@ -1985,9 +1985,10 @@ config GD32F4_SERIALBRK_BSDCOMPAT ---help--- Enable using GPIO on the TX pin to send a BSD compatible break: TIOCSBRK will start the break and TIOCCBRK will end the break. - The current GD32F4 USARTS have no way to leave the break (TX=LOW) - on because the software starts the break and then the hadware automatically - clears the break. This makes it is difficult to sent a long break. + The current GD32F4 USARTS have no way to leave the break on + (TX=LOW) because software starts the break and then the hardware + automatically clears the break. This makes it difficult to send + a long break. config GD32F4_USART_SINGLEWIRE bool "Single Wire Support" diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index d2a5e85e53..2381d25567 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -10298,9 +10298,10 @@ config STM32_SERIALBRK_BSDCOMPAT ---help--- Enable using GPIO on the TX pin to send a BSD compatible break: TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32 U[S]ARTS have no way to leave the break (TX=LOW) - on because the SW starts the break and then the HW automatically clears - the break. This makes it is difficult to sent a long break. + The current STM32 U[S]ARTS have no way to leave the break on + (TX=LOW) because software starts the break and then the hardware + automatically clears the break. This makes it difficult to send + a long break. config STM32_USART_SINGLEWIRE bool "Single Wire Support" diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index 74b732b701..e062b5453f 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -2085,9 +2085,10 @@ config STM32F7_SERIALBRK_BSDCOMPAT ---help--- Enable using GPIO on the TX pin to send a BSD compatible break: TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32 U[S]ARTS have no way to leave the break (TX=LOW) - on because the SW starts the break and then the HW automatically clears - the break. This makes it is difficult to sent a long break. + The current STM32F7 U[S]ARTS have no way to leave the break on + (TX=LOW) because software starts the break and then the hardware + automatically clears the break. This makes it difficult to send + a long break. config STM32F7_USART_SINGLEWIRE bool "Single Wire Support" diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index 3353ee52df..b39ca7dd66 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -1545,9 +1545,10 @@ config STM32H7_SERIALBRK_BSDCOMPAT ---help--- Enable using GPIO on the TX pin to send a BSD compatible break: TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32 U[S]ARTS have no way to leave the break (TX=LOW) - on because the SW starts the break and then the HW automatically clears - the break. This makes it is difficult to sent a long break. + The current STM32H7 U[S]ARTS have no way to leave the break on + (TX=LOW) because software starts the break and then the hardware + automatically clears the break. This makes it difficult to send + a long break. config STM32H7_USART_SINGLEWIRE bool "Single Wire Support" diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index 2c5d208cb9..5a0f8e2316 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -5953,9 +5953,10 @@ config STM32L4_SERIALBRK_BSDCOMPAT ---help--- Enable using GPIO on the TX pin to send a BSD compatible break: TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32 U[S]ARTS have no way to leave the break (TX=LOW) - on because the SW starts the break and then the HW automatically clears - the break. This makes it is difficult to sent a long break. + The current STM32L4 U[S]ARTS have no way to leave the break on + (TX=LOW) because software starts the break and then the hardware + automatically clears the break. This makes it difficult to send + a long break. config STM32L4_USART_SINGLEWIRE bool "Single Wire Support" diff --git a/arch/arm/src/stm32l5/Kconfig b/arch/arm/src/stm32l5/Kconfig index a1821de9ae..a7516b0b90 100644 --- a/arch/arm/src/stm32l5/Kconfig +++ b/arch/arm/src/stm32l5/Kconfig @@ -2863,9 +2863,10 @@ config STM32L5_SERIALBRK_BSDCOMPAT ---help--- Enable using GPIO on the TX pin to send a BSD compatible break: TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32 U[S]ARTS have no way to leave the break (TX=LOW) - on because the SW starts the break and then the HW automatically clears - the break. This makes it is difficult to sent a long break. + The current STM32L5 U[S]ARTS have no way to leave the break on + (TX=LOW) because software starts the break and then the hardware + automatically clears the break. This makes it difficult to send + a long break. config STM32L5_USART_SINGLEWIRE bool "Single Wire Support" diff --git a/arch/arm/src/stm32u5/Kconfig b/arch/arm/src/stm32u5/Kconfig index 6b4e0716b2..990a8047d6 100644 --- a/arch/arm/src/stm32u5/Kconfig +++ b/arch/arm/src/stm32u5/Kconfig @@ -3109,9 +3109,10 @@ config STM32U5_SERIALBRK_BSDCOMPAT ---help--- Enable using GPIO on the TX pin to send a BSD compatible break: TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32 U[S]ARTS have no way to leave the break (TX=LOW) - on because the SW starts the break and then the HW automatically clears - the break. This makes it is difficult to sent a long break. + The current STM32U5 U[S]ARTS have no way to leave the break on + (TX=LOW) because software starts the break and then the hardware + automatically clears the break. This makes it difficult to send + a long break. config STM32U5_USART_SINGLEWIRE bool "Single Wire Support" diff --git a/arch/arm/src/stm32wb/Kconfig b/arch/arm/src/stm32wb/Kconfig index 36da938c9e..51063c6c84 100644 --- a/arch/arm/src/stm32wb/Kconfig +++ b/arch/arm/src/stm32wb/Kconfig @@ -891,9 +891,10 @@ config STM32WB_SERIALBRK_BSDCOMPAT ---help--- Enable using GPIO on the TX pin to send a BSD compatible break: TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32WB U[S]ARTS have no way to leave the break (TX=LOW) - on because the SW starts the break and then the HW automatically clears - the break. This makes it is difficult to sent a long break. + The current STM32WB U[S]ARTS have no way to leave the break on + (TX=LOW) because software starts the break and then the hardware + automatically clears the break. This makes it difficult to send + a long break. config STM32WB_USART_SINGLEWIRE bool "Single Wire Support"