Add PSRAM board config test and update README
This commit is contained in:
Alan C. Assis
Abdelatif Guettouche
parent
dfb626a215
commit
fdc44dc6fc
@ -81,4 +81,82 @@ config PM_ALARM_NSEC
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endif # PM
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if ESP32_SPIRAM
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menu "PSRAM clock and cs IO for ESP32-DOWD"
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config D0WD_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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range 0 33
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default 17
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help
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The PSRAM CLOCK IO can be any unused GPIO, user can config it
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based on hardware design. If user use 1.8V flash and 1.8V psram,
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this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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config D0WD_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 16
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based
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on hardware design. If user use 1.8V flash and 1.8V psram, this
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value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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endmenu
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menu "PSRAM clock and cs IO for ESP32-D2WD"
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config D2WD_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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range 0 33
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default 9
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help
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User can config it based on hardware design. For ESP32-D2WD chip,
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the psram can only be 1.8V psram, so this value can only be one
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of 6, 7, 8, 9, 10, 11, 16, 17.
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config D2WD_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 10
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help
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User can config it based on hardware design. For ESP32-D2WD chip,
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the psram can only be 1.8V psram, so this value can only be one
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of 6, 7, 8, 9, 10, 11, 16, 17.
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endmenu
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menu "PSRAM clock and cs IO for ESP32-PICO"
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config PICO_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 10
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based on
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hardware design.
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For ESP32-PICO chip, the psram share clock with flash, so user do
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not need to configure the clock IO.
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For the reference hardware design, please refer to
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https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
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endmenu
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config ESP32_SPIRAM_SPIWP_SD3_PIN
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int "SPI PSRAM WP(SD3) Pin when customising pins via eFuse (read help)"
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range 0 33
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default 7
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help
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This value is ignored unless flash mode is set to DIO or DOUT and
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the SPI flash pins have been overriden by setting the eFuses
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SPI_PAD_CONFIG_xxx.
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When this is the case, the eFuse config only defines 3 of the 4
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Quad I/O data pins. The WP pin (aka ESP32 pin "SD_DATA_3" or SPI
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flash pin "IO2") is not specified in eFuse. And the psram only
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has QPI mode, the WP pin is necessary, so we need to configure
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this value here.
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When flash mode is set to QIO or QOUT, the PSRAM WP pin will be
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set as the value configured in bootloader.
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For ESP32-PICO chip, the default value of this config should be 7.
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endif # ESP32_PSRAM
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endif # ARCH_BOARD_ESP32CORE
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@ -794,6 +794,21 @@ NOTES:
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Note that mksmartfs is only needed the first time.
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psram:
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This config tests the PSRAM driver over SPIRAM interface.
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You can use the ramtest command to test the PSRAM memory. We are testing
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only 64KB on this example (64 * 1024), but you can change this number to
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2MB or 4MB depending on PSRAM chip used on your board:
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nsh> ramtest -w 0x3F800000 65536
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RAMTest: Marching ones: 3f800000 65536
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RAMTest: Marching zeroes: 3f800000 65536
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RAMTest: Pattern test: 3f800000 65536 55555555 aaaaaaaa
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RAMTest: Pattern test: 3f800000 65536 66666666 99999999
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RAMTest: Pattern test: 3f800000 65536 33333333 cccccccc
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RAMTest: Address-in-address test: 3f800000 65536
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Things to Do
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============
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81
boards/xtensa/esp32/esp32-core/configs/psram/defconfig
Normal file
81
boards/xtensa/esp32/esp32-core/configs/psram/defconfig
Normal file
@ -0,0 +1,81 @@
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#
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# This file is autogenerated: PLEASE DO NOT EDIT IT.
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#
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# You can use "make menuconfig" to make any modifications to the installed .config file.
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# You can then do "make savedefconfig" to generate a new defconfig file that includes your
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# modifications.
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#
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# CONFIG_NSH_ARGCAT is not set
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# CONFIG_NSH_CMDOPT_HEXDUMP is not set
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# CONFIG_NSH_CMDPARMS is not set
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CONFIG_ARCH="xtensa"
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CONFIG_ARCH_BOARD="esp32-core"
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CONFIG_ARCH_BOARD_ESP32CORE=y
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CONFIG_ARCH_CHIP="esp32"
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CONFIG_ARCH_CHIP_ESP32=y
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_ARCH_XTENSA=y
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CONFIG_BOARD_LOOPSPERMSEC=16717
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CONFIG_BUILTIN=y
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CONFIG_DEBUG_ERROR=y
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CONFIG_DEBUG_FEATURES=y
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CONFIG_DEBUG_INFO=y
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CONFIG_DEBUG_WARN=y
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CONFIG_DEV_ZERO=y
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CONFIG_ESP32_EMAC=y
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CONFIG_ESP32_SPIRAM=y
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CONFIG_ESP32_UART0=y
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CONFIG_EXPERIMENTAL=y
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CONFIG_FS_PROCFS=y
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CONFIG_HAVE_CXX=y
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CONFIG_HAVE_CXXINITIALIZE=y
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CONFIG_HEAP2_BASE=0x3F800000
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CONFIG_HEAP2_SIZE=4194304
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CONFIG_IDLETHREAD_STACKSIZE=3072
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CONFIG_INTELHEX_BINARY=y
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CONFIG_MAX_TASKS=16
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CONFIG_MM_REGIONS=2
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CONFIG_NETDB_DNSCLIENT=y
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CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x08080808
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CONFIG_NETDB_HOSTFILE=y
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CONFIG_NETDEVICES=y
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CONFIG_NETDEV_PHY_IOCTL=y
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CONFIG_NETINIT_DRIPADDR=0xc0a80f01
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CONFIG_NETINIT_IPADDR=0xc0a80f64
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CONFIG_NETINIT_THREAD=y
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CONFIG_NETUTILS_TELNETD=y
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CONFIG_NETUTILS_TFTPC=y
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CONFIG_NETUTILS_WEBCLIENT=y
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CONFIG_NET_ARP_SEND=y
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CONFIG_NET_BROADCAST=y
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CONFIG_NET_ICMP=y
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CONFIG_NET_ICMP_SOCKET=y
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CONFIG_NET_TCP=y
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CONFIG_NET_TCPBACKLOG=y
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CONFIG_NET_TCP_WRITE_BUFFERS=y
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CONFIG_NET_UDP=y
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CONFIG_NFILE_DESCRIPTORS=8
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CONFIG_NSH_ARCHINIT=y
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CONFIG_NSH_BUILTIN_APPS=y
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CONFIG_NSH_FILEIOSIZE=512
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CONFIG_NSH_LINELEN=64
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CONFIG_NSH_READLINE=y
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CONFIG_PREALLOC_TIMERS=4
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CONFIG_RAM_SIZE=114688
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CONFIG_RAM_START=0x20000000
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CONFIG_RAW_BINARY=y
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CONFIG_RR_INTERVAL=200
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CONFIG_SCHED_HPWORK=y
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CONFIG_SCHED_WAITPID=y
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CONFIG_SDCLONE_DISABLE=y
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CONFIG_SPI=y
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CONFIG_START_DAY=6
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CONFIG_START_MONTH=12
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CONFIG_START_YEAR=2011
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CONFIG_SUPPRESS_CLOCK_CONFIG=y
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CONFIG_SUPPRESS_UART_CONFIG=y
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CONFIG_SYSTEM_NSH=y
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CONFIG_SYSTEM_PING=y
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CONFIG_SYSTEM_RAMTEST=y
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CONFIG_UART0_SERIAL_CONSOLE=y
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CONFIG_USER_ENTRYPOINT="nsh_main"
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@ -1820,6 +1820,7 @@ PROVIDE ( Xthal_intlevel = 0x3ff9c2b4 );
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PROVIDE ( xthal_memcpy = 0x4000c0bc );
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PROVIDE ( xthal_set_ccompare = 0x4000c058 );
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PROVIDE ( xthal_set_intclear = 0x4000c1ec );
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PROVIDE ( esp_rom_spiflash_config_clk = 0x40062bc8 );
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PROVIDE ( _xtos_alloca_handler = 0x40000010 );
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PROVIDE ( _xtos_cause3_handler = 0x40000dd8 );
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PROVIDE ( _xtos_c_handler_table = 0x3ffe0548 );
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