diff --git a/boards/xtensa/esp32/esp32-core/Kconfig b/boards/xtensa/esp32/esp32-core/Kconfig index 6371130e48..75038a1d44 100644 --- a/boards/xtensa/esp32/esp32-core/Kconfig +++ b/boards/xtensa/esp32/esp32-core/Kconfig @@ -81,4 +81,82 @@ config PM_ALARM_NSEC endif # PM +if ESP32_SPIRAM + +menu "PSRAM clock and cs IO for ESP32-DOWD" +config D0WD_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 17 + help + The PSRAM CLOCK IO can be any unused GPIO, user can config it + based on hardware design. If user use 1.8V flash and 1.8V psram, + this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +config D0WD_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 16 + help + The PSRAM CS IO can be any unused GPIO, user can config it based + on hardware design. If user use 1.8V flash and 1.8V psram, this + value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. +endmenu + +menu "PSRAM clock and cs IO for ESP32-D2WD" +config D2WD_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 9 + help + User can config it based on hardware design. For ESP32-D2WD chip, + the psram can only be 1.8V psram, so this value can only be one + of 6, 7, 8, 9, 10, 11, 16, 17. + +config D2WD_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 10 + help + User can config it based on hardware design. For ESP32-D2WD chip, + the psram can only be 1.8V psram, so this value can only be one + of 6, 7, 8, 9, 10, 11, 16, 17. +endmenu + +menu "PSRAM clock and cs IO for ESP32-PICO" +config PICO_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 10 + help + The PSRAM CS IO can be any unused GPIO, user can config it based on + hardware design. + For ESP32-PICO chip, the psram share clock with flash, so user do + not need to configure the clock IO. + For the reference hardware design, please refer to + https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf +endmenu + +config ESP32_SPIRAM_SPIWP_SD3_PIN + int "SPI PSRAM WP(SD3) Pin when customising pins via eFuse (read help)" + range 0 33 + default 7 + help + This value is ignored unless flash mode is set to DIO or DOUT and + the SPI flash pins have been overriden by setting the eFuses + SPI_PAD_CONFIG_xxx. + + When this is the case, the eFuse config only defines 3 of the 4 + Quad I/O data pins. The WP pin (aka ESP32 pin "SD_DATA_3" or SPI + flash pin "IO2") is not specified in eFuse. And the psram only + has QPI mode, the WP pin is necessary, so we need to configure + this value here. + + When flash mode is set to QIO or QOUT, the PSRAM WP pin will be + set as the value configured in bootloader. + + For ESP32-PICO chip, the default value of this config should be 7. + +endif # ESP32_PSRAM + endif # ARCH_BOARD_ESP32CORE diff --git a/boards/xtensa/esp32/esp32-core/README.txt b/boards/xtensa/esp32/esp32-core/README.txt index 36c68ba45b..c8d68bae0c 100644 --- a/boards/xtensa/esp32/esp32-core/README.txt +++ b/boards/xtensa/esp32/esp32-core/README.txt @@ -794,6 +794,21 @@ NOTES: Note that mksmartfs is only needed the first time. + psram: + + This config tests the PSRAM driver over SPIRAM interface. + You can use the ramtest command to test the PSRAM memory. We are testing + only 64KB on this example (64 * 1024), but you can change this number to + 2MB or 4MB depending on PSRAM chip used on your board: + + nsh> ramtest -w 0x3F800000 65536 + RAMTest: Marching ones: 3f800000 65536 + RAMTest: Marching zeroes: 3f800000 65536 + RAMTest: Pattern test: 3f800000 65536 55555555 aaaaaaaa + RAMTest: Pattern test: 3f800000 65536 66666666 99999999 + RAMTest: Pattern test: 3f800000 65536 33333333 cccccccc + RAMTest: Address-in-address test: 3f800000 65536 + Things to Do ============ diff --git a/boards/xtensa/esp32/esp32-core/configs/psram/defconfig b/boards/xtensa/esp32/esp32-core/configs/psram/defconfig new file mode 100644 index 0000000000..30112e74b8 --- /dev/null +++ b/boards/xtensa/esp32/esp32-core/configs/psram/defconfig @@ -0,0 +1,81 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32-core" +CONFIG_ARCH_BOARD_ESP32CORE=y +CONFIG_ARCH_CHIP="esp32" +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ERROR=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_WARN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32_EMAC=y +CONFIG_ESP32_SPIRAM=y +CONFIG_ESP32_UART0=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0x3F800000 +CONFIG_HEAP2_SIZE=4194304 +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=16 +CONFIG_MM_REGIONS=2 +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x08080808 +CONFIG_NETDB_HOSTFILE=y +CONFIG_NETDEVICES=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETINIT_DRIPADDR=0xc0a80f01 +CONFIG_NETINIT_IPADDR=0xc0a80f64 +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_TCP=y +CONFIG_NET_TCPBACKLOG=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SUPPRESS_CLOCK_CONFIG=y +CONFIG_SUPPRESS_UART_CONFIG=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_RAMTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/xtensa/esp32/esp32-core/scripts/esp32_rom.ld b/boards/xtensa/esp32/esp32-core/scripts/esp32_rom.ld index 479d1181c0..a315c014bc 100644 --- a/boards/xtensa/esp32/esp32-core/scripts/esp32_rom.ld +++ b/boards/xtensa/esp32/esp32-core/scripts/esp32_rom.ld @@ -1820,6 +1820,7 @@ PROVIDE ( Xthal_intlevel = 0x3ff9c2b4 ); PROVIDE ( xthal_memcpy = 0x4000c0bc ); PROVIDE ( xthal_set_ccompare = 0x4000c058 ); PROVIDE ( xthal_set_intclear = 0x4000c1ec ); +PROVIDE ( esp_rom_spiflash_config_clk = 0x40062bc8 ); PROVIDE ( _xtos_alloca_handler = 0x40000010 ); PROVIDE ( _xtos_cause3_handler = 0x40000dd8 ); PROVIDE ( _xtos_c_handler_table = 0x3ffe0548 );