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Fix Cortex-A CPSR register field definition

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This commit is contained in:
Gregory Nutt 2013-07-30 19:05:24 -06:00
parent bfa1a9545b
commit fde3777e9e
4 changed files with 28 additions and 23 deletions
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10
arch/arm/src/arm/up_vectors.S
View File

@ -139,7 +139,7 @@ up_vectorirq:
bl up_decodeirq /* Call the handler */
#endif
/* Restore the CPSR, SVC modr registers and return */
/* Restore the CPSR, SVC mode registers and return */
.Lnoirqset:
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
msr spsr, r0
@ -192,7 +192,7 @@ up_vectorswi:
mov r0, sp /* Get r0=xcp */
bl up_syscall /* Call the handler */
/* Restore the CPSR, SVC modr registers and return */
/* Restore the CPSR, SVC mode registers and return */
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
msr spsr, r0
@ -263,7 +263,7 @@ up_vectordata:
#endif
bl up_dataabort /* Call the handler */
/* Restore the CPSR, SVC modr registers and return */
/* Restore the CPSR, SVC mode registers and return */
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
msr spsr_cxsf, r0
@ -333,7 +333,7 @@ up_vectorprefetch:
mov r0, sp /* Get r0=xcp */
bl up_prefetchabort /* Call the handler */
/* Restore the CPSR, SVC modr registers and return */
/* Restore the CPSR, SVC mode registers and return */
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
msr spsr_cxsf, r0
@ -400,7 +400,7 @@ up_vectorundefinsn:
mov r0, sp /* Get r0=xcp */
bl up_undefinedinsn /* Call the handler */
/* Restore the CPSR, SVC modr registers and return */
/* Restore the CPSR, SVC mode registers and return */
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
msr spsr_cxsf, r0

2
arch/arm/src/armv7-a/arm.h
View File

@ -57,7 +57,7 @@
/* PSR bits */
#define PSR_MODE_SHIFT (1) /* Bits 0-4: Mode fields */
#define PSR_MODE_SHIFT (0) /* Bits 0-4: Mode fields */
#define PSR_MODE_MASK (31 << PSR_MODE_SHIFT)
# define PSR_MODE_USR (16 << PSR_MODE_SHIFT) /* User mode */
# define PSR_MODE_FIQ (17 << PSR_MODE_SHIFT) /* FIQ mode */

8
arch/arm/src/armv7-a/arm_vectors.S
View File

@ -215,7 +215,7 @@ arm_vectorswi:
* context switch is required.
*/
/* Restore the CPSR, SVC modr registers and return */
/* Restore the CPSR, SVC mode registers and return */
ldr r1, [r0, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
msr spsr, r1
@ -294,7 +294,7 @@ arm_vectordata:
* context switch is required.
*/
/* Restore the CPSR, SVC modr registers and return */
/* Restore the CPSR, SVC mode registers and return */
ldr r1, [r0, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
msr spsr_cxsf, r1
@ -376,7 +376,7 @@ arm_vectorprefetch:
* context switch is required.
*/
/* Restore the CPSR, SVC modr registers and return */
/* Restore the CPSR, SVC mode registers and return */
ldr r1, [r0, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
msr spsr_cxsf, r1
@ -453,7 +453,7 @@ arm_vectorundefinsn:
* context switch is required.
*/
/* Restore the CPSR, SVC modr registers and return */
/* Restore the CPSR, SVC mode registers and return */
ldr r1, [r0, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
msr spsr_cxsf, r1

31
arch/arm/src/sama5/sam_timerisr.c
View File

@ -48,6 +48,7 @@
#include <arch/board/board.h>
#include "up_arch.h"
#include "sam_periphclks.h"
#include "chip/sam_pit.h"
/****************************************************************************
@ -100,23 +101,23 @@
int up_timerisr(int irq, uint32_t *regs)
{
/* "When CPIV and PICNT values are obtained by reading the Periodic
* Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is
* reset and the PITS is cleared, thus acknowledging the interrupt. The
* value of PICNT gives the number of periodic intervals elapsed since the
* last read of PIT_PIVR.
*/
/* "When CPIV and PICNT values are obtained by reading the Periodic
* Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is
* reset and the PITS is cleared, thus acknowledging the interrupt. The
* value of PICNT gives the number of periodic intervals elapsed since the
* last read of PIT_PIVR.
*/
uint32_t picnt = getreg32(SAM_PIT_PIVR) >> PIT_PICNT_SHIFT;
uint32_t picnt = getreg32(SAM_PIT_PIVR) >> PIT_PICNT_SHIFT;
/* Process timer interrupt (multiple times if we missed an interrupt) */
/* Process timer interrupt (multiple times if we missed an interrupt) */
while (picnt-- > 0)
{
sched_process_timer();
}
while (picnt-- > 0)
{
sched_process_timer();
}
return OK;
return OK;
}
/****************************************************************************
@ -132,6 +133,10 @@ void up_timerinit(void)
{
uint32_t regval;
/* Enable the PIT peripheral */
sam_pit_enableclk();
/* Make sure that interrupts from the PIT are disabled */
up_disable_irq(SAM_IRQ_PIT);