sergiotarxz/nuttx
sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

arch: renesas: nxstyle fixes

Browse Source 
Nxstyle fixes to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea 2021-03-30 13:10:19 +02:00 committed by David Sidrane
parent 0ae3469782
commit fe0ee48c69
16 changed files with 127 additions and 97 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/renesas/include/m16c/irq.h
View File

@ -222,6 +222,7 @@
/************************************************************************************
* Public Types
************************************************************************************/
/* This struct defines the way the registers are stored. We need to save: */
#ifndef __ASSEMBLY__
@ -323,7 +324,7 @@ static inline irqstate_t up_irq_enable(void)
#endif
/************************************************************************************
* Public Functions
* Public Functions Prototypes
************************************************************************************/
#undef EXTERN

10
arch/renesas/include/sh1/irq.h
View File

@ -274,6 +274,7 @@
#define SH1_NMI_VNDX (11) /* 11: NMI */
#define SH1_USRBRK_VNDX (12) /* 12: User break */
/* 13-31: Reserved for system */
/* Trap instruction */
#define SH1_TRAP_VNDX (32) /* 32-63: TRAPA instruction (user break) */
@ -343,6 +344,7 @@
#define SH1_DMAC3_VNDX (78) /* 78-79: DMAC3 */
#define SH1_DEI3_VNDX (78) /* 78: DMAC3 DEI3 */
/* 79: Reserved */
/* ITU */
#define SH1_IMIA0_VNDX (80) /* 80: ITU0 IMIA0 */
@ -365,6 +367,7 @@
#define SH1_IMIB4_VNDX (97) /* 97: IMIB4 */
#define SH1_OVI4_VNDX (98) /* 98: OVI4 */
/* 99: Reserved */
/* SCI */
#define SH1_ERI0_VNDX (100) /* 100: SCI0 ERI0 */
@ -383,14 +386,15 @@
#define SH1_WDTITI_VNDX (112) /* 112: WDT ITI */
#define SH1_CMI_VNDX (113) /* 113: REF CMI */
/* 114-115: Reserved */
/* 116-255 reserved */
#endif
#define SH1_LAST_VNDX (255)
#define SH1_NVECTORS (256)
/* IRQ Stack Frame Format. The SH-1 has a push down stack. The PC
* and SR are pushed by hardware at the time an IRQ is taken.
/* IRQ Stack Frame Format. The SH-1 has a push down stack.
* The PC and SR are pushed by hardware at the time an IRQ is taken.
*/
/* Saved to the stacked by up_vector */
@ -544,7 +548,7 @@ static inline void up_irq_restore(irqstate_t flags)
#endif
/************************************************************************************
* Public Functions
* Public Functions Prototypes
************************************************************************************/
#undef EXTERN

2
arch/renesas/src/common/up_allocateheap.c
View File

@ -67,6 +67,6 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
}

2
arch/renesas/src/common/up_interruptcontext.c
View File

@ -51,5 +51,5 @@
bool up_interrupt_context(void)
{
return g_current_regs != NULL;
return g_current_regs != NULL;
}

6
arch/renesas/src/common/up_mdelay.c
View File

@ -68,8 +68,8 @@ void up_mdelay(unsigned int milliseconds)
for (i = 0; i < milliseconds; i++)
{
for (j = 0; j < CONFIG_BOARD_LOOPSPERMSEC; j++)
{
}
for (j = 0; j < CONFIG_BOARD_LOOPSPERMSEC; j++)
{
}
}
}

4
arch/renesas/src/common/up_udelay.c
View File

@ -85,6 +85,7 @@ void up_udelay(useconds_t microseconds)
for (i = 0; i < CONFIG_BOARD_LOOPSPERMSEC; i++)
{
}
microseconds -= 1000;
}
@ -93,6 +94,7 @@ void up_udelay(useconds_t microseconds)
for (i = 0; i < CONFIG_BOARD_LOOPSPER100USEC; i++)
{
}
microseconds -= 100;
}
@ -101,6 +103,7 @@ void up_udelay(useconds_t microseconds)
for (i = 0; i < CONFIG_BOARD_LOOPSPER10USEC; i++)
{
}
microseconds -= 10;
}
@ -109,6 +112,7 @@ void up_udelay(useconds_t microseconds)
for (i = 0; i < CONFIG_BOARD_LOOPSPERUSEC; i++)
{
}
microseconds--;
}
}

2
arch/renesas/src/m16c/m16c_irq.c
View File

@ -31,7 +31,7 @@
#include "up_internal.h"
/****************************************************************************
* Public Data
* Public Functions
****************************************************************************/
/* This holds a references to the current interrupt level register storage

18
arch/renesas/src/m16c/m16c_lowputc.c
View File

@ -38,7 +38,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration **********************************************************/
/* Configuration ************************************************************/
#ifndef M16C_XIN_PRESCALER
# define M16C_XIN_PRESCALER 1
@ -138,7 +138,7 @@
#define M16C_MR_VALUE (M16C_MR_SMDBITS|M16C_MR_PARITY|M16C_MR_STOPBITS)
/* Clocking ***************************************************************/
/* Clocking *****************************************************************/
/* The Bit Rate Generator (BRG) value can be calculated by:
*
@ -222,25 +222,27 @@ static inline void up_lowserialsetup(void)
putreg8(0, M16C_UCON);
#endif
/* Set interrupt cause=TX complete and continuous receive mode */
/* Set interrupt cause=TX complete and continuous receive mode */
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
regval = getreg8(M16C_UCON);
regval |= (UART_CON_U0IRS|UART_CON_U0RRM);
regval |= (UART_CON_U0IRS | UART_CON_U0RRM);
putreg8(regval, M16C_UCON);
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
regval = getreg8(M16C_UCON);
regval |= (UART_CON_U1IRS|UART_CON_U1RRM);
regval |= (UART_CON_U1IRS | UART_CON_U1RRM);
putreg8(regval, M16C_UCON);
#else
regval = getreg8(M16C_U2C1);
regval |= (UART_C1_U2IRS|UART_C1_U2RRM);
regval |= (UART_C1_U2IRS | UART_C1_U2RRM);
putreg8(regval, M16C_U2C1);
#endif
/* Set UART transmit/receive control register 1 to enable transmit and receive */
/* Set UART transmit/receive control register 1 to enable transmit and
* receive
*/
putreg8(UART_C1_TE|UART_C1_RE, M16C_UART_BASE + M16C_UART_C1);
putreg8(UART_C1_TE | UART_C1_RE, M16C_UART_BASE + M16C_UART_C1);
/* Set UART transmit/receive mode register data bits, stop bits, parity */

139
arch/renesas/src/m16c/m16c_serial.c
View File

@ -51,7 +51,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration **********************************************************/
/* Configuration ************************************************************/
#ifndef M16C_XIN_PRESCALER
# define M16C_XIN_PRESCALER 1
@ -60,22 +60,22 @@
/* Make sure interrupt priorities are defined. If not, use a default of 5 */
#ifndef M16C_S2T_PRIO
# define M16C_S2T_PRIO 5 /* UART2 transmit interrupt priority */
# define M16C_S2T_PRIO 5 /* UART2 transmit interrupt priority */
#endif
#ifndef M16C_S2R_PRIO
# define M16C_S2R_PRIO 5 /* UART2 receive interrupt priority */
# define M16C_S2R_PRIO 5 /* UART2 receive interrupt priority */
#endif
#ifndef M16C_S0T_PRIO
# define M16C_S0T_PRIO 5 /* UART0 transmit interrupt priority */
# define M16C_S0T_PRIO 5 /* UART0 transmit interrupt priority */
#endif
#ifndef M16C_S0R_PRIO
# define M16C_S0R_PRIO 5 /* UART0 receive interrupt priority */
# define M16C_S0R_PRIO 5 /* UART0 receive interrupt priority */
#endif
#ifndef M16C_S1T_PRIO
# define M16C_S1T_PRIO 5 /* UART1 transmit interrupt priority */
# define M16C_S1T_PRIO 5 /* UART1 transmit interrupt priority */
#endif
#ifndef M16C_S1R_PRIO
# define M16C_S1R_PRIO 5 /* UART1 receive interrupt priority */
# define M16C_S1R_PRIO 5 /* UART1 receive interrupt priority */
#endif
/* Some sanity checks *******************************************************/
@ -229,17 +229,17 @@ elif defined(CONFIG_M16C_UART1)
struct up_dev_s
{
uint32_t baud; /* Configured baud */
uint16_t uartbase; /* Base address of UART registers */
uint8_t uartno; /* UART number */
volatile uint8_t ucon; /* Saved SCR value */
volatile uint8_t ssr; /* Saved SR value (only used during interrupt processing) */
uint8_t rcvirq; /* UART receive data available IRQ */
uint8_t xmtirq; /* UART transmit complete IRQ */
uint8_t enables; /* Bit 0: 1=RX enabled, Bit 1: 1=TX enabled */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (7 or 8) */
bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
uint32_t baud; /* Configured baud */
uint16_t uartbase; /* Base address of UART registers */
uint8_t uartno; /* UART number */
volatile uint8_t ucon; /* Saved SCR value */
volatile uint8_t ssr; /* Saved SR value (only used during interrupt processing) */
uint8_t rcvirq; /* UART receive data available IRQ */
uint8_t xmtirq; /* UART transmit complete IRQ */
uint8_t enables; /* Bit 0: 1=RX enabled, Bit 1: 1=TX enabled */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (7 or 8) */
bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
};
/****************************************************************************
@ -348,15 +348,15 @@ static struct up_dev_s g_uart1priv =
static uart_dev_t g_uart1port =
{
.recv =
{
.size = CONFIG_UART1_RXBUFSIZE,
.buffer = g_uart1rxbuffer,
},
{
.size = CONFIG_UART1_RXBUFSIZE,
.buffer = g_uart1rxbuffer,
},
.xmit =
{
.size = CONFIG_UART1_TXBUFSIZE,
.buffer = g_uart1txbuffer,
},
{
.size = CONFIG_UART1_TXBUFSIZE,
.buffer = g_uart1txbuffer,
},
.ops = &g_uart_ops,
.priv = &g_uart1priv,
};
@ -380,15 +380,15 @@ static struct up_dev_s g_uart2priv =
static uart_dev_t g_uart2port =
{
.recv =
{
.size = CONFIG_UART2_RXBUFSIZE,
.buffer = g_uart2rxbuffer,
},
{
.size = CONFIG_UART2_RXBUFSIZE,
.buffer = g_uart2rxbuffer,
},
.xmit =
{
.size = CONFIG_UART2_TXBUFSIZE,
.buffer = g_uart2txbuffer,
},
{
.size = CONFIG_UART2_TXBUFSIZE,
.buffer = g_uart2txbuffer,
},
.ops = &g_uart_ops,
.priv = &g_uart2priv,
};
@ -420,7 +420,8 @@ static inline uint16_t up_serialin16(struct up_dev_s *priv, int offset)
* Name: up_serialout
****************************************************************************/
static inline void up_serialout(struct up_dev_s *priv, int offset, uint8_t value)
static inline void up_serialout(struct up_dev_s *priv,
int offset, uint8_t value)
{
putreg8(value, priv->uartbase + offset);
}
@ -429,7 +430,8 @@ static inline void up_serialout(struct up_dev_s *priv, int offset, uint8_t value
* Name: up_serialout16
****************************************************************************/
static inline void up_serialout16(struct up_dev_s *priv, int offset, uint16_t value)
static inline void up_serialout16(struct up_dev_s *priv,
int offset, uint16_t value)
{
putreg16(value, priv->uartbase + offset);
}
@ -438,7 +440,8 @@ static inline void up_serialout16(struct up_dev_s *priv, int offset, uint16_t va
* Name: up_disableuartint
****************************************************************************/
static inline void up_disableuartint(struct up_dev_s *priv, uint8_t *penables)
static inline void up_disableuartint(struct up_dev_s *priv,
uint8_t *penables)
{
uint8_t enables = priv->enables;
m16c_txint(priv, false);
@ -476,8 +479,9 @@ static inline void up_waittxready(struct up_dev_s *priv)
/* Check the TI bit in the CI register. 1=Transmit buffer empty */
if ((up_serialin(priv, M16C_UART_C1) & UART_C1_TI) != 0)
{
{
/* The transmit buffer is empty... return */
break;
}
}
@ -525,7 +529,7 @@ static inline void ub_setbrg(struct up_dev_s *priv, unsigned int baud)
static int up_setup(struct uart_dev_s *dev)
{
#ifndef CONFIG_SUPPRESS_UART_CONFIG
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint8_t regval;
/* Set the baud rate generator */
@ -541,13 +545,13 @@ static int up_setup(struct uart_dev_s *dev)
m16c_rxint(priv, false);
m16c_txint(priv, false);
/* Set interrupt cause=TX complete and continuous receive mode */
/* Set interrupt cause=TX complete and continuous receive mode */
#ifdef CONFIG_M16C_UART0
if (priv->uartno == 0)
{
regval = getreg8(M16C_UCON);
regval |= (UART_CON_U0IRS|UART_CON_U0RRM);
regval |= (UART_CON_U0IRS | UART_CON_U0RRM);
putreg8(regval, M16C_UCON);
}
else
@ -556,7 +560,7 @@ static int up_setup(struct uart_dev_s *dev)
if (priv->uartno == 1)
{
regval = getreg8(M16C_UCON);
regval |= (UART_CON_U1IRS|UART_CON_U1RRM);
regval |= (UART_CON_U1IRS | UART_CON_U1RRM);
putreg8(regval, M16C_UCON);
}
else
@ -565,7 +569,7 @@ static int up_setup(struct uart_dev_s *dev)
if (priv->uartno == 2)
{
regval = getreg8(M16C_U2C1);
regval |= (UART_C1_U2IRS|UART_C1_U2RRM);
regval |= (UART_C1_U2IRS | UART_C1_U2RRM);
putreg8(regval, M16C_U2C1);
}
else
@ -574,11 +578,15 @@ static int up_setup(struct uart_dev_s *dev)
_err("ERROR: Invalid UART #\n");
}
/* Set UART transmit/receive control register 1 to enable transmit and receive */
/* Set UART transmit/receive control register 1 to enable transmit
* and receive
*/
up_serialout(priv, M16C_UART_C1, UART_C1_TE|UART_C1_RE);
up_serialout(priv, M16C_UART_C1, UART_C1_TE | UART_C1_RE);
/* Set UART transmit/receive mode register data bits, stop bits, parity */
/* Set UART transmit/receive mode register data bits, stop bits,
* parity
*/
regval = 0;
@ -668,7 +676,7 @@ static int up_setup(struct uart_dev_s *dev)
static void up_shutdown(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
up_disableuartint(priv, NULL);
}
@ -676,20 +684,21 @@ static void up_shutdown(struct uart_dev_s *dev)
* Name: up_attach
*
* Description:
* Configure the UART to operation in interrupt driven mode. This method is
* called when the serial port is opened. Normally, this is just after the
* the setup() method is called, however, the serial console may operate in
* a non-interrupt driven mode during the boot phase.
* Configure the UART to operation in interrupt driven mode. This method
* is called when the serial port is opened. Normally, this is just after
* the the setup() method is called, however, the serial console may
* operate in a non-interrupt driven mode during the boot phase.
*
* RX and TX interrupts are not enabled when by the attach method (unless the
* hardware supports multiple levels of interrupt enabling). The RX and TX
* interrupts are not enabled until the txint() and rxint() methods are called.
* RX and TX interrupts are not enabled when by the attach method (unless
* the hardware supports multiple levels of interrupt enabling). The RX
* and TX interrupts are not enabled until the txint() and rxint() methods
* are called.
*
****************************************************************************/
static int up_attach(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
int ret;
/* Attach the UART receive data available IRQ */
@ -716,14 +725,14 @@ static int up_attach(struct uart_dev_s *dev)
*
* Description:
* Detach UART interrupts. This method is called when the serial port is
* closed normally just before the shutdown method is called. The exception is
* the serial console which is never shutdown.
* closed normally just before the shutdown method is called.
* The exception is the serial console which is never shutdown.
*
****************************************************************************/
static void up_detach(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
/* Disable all UART interrupts */
@ -771,7 +780,7 @@ static int up_rcvinterrupt(int irq, void *context, void *arg)
static int up_receive(struct uart_dev_s *dev, unsigned int *status)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint16_t rb;
/* Read the character from the readbuffer */
@ -857,7 +866,7 @@ static void m16c_rxint(struct up_dev_s *dev, bool enable)
static void up_rxint(struct uart_dev_s *dev, bool enable)
{
m16c_rxint((struct up_dev_s*)dev->priv, enable);
m16c_rxint((struct up_dev_s *)dev->priv, enable);
}
/****************************************************************************
@ -870,7 +879,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
static bool up_rxavailable(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
/* Return true if there is data available in the read buffer */
@ -912,7 +921,7 @@ static int up_xmtinterrupt(int irq, void *context, void *arg)
static void up_send(struct uart_dev_s *dev, int ch)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
/* Write the data to the transmit buffer */
@ -989,7 +998,7 @@ static void m16c_txint(struct up_dev_s *dev, bool enable)
static void up_txint(struct uart_dev_s *dev, bool enable)
{
m16c_txint((struct up_dev_s*)dev->priv, enable);
m16c_txint((struct up_dev_s *)dev->priv, enable);
}
/****************************************************************************
@ -1002,7 +1011,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
static bool up_txready(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
return ((up_serialin(priv, M16C_UART_C1) & UART_C1_TI) != 0);
}
@ -1087,7 +1096,7 @@ void up_consoleinit(void)
int up_putc(int ch)
{
#ifdef HAVE_SERIALCONSOLE
struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv;
uint8_t ucon;
up_disableuartint(priv, &ucon);

4
arch/renesas/src/m16c/m16c_timer.h
View File

@ -51,6 +51,7 @@
#define TABSR_TB2S 0x80 /* Bit 7: Timer B2 count start */
/* Clock Prescaler Reset Flag Register */
/* Bits 0-6: Not used */
#define CPSRF_CPSR 0x80 /* Bit 7: 1=Prescaler is reset */
@ -107,7 +108,8 @@
*/
/* Timer B Registers (16-bit access), simple value range 0000-ffff
* (except in Pulse period/pulse width measurement mode)
* (except in Pulse period/pulse
* width measurement mode)
*/
/* Timer A Mode Register (8-bit access) */

20
arch/renesas/src/m16c/m16c_timerisr.c
View File

@ -41,6 +41,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration */
#ifndef M16C_TA0_PRIO /* Timer A0 interrupt priority */
@ -54,21 +55,24 @@
*
* 20,000,000 / 100 = 200,000
*
* The ideal prescaler value would be the one, then that drops this to exactly
* 66535:
* The ideal prescaler value would be the one, then that drops this to
* exactly 66535:
*
* M16C_IDEAL_PRESCALER = 200,000 / 65535 = 3.05
*
* And any value greater than 3.05 would also work with less and less precision.
* The following calculation will produce the ideal prescaler as the next integer
* value above any fractional values:
* And any value greater than 3.05 would also work with less and less
* precision.
* The following calculation will produce the ideal prescaler as the next
* integer value above any fractional values:
*/
#define M16C_DIVISOR (65535 * CLK_TCK)
#define M16C_IDEAL_PRESCALER \
((M16C_XIN_FREQ + M16C_DIVISOR - 1) / M16C_DIVISOR)
/* Now, given this idel prescaler value, pick between available choices: 1, 8, and 32 */
/* Now, given this idel prescaler value,
* pick between available choices: 1, 8, and 32
*/
#if M16C_IDEAL_PRESCALER > 8
# define M16C_PRESCALE_VALUE 32
@ -141,7 +145,9 @@ void up_timer_initialize(void)
putreg8(0, M16C_TB1IC);
putreg8(0, M16C_TB2IC);
/* Set up timer 0 mode register for timer mode with the calculated prescaler value */
/* Set up timer 0 mode register for timer mode with the calculated
* prescaler value
*/
putreg8(M16C_TA0MODE_CONFIG, M16C_TA0MR);

1
arch/renesas/src/m16c/m16c_uart.h
View File

@ -111,6 +111,7 @@
#define UART_CON_CLKMD1 0x20 /* Bit 5: CLK/CLKS select bit */
#define UART_CON_RCSP 0x40 /* Bit 6: Separate CTS/RTS bit */
/* Bit 7: Reserved */
/* UART2 special mode register 1 (to be provided) */
/* UART2 special mode register 2 (to be provided) */

2
arch/renesas/src/sh1/chip.h
View File

@ -53,7 +53,7 @@
#endif
/************************************************************************************
* Public Functions
* Public Functions Prototypes
************************************************************************************/
#endif /* __ARCH_RENESAS_SRC_SH1_CHIP_H */

2
arch/renesas/src/sh1/sh1_703x.h
View File

@ -441,7 +441,7 @@
************************************************************************************/
/************************************************************************************
* Public Functions
* Public Functions Prototypes
************************************************************************************/
#endif /* __ARCH_RENESAS_SRC_SH1_703X_H */

7
arch/renesas/src/sh1/sh1_lowputc.c
View File

@ -37,7 +37,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration **********************************************************/
/* Configuration ************************************************************/
/* Is there a serial console? */
@ -104,7 +104,7 @@
#define SH1_SMR_VALUE (SH1_SMR_MODE|SH1_SMR_PARITY|SH1_SMR_STOP)
/* Clocking ***************************************************************/
/* Clocking *****************************************************************/
/* The calculation of the BRR to achieve the desired BAUD is given by the
* following formula:
@ -163,7 +163,8 @@ static inline int up_txready(void)
{
/* Check the TDRE bit in the SSR. 1=TDR is empty */
return ((getreg8(SH1_SCI_BASE + SH1_SCI_SSR_OFFSET) & SH1_SCISSR_TDRE) != 0);
return ((getreg8(SH1_SCI_BASE + SH1_SCI_SSR_OFFSET) &
SH1_SCISSR_TDRE) != 0);
}
#endif

2
arch/renesas/src/sh1/sh1_timerisr.c
View File

@ -156,7 +156,7 @@ void up_timer_initialize(void)
/* Set the timer control register. TCNT cleared by FRA */
putreg8(SH1_ITUTCR_CGRA|SH1_ITUTCR_DIV, SH1_ITU0_TCR);
putreg8(SH1_ITUTCR_CGRA | SH1_ITUTCR_DIV, SH1_ITU0_TCR);
/* Set the timer I/O control register */