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SAMD20: Fixes the problem introduced with the SAML21 integration

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This commit is contained in:
Gregory Nutt 2015-05-25 10:13:06 -06:00
parent 643a98a0a8
commit fe175fbc16
1 changed files with 4 additions and 3 deletions
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7
arch/arm/src/samdl/samd_clockconfig.c
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@ -558,7 +558,7 @@ static inline void sam_osc8m_config(void)
* BOARD_DFLL_FINEVALUE - Value * BOARD_DFLL_FINEVALUE - Value
* *
* Closed loop mode only: * Closed loop mode only:
* BOARD_DFLL_SRCGCLKGEN - See GCLK_CLKCTRL_GEN* definitions * BOARD_DFLL_SRCGCLKGEN - GCLK index
* BOARD_DFLL_MULTIPLIER - Value * BOARD_DFLL_MULTIPLIER - Value
* BOARD_DFLL_MAXCOARSESTEP - Value * BOARD_DFLL_MAXCOARSESTEP - Value
* BOARD_DFLL_MAXFINESTEP - Value * BOARD_DFLL_MAXFINESTEP - Value
@ -644,7 +644,7 @@ static inline void sam_dfll_config(void)
* Enable DFLL reference clock if in closed loop mode. * Enable DFLL reference clock if in closed loop mode.
* Depends on: * Depends on:
* *
* BOARD_DFLL_SRCGCLKGEN - See GCLK_CLKCTRL_GEN* definitions * BOARD_DFLL_SRCGCLKGEN - GCLK index
* *
* Input Parameters: * Input Parameters:
* None * None
@ -675,7 +675,8 @@ static inline void sam_dfll_reference(void)
* NOTE: We could enable write lock here to prevent further modification * NOTE: We could enable write lock here to prevent further modification
*/ */
regval = (BOARD_DFLL_SRCGCLKGEN | GCLK_CLKCTRL_ID_DFLL48M); regval = ((BOARD_DFLL_SRCGCLKGEN << GCLK_CLKCTRL_GEN_SHIFT) |
GCLK_CLKCTRL_ID_DFLL48M);
putreg16(regval, SAM_GCLK_CLKCTRL); putreg16(regval, SAM_GCLK_CLKCTRL);
/* Enable the DFLL reference clock */ /* Enable the DFLL reference clock */