sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

More PIC32 fixes

Browse Source 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4101 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2011-11-18 22:37:27 +00:00
parent 005133323f
commit fe49443cc3
3 changed files with 34 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/src/stm32/stm32_gpio.h
View File

@ -221,7 +221,7 @@ extern "C" {
# define GPIO_OUTPUT_MODE_2MHz (0 << GPIO_MODE_SHIFT) /* 2 MHz Low speed output */
# define GPIO_OUTPUT_MODE_25MHz (1 << GPIO_MODE_SHIFT) /* 25 MHz Medium speed output */
# define GPIO_OUTPUT_MODE_20MHz (2 << GPIO_MODE_SHIFT) /* 50 MHz Fast speed output */
# define GPIOOUTPUT__MODE_100MHz (3 << GPIO_MODE_SHIFT) /* 100 MHz High speed output */
# define GPIO_OUTPUT_MODE_100MHz (3 << GPIO_MODE_SHIFT) /* 100 MHz High speed output */
/* Output type selection:
* .... ..O. .... ....

24
arch/mips/src/pic32mx/excptmacros.h
View File

@ -114,6 +114,7 @@
* bits (Status<15:10>) and the ErrorEPC register, respectively, on the stack. ..."
*/
#ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS // Does not work!
mfc0 k0, MIPS32_CP0_CAUSE
mfc0 k1, MIPS32_CP0_EPC
@ -148,6 +149,25 @@
/* And Enable interrupts */
mtc0 k1, MIPS32_CP0_STATUS
#else
/* Get the EPC and STATUS register (Don't bother with the CAUSE register if we are
* not supporting nested interrupts)
*/
mfc0 k0, MIPS32_CP0_EPC
mfc0 k1, MIPS32_CP0_STATUS
/* Create the register context stack frame large enough to hold the entire register
* save array.
*/
addiu sp, sp, -XCPTCONTEXT_SIZE
/* Save the EPC and STATUS in the register context array */
sw k0, REG_EPC(sp)
sw k1, REG_STATUS(sp)
#endif
/* Save floating point registers */
@ -315,6 +335,10 @@
lw gp, REG_GP(k1)
#endif
/* $29 = sp: Stack pointer */
lw sp, REG_SP(k1)
/* $30 = either s8 or fp: Depends if a frame pointer is used or not */
lw s8, REG_S8(k1)

12
arch/mips/src/pic32mx/pic32mx-head.S
View File

@ -436,7 +436,9 @@ _bev_handler:
la t0, pic32mx_dobev /* Call up_dobev(regs) */
jalr ra, t0
nop
di /* Disable interrupts */
#ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS
di /* Prohibit nested interrupts from here */
#endif
RESTORE_STACK t0, t1 /* Undo the operations of USE_STACK */
EXCPT_EPILOGUE v0 /* Return to the context returned by up_dobev() */
.end _bev_handler
@ -459,7 +461,9 @@ _int_handler:
la t0, pic32mx_decodeirq /* Call pic32mx_decodeirq(regs) */
jalr ra, t0
nop
di /* Disable interrupts */
#ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS
di /* Prohibit nested interrupts from here */
#endif
RESTORE_STACK t0, t1 /* Undo the operations of USE_STACK */
EXCPT_EPILOGUE v0 /* Return to the context returned by pic32mx_decodeirq() */
.end _int_handler
@ -483,7 +487,9 @@ _nmi_handler:
la t0, pic32mx_donmi /* Call up_donmi(regs) */
jalr ra, t0
nop
di /* Disable interrupts */
#ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS
di /* Prohibit nested interrupts from here */
#endif
RESTORE_STACK t0, t1 /* Undo the operations of USE_STACK */
EXCPT_EPILOGUE v0 /* Return to the context returned by pic32mx_donmi() */
.end _nmi_handler