From fe813545e8bea6af2ccbde039747c407270eb9db Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 11 Jun 2017 11:00:29 -0600 Subject: [PATCH] STM32F33: Forgot to add new files that were a part of the last patch before committing. --- arch/arm/src/stm32/stm32_hrtim.c | 1519 ++++++++++++++++++++++++++++++ arch/arm/src/stm32/stm32_hrtim.h | 265 ++++++ 2 files changed, 1784 insertions(+) create mode 100644 arch/arm/src/stm32/stm32_hrtim.c create mode 100644 arch/arm/src/stm32/stm32_hrtim.h diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/stm32/stm32_hrtim.c new file mode 100644 index 0000000000..c0cc3e48af --- /dev/null +++ b/arch/arm/src/stm32/stm32_hrtim.c @@ -0,0 +1,1519 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_hrtim.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32_gpio.h" +#include "stm32_hrtim.h" + +#if defined(CONFIG_STM32_HRTIM1) + +/* Only STM32F33XXX */ + +#if defined(CONFIG_STM32_STM32F33XX) + +#ifdef CONFIG_STM32_HRTIM_ADC +# error HRTIM ADC Triggering not supported yet +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT +# error HRTIM Faults not supported yet +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV +# error HRTIM External Events not supported yet +#endif + +#ifdef CONFIG_STM32_HRTIM_BURST +# error HRTIM Burst mode not supported yet +#endif + +#ifdef CONFIG_STM32_HRTIM_IRQ +# error HRTIM Interrupts not supported yet +#endif + +#ifdef CONFIG_STM32_HRTIM_DMA +# error HRTIM DMA not supported yet +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* HRTIM default configuration **********************************************/ + +#ifndef HRTIM_TIMER_MASTER +# define HRTIM_MASTER_PRESCALER HRTIM_PRESCALER_2 +#endif + +/* HRTIM clock source configuration */ + +#ifdef CONFIG_STM32_HRTIM_CLK_FROM_PLL +# if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL +# if (STM32_RCC_CFGR_PPRE2 != RCC_CFGR_PPRE2_HCLK) && \ + (STM32_RCC_CFGR_PPRE2 != RCC_CFGR_PPRE2_HCLKd2) +# error "APB2 prescaler factor can not be greater than 2" +# else +# define HRTIM_HAVE_CLK_FROM_PLL 1 +# define HRTIM_CLOCK 2*STM32_PLL_FREQUENCY +# endif +# else +# error "Clock system must be set to PLL" +# endif +#else +# define HRTIM_HAVE_CLK_FROM_APB2 1 +# if STM32_RCC_CFGR_PPRE2 == RCC_CFGR_PPRE2_HCLK +# define HRTIM_CLOCK STM32_PCLK2_FREQUENCY +# else +# define HRTIM_CLOCK 2*STM32_PCLK2_FREQUENCY +# endif +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA) || defined(CONFIG_STM32_HRTIM_TIMB) || \ + defined(CONFIG_STM32_HRTIM_TIMC) || defined(CONFIG_STM32_HRTIM_TIMD) || \ + defined(CONFIG_STM32_HRTIM_TIME) +# define HRTIM_HAVE_SLAVE 1 +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA_PWM) || defined(CONFIG_STM32_HRTIM_TIMB_PWM) || \ + defined(CONFIG_STM32_HRTIM_TIMC_PWM) || defined(CONFIG_STM32_HRTIM_TIMD_PWM) || \ + defined(CONFIG_STM32_HRTIM_TIME_PWM) +# define HRTIM_HAVE_PWM 1 +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA_CAP) || defined(CONFIG_STM32_HRTIM_TIMB_CAP) || \ + defined(CONFIG_STM32_HRTIM_TIMC_CAP) || defined(CONFIG_STM32_HRTIM_TIMD_CAP) || \ + defined(CONFIG_STM32_HRTIM_TIME_CAP) +# define HRTIM_HAVE_CAPTURE 1 +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA_DT) || defined(CONFIG_STM32_HRTIM_TIMB_DT) || \ + defined(CONFIG_STM32_HRTIM_TIMC_DT) || defined(CONFIG_STM32_HRTIM_TIMD_DT) || \ + defined(CONFIG_STM32_HRTIM_TIME_DT) +# define HRTIM_HAVE_DEADTIME 1 +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA_CHOP) || defined(CONFIG_STM32_HRTIM_TIMB_CHOP) || \ + defined(CONFIG_STM32_HRTIM_TIMC_CHOP) || defined(CONFIG_STM32_HRTIM_TIMD_CHOP) || \ + defined(CONFIG_STM32_HRTIM_TIME_CHOP) +# define HRTIM_HAVE_CHOPPER 1 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifdef HRTIM_HAVE_PWM + +/* HRTIM TimerX Single Output Set/Reset Configuration */ + +struct stm32_hrtim_timout_s +{ + uint32_t set; /* Set events*/ + uint32_t rst; /* Reset events*/ +}; + +/* HRTIM TimerX Output Chopper Configuration */ + +#ifdef HRTIM_HAVE_CHOPPER +struct stm32_hrtim_chopper_s +{ + uint32_t reserved; /* reserved for future use */ +}; +#endif + +/* HRTIM TimerX Output Deadtime Configuration*/ + +#ifdef HRTIM_HAVE_DEADTIME +struct stm32_hrtim_deadtime_s +{ + uint32_t reserved; /* reserved for future use */ +}; +#endif + +/* HRTIM Timer PWM structure */ + +struct stm32_hrtim_pwm_s +{ + struct stm32_hrtim_timout_s ch1; /* Channel 1 Set/Reset configuration*/ + struct stm32_hrtim_timout_s ch2; /* Channel 2 Set/Reset configuration */ + +#ifdef HRTIM_HAVE_CHOPPER + struct stm32_hrtim_chopper_s chp; +#endif +#ifdef HRTIM_HAVE_DEADTIME + struct stm32_hrtim_deadtime_s dt; +#endif +}; + +#endif + +#ifdef HRTIM_HAVE_CAPTURE +struct stm32_hrtim_capture_s +{ + uint32_t reserved; /* reserved for future use */ +} +#endif + +/* Common data structure for Master Timer and Slave Timers*/ + +struct stm32_hrtim_timcmn_s +{ + uint16_t cmp[4]; /* Compare registers */ + uint32_t base; /* The base adress of the timer */ + uint32_t frequency; /* Current frequency setting */ + uint32_t pclk; /* The frequency of the peripheral clock + * that drives the timer module */ +#ifdef CONFIG_STM32_HRTIM_DMA + uint32_t dmaburst; +#endif +}; + +/* Master Timer and Slave Timers structure */ + +struct stm32_hrtim_tim_s +{ + struct stm32_hrtim_timcmn_s tim; /* Common Timer data */ + FAR void *priv; /* Timer private data */ +}; + +/* Master Timer private data structure */ + +struct stm32_hrtim_master_priv_s +{ + uint32_t reserved; /* reserved for future use */ +}; + +/* Slave Timer (A-E) private data structure */ + +struct stm32_hrtim_slave_priv_s +{ + uint32_t reset; /* Timer reset events */ +#ifdef HRTIM_HAVE_PWM + struct stm32_hrtim_pwm_s pwm; /* PWM configuration */ +#endif +#ifdef HRTIM_HAVE_CAPTURE + struct stm32_hrtim_capture_s cap; /* Capture configuration */ +#endif +}; + +/* This structure describes the configuration of HRTIM device */ + +struct stm32_hrtim_s +{ + uint32_t base; /* Base adress of HRTIM block */ + FAR const struct hrtim_ops_s *ops; /* */ + struct stm32_hrtim_tim_s *master; /* Master Timer */ +#ifdef CONFIG_STM32_HRTIM_TIMA + struct stm32_hrtim_tim_s *tima; /* HRTIM Timer A */ +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB + struct stm32_hrtim_tim_s *timb; /* HRTIM Timer B */ +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC + struct stm32_hrtim_tim_s *timc; /* HRTIM Timer C */ +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD + struct stm32_hrtim_tim_s *timd; /* HRTIM Timer D */ +#endif +#ifdef CONFIG_STM32_HRTIM_TIME + struct stm32_hrtim_tim_s *time; /* HRTIM Timer E */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* HRTIM Register access */ + +#ifdef HRTIM_HAVE_CLK_FROM_PLL +static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, + uint32_t setbits); +#endif +static uint32_t hrtim_getreg(FAR struct stm32_hrtim_s *priv, int offset); +static void hrtim_putreg(FAR struct stm32_hrtim_s *priv, int offset, + uint32_t value); +static void hrtim_modifyreg(FAR struct stm32_hrtim_s *priv, int offset, + uint32_t clrbits, uint32_t setbits); +static void hrtim_tim_putreg(FAR struct stm32_hrtim_s *priv, uint8_t index, + int offset, uint32_t value); +static void hrtim_tim_modifyreg(FAR struct stm32_hrtim_s *priv, uint8_t index, + int offset, uint32_t clrbits, uint32_t setbits); + +/* HRTIM helper */ + +static uint32_t hrtim_tim_getreg(FAR struct stm32_hrtim_s *priv, uint8_t index, + int offset); +static FAR struct stm32_hrtim_tim_s *hrtim_tim_get(FAR struct stm32_hrtim_s *priv, + uint8_t index); + +/* HRTIM Driver Methods */ + +static int hrtim_ioctl(FAR struct hrtim_dev_s *dev, int cmd, unsigned long arg); + +/* Configuration */ + +static int hrtim_dll_cal(FAR struct stm32_hrtim_s *priv); +static int hrtim_tim_clock_config(FAR struct stm32_hrtim_s *priv, uint8_t index, + uint8_t pre); +static int hrtim_tim_clocks_config(FAR struct stm32_hrtim_s *priv); +#if defined(HRTIM_HAVE_CAPTURE) || defined(HRTIM_HAVE_PWM) || defined(HRTIM_HAVE_SYNC) +static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv); +#endif +static void hrtim_preload_config(FAR struct stm32_hrtim_s *priv); +#if defined(HRTIM_HAVE_CAPTURE) +static int hrtim_inputs_config(FAR struct stm32_hrtim_s *priv); +#endif +#if defined(HRTIM_HAVE_SYNC) +static int hrtim_synch_config(FAR struct stm32_hrtim_s *priv); +#endif +#if defined(HRTIM_HAVE_PWM) +static int hrtim_outputs_config(FAR struct stm32_hrtim_s *priv); +#endif +#ifdef HRTIM_HAVE_ADC +static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv); +#endif +#ifdef HRTIM_HAVE_FAULTS +static int hrtim_faults_config(FAR struct stm32_hrtim_s *priv); +#endif +#ifdef HRTIM_HAVE_EEV +static int hrtim_eev_config(FAR struct stm32_hrtim_s *priv); +#endif +#ifdef HRTIM_HAVE_INTERRUPTS +static int hrtim_irq_config(FAR struct stm32_hrtim_s *priv); +#endif + +/* Initialization */ + +static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* HRTIM interface operations */ + +static const struct hrtim_ops_s g_hrtimops = +{ + .ho_ioctl = hrtim_ioctl, +}; + +/* Master Timer data */ + +static struct stm32_hrtim_tim_s g_master = +{ + .tim = + { + .base = STM32_HRTIM1_MASTER_BASE, + .pclk = HRTIM_CLOCK/HRTIM_MASTER_PRESCALER + }, + .priv = NULL, +}; + +/* NOTE: only TIMER A data defined at this time */ + +#ifdef CONFIG_STM32_HRTIM_TIMA + +/* Timer A private data */ + +static struct stm32_hrtim_slave_priv_s g_tima_priv = +{ +#ifdef CONFIG_STM32_HRTIM_TIMA_PWM + .pwm = + { + .ch1 = + { + .set = HRTIM_TIMA_CH1_SET, + .rst = HRTIM_TIMA_CH1_RST + }, + .ch2 = + { + .set = HRTIM_TIMA_CH2_SET, + .rst = HRTIM_TIMA_CH2_RST + }, +#ifdef CONFIG_STM32_HRTIM_TIMA_CHOP + .chp = + { + .reserved = 0 + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMA_DT + .dt = + { + .reserved = 0 + } +#endif + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMA_CAP + .cap = + { + .reserved = 0 + } +#endif +}; + +/* Timer A data */ + +static struct stm32_hrtim_tim_s g_tima = +{ + .tim = + { + .base = STM32_HRTIM1_TIMERA_BASE, + .pclk = HRTIM_CLOCK/HRTIM_TIMA_PRESCALER + }, + .priv = &g_tima_priv +}; + +#endif + +/* HRTIM1 private data */ + +static struct stm32_hrtim_s g_hrtim1priv = +{ + .master = &g_master, + .base = STM32_HRTIM1_BASE, +#ifdef CONFIG_STM32_HRTIM_TIMA + .tima = &g_tima, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB + .timb = &g_timb, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC + .timc = &g_timc, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD + .timd = &g_timd, +#endif +#ifdef CONFIG_STM32_HRTIM_TIME + .time = &g_time, +#endif +}; + +struct hrtim_dev_s g_hrtim1dev = +{ + .hd_ops = &g_hrtimops, + .hd_priv = &g_hrtim1priv, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_modifyreg32 + * + * Description: + * Modify the value of a 32-bit register (not atomic). + * + * Input Parameters: + * addr - The address of the register + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, + uint32_t setbits) +{ + putreg32((getreg32(addr) & ~clrbits) | setbits, addr); +} + + +/**************************************************************************** + * Name: hrtim_getreg + * + * Description: + * Read the value of an HRTIM register. + * + * Input Parameters: + * priv - A reference to the HRTIM block + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t hrtim_getreg(FAR struct stm32_hrtim_s *priv, int offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: hrtim_putreg + * + * Description: + * Write a value to an HRTIM register. + * + * Input Parameters: + * priv - A reference to the HRTIM block + * offset - The offset to the register to write to + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void hrtim_putreg(FAR struct stm32_hrtim_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +/**************************************************************************** + * Name: hrtim__modifyreg + * + * Description: + * Modify the value of an HRTIM register (not atomic). + * + * Input Parameters: + * priv - A reference to the HRTIM block + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void hrtim_modifyreg(FAR struct stm32_hrtim_s *priv, int offset, + uint32_t clrbits, uint32_t setbits) +{ + hrtim_putreg(priv, offset, (hrtim_getreg(priv, offset) & ~clrbits) | setbits); +} + + +/**************************************************************************** + * Name: hrtim_tim_get + * + * Description: + * Get Timer data structure for given HRTIM Timer index + * + * Input Parameters: + * priv - A reference to the HRTIM block + * index - An HRTIM Timer index to get + * + * Returned Value: + * Base adress offset for given timer index + * + ****************************************************************************/ + +static FAR struct stm32_hrtim_tim_s *hrtim_tim_get(FAR struct stm32_hrtim_s *priv, uint8_t index) +{ + FAR struct stm32_hrtim_tim_s *tim; + + switch (index) + { + case HRTIM_TIMER_MASTER: + { + tim = priv->master; + break; + } + +#ifdef CONFIG_STM32_HRTIM_TIMA + case HRTIM_TIMER_TIMA: + { + tim = priv->tima; + break; + } +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB + case HRTIM_TIMER_TIMB: + { + tim = &priv->timb; + break; + } +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC + case HRTIM_TIMER_TIMC: + { + tim = &priv->timc; + break; + } +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD + case HRTIM_TIMER_TIMD: + { + tim = &priv->timd; + break; + } +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME + case HRTIM_TIMER_TIME: + { + tim = &priv->time; + break; + } +#endif + + default: + { + tmrerr("ERROR: No such timerx index: %d\n", index); + tim = NULL; + } + } + + return tim; +} + +/**************************************************************************** + * Name: hrtim_base_get + * + * Description: + * Get base adress offset for given HRTIM Timer index + * + * Input Parameters: + * priv - A reference to the HRTIM block + * index - An HRTIM Timer index to get + * + * Returned Value: + * Base adress offset for given timer index + * + ****************************************************************************/ + +static uint32_t hrtim_base_get(FAR struct stm32_hrtim_s* priv, uint8_t index) +{ + FAR struct stm32_hrtim_tim_s* tim; + uint32_t base; + + tim = hrtim_tim_get(priv,index); + if (tim == NULL) + { + base = 0; + goto errout; + } + + base = tim->tim.base; + +errout: + return base; +} + +/**************************************************************************** + * Name: hrtim_tim_getreg + * + * Description: + * Read the value of an HRTIM Timer register. + * + * Input Parameters: + * priv - A reference to the HRTIM block + * tim - An HRTIM timer index + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t hrtim_tim_getreg(FAR struct stm32_hrtim_s *priv, uint8_t index, + int offset) +{ + uint32_t base; + + base = hrtim_base_get(priv, index); + if (base < 0) + { + return 0; + } + + return getreg32(base + offset); +} + +/**************************************************************************** + * Name: hrtim_tim_putreg + * + * Description: + * Write a value to an HRTIM Timer register. + * + * Input Parameters: + * priv - A reference to the HRTIM block + * index - An HRTIM timer index + * offset - The offset to the register to write to + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void hrtim_tim_putreg(FAR struct stm32_hrtim_s *priv, uint8_t index, + int offset, uint32_t value) +{ + uint32_t base; + + base = hrtim_base_get(priv, index); + if (base > 0) + { + putreg32(value, base + offset); + } +} + +/**************************************************************************** + * Name: hrtim_tim_modifyreg + * + * Description: + * Modify the value of an HRTIM Timer register (not atomic). + * + * Input Parameters: + * priv - A reference to the HRTIM block + * index - An HRTIM timer index + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void hrtim_tim_modifyreg(FAR struct stm32_hrtim_s *priv, uint8_t index, + int offset, uint32_t clrbits, uint32_t setbits) +{ + hrtim_tim_putreg(priv, index, offset, + (hrtim_tim_getreg(priv, index, offset) & ~clrbits) | setbits); +} + +/**************************************************************************** + * Name: hrtim_ioctl + * + * Description: + * All ioctl calls will be routed through this method. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * cmd - command + * arg - arguments passed with command + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int hrtim_ioctl(FAR struct hrtim_dev_s *dev, int cmd, unsigned long arg) +{ +#warning "hrtim_ioctl: missing logic" + return -ENOTTY; +} + +/**************************************************************************** + * Name: stm32_dll_cal + * + * Description: + * Calibrate HRTIM DLL + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_dll_cal(FAR struct stm32_hrtim_s *priv) +{ + uint32_t regval = 0; + +#ifdef CONFIG_STM32_HRTIM_PERIODIC_CAL + + /* Configure calibration rate */ + + regval |= HRTIM_DLLCR_CAL_RATE; + + /* Enable Periodic calibration */ + + regval |= HRTIM_DLLCR_CALEN; + +#endif + + /* DLL Calibration Start */ + + regval |= HRTIM_DLLCR_CAL; + + hrtim_putreg(priv, STM32_HRTIM_CMN_DLLCR, regval); + + /* Wait for HRTIM ready flag */ + + while(!(hrtim_getreg(priv, STM32_HRTIM_CMN_ISR) & HRTIM_ISR_DLLRDY)); + + return OK; +} + +/**************************************************************************** + * Name: stm32_tim_clock_config + * + * Description: + * Configure HRTIM Timer clock + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * index - An HRTIM timer index + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_tim_clock_config(FAR struct stm32_hrtim_s *priv, uint8_t index, uint8_t pre) +{ + int ret = OK; + uint32_t regval = 0; + + regval = hrtim_tim_getreg(priv, index, STM32_HRTIM_TIM_CR_OFFSET); + + switch (pre) + { + case HRTIM_PRESCALER_1: + { + regval |= HRTIM_CMNCR_CKPSC_NODIV; + break; + } + case HRTIM_PRESCALER_2: + { + regval |= HRTIM_CMNCR_CKPSC_d2; + break; + } + case HRTIM_PRESCALER_4: + { + regval |= HRTIM_CMNCR_CKPSC_d4; + break; + } + case HRTIM_PRESCALER_8: + { + regval |= HRTIM_CMNCR_CKPSC_d8; + break; + } + case HRTIM_PRESCALER_16: + { + regval |= HRTIM_CMNCR_CKPSC_d16; + break; + } + case HRTIM_PRESCALER_32: + { + regval |= HRTIM_CMNCR_CKPSC_d32; + break; + } + case HRTIM_PRESCALER_64: + { + regval |= HRTIM_CMNCR_CKPSC_d64; + break; + } + case HRTIM_PRESCALER_128: + { + regval |= HRTIM_CMNCR_CKPSC_d128; + break; + } + default: + { + tmrerr("ERROR: invalid prescaler value %d for timer %d\n", index, + pre); + ret = -EINVAL; + goto errout; + } + } + +errout: + return ret; +} + + +/**************************************************************************** + * Name: stm32_tim_clocks_config + * + * Description: + * Configure HRTIM Timers Clocks + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_tim_clocks_config(FAR struct stm32_hrtim_s *priv) +{ + int ret = OK; + + /* Configure Master Timer clock */ + + ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_MASTER, HRTIM_MASTER_PRESCALER); + if (ret < 0) + { + goto errout; + } + + /* Configure Timer A clock */ + +#ifdef CONFIG_STM32_HRTIM_TIMA + ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_TIMA, HRTIM_TIMA_PRESCALER); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure Timer B clock */ + +#ifdef CONFIG_STM32_HRTIM_TIMB + ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_TIMB, HRTIM_TIMB_PRESCALER); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure Timer C clock */ + +#ifdef CONFIG_STM32_HRTIM_TIMC + ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_TIMC, HRTIM_TIMC_PRESCALER); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure Timer D clock */ + +#ifdef CONFIG_STM32_HRTIM_TIMD + ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_TIMD, HRTIM_TIMD_PRESCALER); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure Timer E clock */ + +#ifdef CONFIG_STM32_HRTIM_TIME + ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_TIME, HRTIM_TIME_PRESCALER); + if (ret < 0) + { + goto errout; + } +#endif + +errout: + return ret; +} + +/**************************************************************************** + * Name: stm32_gpios_config + * + * Description: + * Configure HRTIM GPIO + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +#if defined(HRTIM_HAVE_CAPTURE) || defined(HRTIM_HAVE_PWM) || defined(HRTIM_HAVE_SYNC) +static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv) +{ +#warning "hrtim_gpios_config: missing logic" + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_inputs_config + * + * Description: + * Configure HRTIM Inputs + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +#if defined(HRTIM_HAVE_CAPTURE) +static int hrtim_inputs_config(FAR struct stm32_hrtim_s *priv) +{ +#warning "hrtim_inputs_config: missing logic" + + /* source */ + + /* polarity */ + + /* edge-sensitivity */ + + return OK; +} +#endif + + +/**************************************************************************** + * Name: stm32_synch_config + * + * Description: + * Configure HRTIM Synchronization Input/Output + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +#if defined(HRTIM_HAVE_SYNC) +static int hrtim_synch_config(FAR struct stm32_hrtim_s *priv) +{ +#warning "hrtim_synch_config: missing logic" + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_tim_outputs_config + * + * Description: + * Configure HRTIM Slave Timer Outputs (CH1 and CH2) + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +#if defined(HRTIM_HAVE_PWM) +static int hrtim_tim_outputs_config(FAR struct stm32_hrtim_s *priv, uint8_t index) +{ + FAR struct stm32_hrtim_tim_s* tim; + FAR struct stm32_hrtim_slave_priv_s* slave; + + int ret = OK; + uint32_t regval = 0; + + /* Master Timer has no outputs */ + + if (index == HRTIM_TIMER_MASTER) + { + ret = -EINVAL; + goto errout; + } + + /* Get Timer data strucutre */ + + tim = hrtim_tim_get(priv, index); + if (tim == NULL) + { + ret = -EINVAL; + goto errout; + } + + slave = (struct stm32_hrtim_slave_priv_s*)tim->priv; + + /* Configure CH1 SET events */ + + regval = slave->pwm.ch1.set; + hrtim_tim_putreg(priv, index, STM32_HRTIM_TIM_SET1R_OFFSET, regval); + + /* Configure CH1 RESET events */ + + regval = slave->pwm.ch1.rst; + hrtim_tim_putreg(priv, index, STM32_HRTIM_TIM_RST1R_OFFSET, regval); + + /* Configure CH2 SET events */ + + regval = slave->pwm.ch2.set; + hrtim_tim_putreg(priv, index, STM32_HRTIM_TIM_SET2R_OFFSET, regval); + + /* Configure CH2 RESET events */ + + regval = slave->pwm.ch2.rst; + hrtim_tim_putreg(priv, index, STM32_HRTIM_TIM_RST2R_OFFSET, regval); + +errout: + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_outputs_config + * + * Description: + * Configure HRTIM Outputs + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +#if defined(HRTIM_HAVE_PWM) +static int hrtim_outputs_config(FAR struct stm32_hrtim_s *priv) +{ + int ret = OK; + + /* Configure HRTIM TIMER A Outputs */ + +#ifdef CONFIG_STM32_HRTIM_TIMA_PWM + ret = hrtim_tim_outputs_config(priv, HRTIM_TIMER_TIMA); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure HRTIM TIMER B Outputs */ + +#ifdef CONFIG_STM32_HRTIM_TIMB_PWM + ret = hrtim_tim_outputs_config(priv, HRTIM_TIMER_TIMB); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure HRTIM TIMER C Outputs */ + +#ifdef CONFIG_STM32_HRTIM_TIMC_PWM + ret = hrtim_tim_outputs_config(priv, HRTIM_TIMER_TIMC); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure HRTIM TIMER D Outputs */ + +#ifdef CONFIG_STM32_HRTIM_TIMD_PWM + ret = hrtim_tim_outputs_config(priv, HRTIM_TIMER_TIMD); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure HRTIM TIMER E Outputs */ + +#ifdef CONFIG_STM32_HRTIM_TIME_PWM + ret = hrtim_tim_outputs_config(priv, HRTIM_TIMER_TIME); + if (ret < 0) + { + goto errout; + } +#endif + +errout: + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_adc_config + * + * Description: + * Configure HRTIM ADC triggers + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +#ifdef HRTIM_HAVE_ADC +static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv) +{ +#warning "hrtim_adc_config: missing logic" + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_faults_config + * + * Description: + * Configure HRTIM Faults + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +#ifdef HRTIM_HAVE_FAULTS +static int hrtim_faults_config(FAR struct stm32_hrtim_s *priv) +{ +#warning "hrtim_faults_config: missing logic" + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_eev_config + * + * Description: + * Configure HRTIM External Events + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +#ifdef HRTIM_HAVE_EEV +static int hrtim_eev_config(FAR struct stm32_hrtim_s *priv) +{ +#warning "hrtim_eev_confi: missing logic" + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_irq_config + * + * Description: + * Configure HRTIM interrupts + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +#ifdef HRTIM_HAVE_INTERRUPTS +static int hrtim_irq_config(FAR struct stm32_hrtim_s *priv) +{ +#warning "hrtim_irq_config: missing logic" + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_preload_config + * + * Description: + * Configure HRTIM preload registers + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void hrtim_preload_config(FAR struct stm32_hrtim_s *priv) +{ + +#ifndef CONFIG_STM32_HRTIM_MASTER_PRELOAD_DIS + hrtim_tim_modifyreg(priv, HRTIM_TIMER_MASTER, STM32_HRTIM_TIM_CR_OFFSET, + 0, HRTIM_CMNCR_PREEN); +#endif + +#if defined(CONFIG_ST32_HRTIM_TIMA) && defined(CONFIG_STM32_HRTIM_TIMA_PRELOAD_DIS) + hrtim_tim_modifyreg(priv, HRTIM_TIMER_TIMA, STM32_HRTIM_TIM_CR_OFFSET, + 0, HRTIM_CMNCR_PREEN); +#endif + +#if defined(CONFIG_ST32_HRTIM_TIMB) && defined(CONFIG_STM32_HRTIM_TIMB_PRELOAD_DIS) + hrtim_tim_modifyreg(priv, HRTIM_TIMER_TIMB, STM32_HRTIM_TIM_CR_OFFSET, + 0, HRTIM_CMNCR_PREEN); +#endif + +#if defined(CONFIG_ST32_HRTIM_TIMC) && defined(CONFIG_STM32_HRTIM_TIMC_PRELOAD_DIS) + hrtim_tim_modifyreg(priv, HRTIM_TIMER_TIMC, STM32_HRTIM_TIM_CR_OFFSET, + 0, HRTIM_CMNCR_PREEN); +#endif + +#if defined(CONFIG_ST32_HRTIM_TIMD) && defined(CONFIG_STM32_HRTIM_TIMD_PRELOAD_DIS) + hrtim_tim_modifyreg(priv, HRTIM_TIMER_TIMD, STM32_HRTIM_TIM_CR_OFFSET, + 0, HRTIM_CMNCR_PREEN); +#endif + +#if defined(CONFIG_ST32_HRTIM_TIME) && defined(CONFIG_STM32_HRTIM_TIME_PRELOAD_DIS) + hrtim_tim_modifyreg(priv, HRTIM_TIMER_TIME, STM32_HRTIM_TIM_CR_OFFSET, + 0, HRTIM_CMNCR_PREEN); +#endif + +} + +/**************************************************************************** + * Name: stm32_hrtimconfig + * + * Description: + * Configure HRTIM + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) +{ + int ret; + uint32_t regval = 0; + + /* Configure PLL VCO output as HRTIM clock source */ + +#ifdef HRTIM_HAVE_CLK_FROM_PLL + stm32_modifyreg32(STM32_RCC_CFGR3, 0, RCC_CFGR3_HRTIM1SW); +#endif + + /* HRTIM DLL calibration */ + + ret = hrtim_dll_cal(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM DLL calibration failed!\n"); + goto errout; + } + + /* Configure Timers Clocks */ + + ret = hrtim_tim_clocks_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM timers clock configuration failed!\n"); + goto errout; + } + + /* Configure HRTIM GPIOs */ + +#if defined(HRTIM_HAVE_CAPTURE) || defined(HRTIM_HAVE_PWM) || defined(HRTIM_HAVE_SYNC) + ret = hrtim_gpios_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM GPIOs configuration failed!\n"); + goto errout; + } +#endif + + /* Configure HRTIM inputs */ + +#if defined(HRTIM_HAVE_CAPTURE) + ret = hrtim_inputs_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM inputs configuration failed!\n"); + goto errout; + } +#endif + + /* Configure Synchronisation IOs */ + +#if defined(HRTIM_HAVE_SYNC) + ret = hrtim_synch_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM synchronisation configuration failed!\n"); + goto errout; + } +#endif + + /* Configure HRTIM outputs GPIOs */ + +#if defined(HRTIM_HAVE_PWM) + ret = hrtim_outputs_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM outputs configuration failed!\n"); + goto errout; + } +#endif + + /* Configure ADC triggers */ + +#ifdef HRTIM_HAVE_ADC + ret = hrtim_adc_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM ADC configuration failed!\n"); + goto errout; + } +#endif + + /* Configure Faults */ + +#ifdef HRTIM_HAVE_FAULTS + ret = hrtim_faults_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM faults configuration failed!\n"); + goto errout; + } +#endif + + /* Configure Events */ + +#ifdef HRTIM_HAVE_EEV + ret = hrtim_eev_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM EEV configuration failed!\n"); + goto errout; + } +#endif + + /* Configure interrupts */ + +#ifdef HRTIM_HAVE_INTERRUPTS + ret = hrtim_irq_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM IRQ configuration failed!\n"); + goto errout; + } +#endif + + /* Enable registers preload */ + + hrtim_preload_config(priv); + + /* Enable Master Timer */ + + regval |= HRTIM_MCR_MCEN; + + /* Enable Slave Timers */ + +#ifdef CONFIG_STM32_HRTIM_TIMA + regval |= HRTIM_MCR_TACEN; +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB + regval |= HRTIM_MCR_TBCEN; +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC + regval |= HRTIM_MCR_TCCEN; +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD + regval |= HRTIM_MCR_TDCEN; +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME + regval |= HRTIM_MCR_TECEN; +#endif + + /* Write enable bits at once */ + + hrtim_tim_modifyreg(priv, HRTIM_TIMER_MASTER, STM32_HRTIM_TIM_CR_OFFSET, 0, regval); + +errout: + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_hrtiminitialize + * + * Description: + * Initialize the HRTIM. + * + * Returned Value: + * Valid HRTIM device structure reference on succcess; a NULL on failure. + * + * Assumptions: + * 1. Clock to the HRTIM block has enabled, + * 2. Board-specific logic has already configured + * + ****************************************************************************/ + +FAR struct hrtim_dev_s* stm32_hrtiminitialize(void) +{ + FAR struct hrtim_dev_s *dev; + FAR struct stm32_hrtim_s *hrtim; + int ret; + + dev = &g_hrtim1dev; + + hrtim = dev->hd_priv; + + ret = stm32_hrtimconfig(hrtim); + if (ret < 0) + { + tmrerr("ERROR: Failed to initialize HRTIM1: %d\n", ret); + errno = -ret; + return NULL; + } + + return dev; +} + +#endif /* CONFIG_STM32_STM32F33XX */ + +#endif /* CONFIG_STM32_HRTIM1 */ diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/stm32/stm32_hrtim.h new file mode 100644 index 0000000000..1fa9a4971a --- /dev/null +++ b/arch/arm/src/stm32/stm32_hrtim.h @@ -0,0 +1,265 @@ +/************************************************************************************ + * arch/arm/src/stm32/stm32_hrtim.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_HRTIM_H +#define __ARCH_ARM_SRC_STM32_STM32_HRTIM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +#ifdef CONFIG_STM32_HRTIM1 + +#if defined(CONFIG_STM32_STM32F33XX) +# include "chip/stm32f33xxx_hrtim.h" +#else +# error +#endif + +/************************************************************************************ + * Pre-processor definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/* HRTIM Timer X index */ + +enum stm32_hrtim_tim_e +{ + HRTIM_TIMER_MASTER, +#ifdef CONFIG_STM32_HRTIM_TIMA + HRTIM_TIMER_TIMA, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB + HRTIM_TIMER_TIMB, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC + HRTIM_TIMER_TIMC, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD + HRTIM_TIMER_TIMD, +#endif +#ifdef CONFIG_STM32_HRTIM_TIME + HRTIM_TIMER_TIME, +#endif +}; + +/* Source which can force the Tx1/Tx2 output to its inactive state */ + +enum stm32_hrtim_out_rst_e +{ + HRTIM_OUT_RST_UPDATE = (1 << 0), + HRTIM_OUT_RST_EXTEVNT10 = (1 << 1), + HRTIM_OUT_RST_EXTEVNT9 = (1 << 2), + HRTIM_OUT_RST_EXTEVNT8 = (1 << 3), + HRTIM_OUT_RST_EXTEVNT7 = (1 << 4), + HRTIM_OUT_RST_EXTEVNT6 = (1 << 5), + HRTIM_OUT_RST_EXTEVNT5 = (1 << 6), + HRTIM_OUT_RST_EXTEVNT4 = (1 << 7), + HRTIM_OUT_RST_EXTEVNT3 = (1 << 8), + HRTIM_OUT_RST_EXTEVNT2 = (1 << 9), + HRTIM_OUT_RST_EXTEVNT1 = (1 << 10), + HRTIM_OUT_RST_TIMEVNT9 = (1 << 11), + HRTIM_OUT_RST_TIMEVNT8 = (1 << 12), + HRTIM_OUT_RST_TIMEVNT7 = (1 << 13), + HRTIM_OUT_RST_TIMEVNT6 = (1 << 14), + HRTIM_OUT_RST_TIMEVNT5 = (1 << 15), + HRTIM_OUT_RST_TIMEVNT4 = (1 << 16), + HRTIM_OUT_RST_TIMEVNT3 = (1 << 17), + HRTIM_OUT_RST_TIMEVNT2 = (1 << 18), + HRTIM_OUT_RST_TIMEVNT1 = (1 << 19), + HRTIM_OUT_RST_MSTCMP4 = (1 << 20), + HRTIM_OUT_RST_MSTCMP3 = (1 << 21), + HRTIM_OUT_RST_MSTCMP2 = (1 << 22), + HRTIM_OUT_RST_MSTCMP1 = (1 << 23), + HRTIM_OUT_RST_MSTPER = (1 << 24), + HRTIM_OUT_RST_CMP4 = (1 << 25), + HRTIM_OUT_RST_CMP3 = (1 << 26), + HRTIM_OUT_RST_CMP2 = (1 << 27), + HRTIM_OUT_RST_CMP1 = (1 << 28), + HRTIM_OUT_RST_PER = (1 << 29), + HRTIM_OUT_RST_RESYNC = (1 << 30), + HRTIM_OUT_RST_SOFT = (1 << 31), +}; + +/* Source which can force the Tx1/Tx2 output to its active state */ + +enum stm32_hrtim_out_set_e +{ + HRTIM_OUT_SET_UPDATE = (1 << 0), + HRTIM_OUT_SET_EXTEVNT10 = (1 << 1), + HRTIM_OUT_SET_EXTEVNT9 = (1 << 2), + HRTIM_OUT_SET_EXTEVNT8 = (1 << 3), + HRTIM_OUT_SET_EXTEVNT7 = (1 << 4), + HRTIM_OUT_SET_EXTEVNT6 = (1 << 5), + HRTIM_OUT_SET_EXTEVNT5 = (1 << 6), + HRTIM_OUT_SET_EXTEVNT4 = (1 << 7), + HRTIM_OUT_SET_EXTEVNT3 = (1 << 8), + HRTIM_OUT_SET_EXTEVNT2 = (1 << 9), + HRTIM_OUT_SET_EXTEVNT1 = (1 << 10), + HRTIM_OUT_SET_TIMEVNT9 = (1 << 11), + HRTIM_OUT_SET_TIMEVNT8 = (1 << 12), + HRTIM_OUT_SET_TIMEVNT7 = (1 << 13), + HRTIM_OUT_SET_TIMEVNT6 = (1 << 14), + HRTIM_OUT_SET_TIMEVNT5 = (1 << 15), + HRTIM_OUT_SET_TIMEVNT4 = (1 << 16), + HRTIM_OUT_SET_TIMEVNT3 = (1 << 17), + HRTIM_OUT_SET_TIMEVNT2 = (1 << 18), + HRTIM_OUT_SET_TIMEVNT1 = (1 << 19), + HRTIM_OUT_SET_MSTCMP4 = (1 << 20), + HRTIM_OUT_SET_MSTCMP3 = (1 << 21), + HRTIM_OUT_SET_MSTCMP2 = (1 << 22), + HRTIM_OUT_SET_MSTCMP1 = (1 << 23), + HRTIM_OUT_SET_MSTPER = (1 << 24), + HRTIM_OUT_SET_CMP4 = (1 << 25), + HRTIM_OUT_SET_CMP3 = (1 << 26), + HRTIM_OUT_SET_CMP2 = (1 << 27), + HRTIM_OUT_SET_CMP1 = (1 << 28), + HRTIM_OUT_SET_PER = (1 << 29), + HRTIM_OUT_SET_RESYNC = (1 << 30), + HRTIM_OUT_SET_SOFT = (1 << 31), +}; + +/* Events that can reset TimerX Counter */ + +enum stm32_hrtim_tim_rst_e +{ + /* Timer owns events */ + + HRTIM_RST_UPDT, + HRTIM_RST_CMP4, + HRTIM_RST_CMP2, + + /* Master Timer Events */ + + HRTIM_RST_MSTCMP4, + HRTIM_RST_MSTCMP3, + HRTIM_RST_MSTCMP2, + HRTIM_RST_MSTCMP1, + HRTIM_RST_MSTPER, + + /* TimerX events */ + + HRTIM_RST_TECMP4, + HRTIM_RST_TECMP2, + HRTIM_RST_TECMP1, + HRTIM_RST_TDCMP4, + HRTIM_RST_TDCMP2, + HRTIM_RST_TDCMP1, + HRTIM_RST_TCCMP4, + HRTIM_RST_TCCMP2, + HRTIM_RST_TCCMP1, + HRTIM_RST_TBCMP4, + HRTIM_RST_TBCMP2, + HRTIM_RST_TBCMP1, + HRTIM_RST_TACMP4, + HRTIM_RST_TACMP2, + HRTIM_RST_TACMP1, + + /* External Events */ + + HRTIM_RST_EXTEVNT10, + HRTIM_RST_EXTEVNT9, + HRTIM_RST_EXTEVNT8, + HRTIM_RST_EXTEVNT7, + HRTIM_RST_EXTEVNT6, + HRTIM_RST_EXTEVNT5, + HRTIM_RST_EXTEVNT4, + HRTIM_RST_EXTEVNT3, + HRTIM_RST_EXTEVNT2, + HRTIM_RST_EXTEVNT1, +}; + +/* HRTIM Timer X prescaler */ + +enum stm32_hrtim_tim_prescaler_e +{ + HRTIM_PRESCALER_1, + HRTIM_PRESCALER_2, + HRTIM_PRESCALER_4, + HRTIM_PRESCALER_8, + HRTIM_PRESCALER_16, + HRTIM_PRESCALER_32, + HRTIM_PRESCALER_64, + HRTIM_PRESCALER_128, +}; + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_hrtiminitialize + * + * Description: + * Initialize the HRTIM. + * + * Input Parameters: + * None + * + * Returned Value: + * Valid HRTIM device structure reference on succcess; a NULL on failure. + * + * Assumptions: + * 1. Clock to the HRTIM block has enabled, + * 2. Board-specific logic has already configured + * + ****************************************************************************/ + +FAR struct hrtim_dev_s* stm32_hrtiminitialize(void); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_HRTIM1 */ +#endif /* __ARCH_ARM_SRC_STM32_STM32_HRTIM_H */