diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c index 0bdebfa76b..9f09a3b72c 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -58,6 +58,91 @@ #define ESP32_LEVEL_SET ESP32_INTSET(ESP32_CPUINT_NLEVELPERIPHS) #define ESP32_EDGE_SET ESP32_INTSET(ESP32_CPUINT_NEDGEPERIPHS) +/* Mapping Peripheral IDs to map register addresses + * + * PERIPHERAL ID DPORT REGISTER OFFSET + * MNEMONIC VAL PRO CPU APP CPU + * -------------------------- --- ------- ------- + * ESP32_PERIPH_MAC 0 0x104 0x218 + * ESP32_PERIPH_MAC_NMI 1 0x108 0x21c + * ESP32_PERIPH_BB 2 0x10c 0x220 + * ESP32_PERIPH_BB_MAC 3 0x110 0x224 + * ESP32_PERIPH_BT_BB 4 0x114 0x228 + * ESP32_PERIPH_BT_BB_NMI 5 0x118 0x22c + * ESP32_PERIPH_RWBT_IRQ 6 0x11c 0x230 + * ESP32_PERIPH_RWBLE_IRQ 7 0x120 0x234 + * ESP32_PERIPH_RWBT_NMI 8 0x124 0x238 + * ESP32_PERIPH_RWBLE_NMI 9 0x128 0x23c + * ESP32_PERIPH_SLC0 10 0x12c 0x240 + * ESP32_PERIPH_SLC1 11 0x130 0x244 + * ESP32_PERIPH_UHCI0 12 0x134 0x248 + * ESP32_PERIPH_UHCI1 13 0x138 0x24c + * ESP32_PERIPH_TG_T0_LEVEL 14 0x13c 0x250 + * ESP32_PERIPH_TG_T1_LEVEL 15 0x140 0x254 + * ESP32_PERIPH_TG_WDT_LEVEL 16 0x144 0x258 + * ESP32_PERIPH_TG_LACT_LEVEL 17 0x148 0x25c + * ESP32_PERIPH_TG1_T0_LEVEL 18 0x14c 0x260 + * ESP32_PERIPH_TG1_T1_LEVEL 19 0x150 0x264 + * ESP32_PERIPH_TG1_WDT_LEVEL 20 0x154 0x268 + * ESP32_PERIPH_G1_LACT_LEVEL 21 0x158 0x26c + * ESP32_PERIPH_CPU_GPIO 22 0x15c 0x270 + * ESP32_PERIPH_CPU_NMI 23 0x160 0x274 + * ESP32_PERIPH_CPU_CPU0 24 0x164 0x278 + * ESP32_PERIPH_CPU_CPU1 25 0x168 0x27c + * ESP32_PERIPH_CPU_CPU2 26 0x16c 0x280 + * ESP32_PERIPH_CPU_CPU3 27 0x170 0x284 + * ESP32_PERIPH_SPI0 28 0x174 0x288 + * ESP32_PERIPH_SPI1 29 0x178 0x28c + * ESP32_PERIPH_SPI2 30 0x17c 0x290 + * ESP32_PERIPH_SPI3 31 0x180 0x294 + * ESP32_PERIPH_I2S0 32 0x184 0x298 + * ESP32_PERIPH_I2S1 33 0x188 0x29c + * ESP32_PERIPH_UART 34 0x18c 0x2a0 + * ESP32_PERIPH_UART1 35 0x190 0x2a4 + * ESP32_PERIPH_UART2 36 0x194 0x2a8 + * ESP32_PERIPH_SDIO_HOST 37 0x198 0x2ac + * ESP32_PERIPH_EMAC 38 0x19c 0x2b0 + * ESP32_PERIPH_PWM0 39 0x1a0 0x2b4 + * ESP32_PERIPH_PWM1 40 0x1a4 0x2b8 + * ESP32_PERIPH_PWM2 41 0x1a8 0x2bc + * ESP32_PERIPH_PWM3 42 0x1ac 0x2c0 + * ESP32_PERIPH_LEDC 43 0x1b0 0x2c4 + * ESP32_PERIPH_EFUSE 44 0x1b4 0x2c8 + * ESP32_PERIPH_CAN 45 0x1b8 0x2cc + * ESP32_PERIPH_RTC_CORE 46 0x1bc 0x2d0 + * ESP32_PERIPH_RMT 47 0x1c0 0x2d4 + * ESP32_PERIPH_PCNT 48 0x1c4 0x2d8 + * ESP32_PERIPH_I2C_EXT0 49 0x1c8 0x2dc + * ESP32_PERIPH_I2C_EXT1 50 0x1cc 0x2e0 + * ESP32_PERIPH_RSA 51 0x1d0 0x2e4 + * ESP32_PERIPH_SPI1_DMA 52 0x1d4 0x2e8 + * ESP32_PERIPH_SPI2_DMA 53 0x1d8 0x2ec + * ESP32_PERIPH_SPI3_DMA 54 0x1dc 0x2f0 + * ESP32_PERIPH_WDG 55 0x1e0 0x2f4 + * ESP32_PERIPH_TIMER1 56 0x1e4 0x2f8 + * ESP32_PERIPH_TIMER2 57 0x1e8 0x2fc + * ESP32_PERIPH_TG_T0_EDGE 58 0x1ec 0x300 + * ESP32_PERIPH_TG_T1_EDGE 59 0x1f0 0x304 + * ESP32_PERIPH_TG_WDT_EDGE 60 0x1F4 0x308 + * ESP32_PERIPH_TG_LACT_EDGE 61 0x1F8 0x30c + * ESP32_PERIPH_TG1_T0_EDGE 62 0x1fc 0x310 + * ESP32_PERIPH_TG1_T1_EDGE 63 0x200 0x314 + * ESP32_PERIPH_TG1_WDT_EDGE 64 0x204 0x318 + * ESP32_PERIPH_TG1_LACT_EDGE 65 0x208 0x31c + * ESP32_PERIPH_MMU_IA 66 0x20c 0x320 + * ESP32_PERIPH_MPU_IA 67 0x210 0x324 + * ESP32_PERIPH_CACHE_IA 68 0x214 0x328 + */ + +#define DPORT_PRO_MAP_REGADDR(n) (DR_REG_DPORT_BASE + 0x104 + ((n) << 2)) +#define DPORT_APP_MAP_REGADDR(n) (DR_REG_DPORT_BASE + 0x218 + ((n) << 2)) + +/* CPU interrupts can be detached from any peripheral source by setting the + * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29). + */ + +#define NO_CPUINT ESP32_CPUINT_TIMER0 + /**************************************************************************** * Private Data ****************************************************************************/ @@ -270,7 +355,7 @@ int esp32_alloc_edgeint(void) } leave_critical_section(flags); - return ret; + return ret; } /**************************************************************************** @@ -321,7 +406,24 @@ void esp32_free_edgeint(int cpuint) void esp32_attach_peripheral(int cpu, int periphid, int cpuint) { -# warning Missing logic + uintptr_t regaddr; + + DEBUGASSERT(periphid >= 0 && periphid < NR_PERIPHERALS); + DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX); +#ifdef CONFIG_SMP + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); + + if (cpu != 0) + { + regaddr = DPORT_APP_MAP_REGADDR(periphid); + } + else +#endif + { + regaddr = DPORT_PRO_MAP_REGADDR(periphid); + } + + putreg(cpuint, regaddr); } /**************************************************************************** @@ -332,14 +434,30 @@ void esp32_attach_peripheral(int cpu, int periphid, int cpuint) * * Input Parameters: * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * cpuint - The CPU interrupt to receive the peripheral interrupt + * periphid - The peripheral number from ira.h to be assigned. * * Returned Value: * None * ****************************************************************************/ -void esp32_detach_peripheral(int cpu, int cpuint) +void esp32_detach_peripheral(int cpu, int periphid) { -# warning Missing logic + uintptr_t regaddr; + + DEBUGASSERT(periphid >= 0 && periphid < NR_PERIPHERALS); +#ifdef CONFIG_SMP + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); + + if (cpu != 0) + { + regaddr = DPORT_APP_MAP_REGADDR(periphid); + } + else +#endif + { + regaddr = DPORT_PRO_MAP_REGADDR(periphid); + } + + putreg(NO_CPUINT, regaddr); } diff --git a/arch/xtensa/src/esp32/esp32_cpuint.h b/arch/xtensa/src/esp32/esp32_cpuint.h index f3bbbaf4a4..07af5ea8f3 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.h +++ b/arch/xtensa/src/esp32/esp32_cpuint.h @@ -124,7 +124,7 @@ void esp32_free_edgeint(int cpuint); * * Input Parameters: * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from ira.h to be assigned. + * periphid - The peripheral number from ira.h to be attached. * cpuint - The CPU interrupt to receive the peripheral interrupt * * Returned Value: @@ -142,13 +142,13 @@ void esp32_attach_peripheral(int cpu, int periphid, int cpuint); * * Input Parameters: * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * cpuint - The CPU interrupt to receive the peripheral interrupt + * periphid - The peripheral number from ira.h to be detached. * * Returned Value: * None * ****************************************************************************/ -void esp32_detach_peripheral(int cpu, int cpuint); +void esp32_detach_peripheral(int cpu, int periphid); #endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CPUINT_H */ diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 1f4a6d4c01..ec5d0c7d06 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -120,6 +120,7 @@ static inline void xtensa_disable_all(void) int xtensa_start_handler(int irq, FAR void *context) { FAR struct tcb_s *tcb; + int i; sinfo("CPU%d Started\n", up_cpu_index()); @@ -145,8 +146,12 @@ int xtensa_start_handler(int irq, FAR void *context) xtensa_disable_all(); - /* Disable peripheral sources from all PRO CPU interrupt */ -#warning Missing logic + /* Detach all peripheral sources APP CPU interrupts */ + + for (i = 0; i < NR_PERIPHERALS) + { + esp32_detach_peripheral(1, i);; + } /* Dump registers so that we can see what is going to happen on return */ diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index 6394beb8e1..010f05eb99 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -120,12 +120,18 @@ static inline void xtensa_disable_all(void) void xtensa_irq_initialize(void) { + int i; + /* Disable all PRO CPU interrupts */ xtensa_disable_all(); - /* Disable peripheral sources from all PRO CPU interrupt */ -#warning Missing logic + /* Detach all peripheral sources PRO CPU interrupts */ + + for (i = 0; i < NR_PERIPHERALS) + { + esp32_detach_peripheral(0, i);; + } #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 /* Colorize the interrupt stack for debug purposes */ @@ -133,9 +139,6 @@ void xtensa_irq_initialize(void) #warning Missing logic #endif - /* Set all interrupts (and exceptions) to the default priority */ -#warning Missing logic - /* Attach all processor exceptions */ #warning Missing logic diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c index 639934d535..3d031dc776 100644 --- a/arch/xtensa/src/esp32/esp32_timerisr.c +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -191,6 +191,10 @@ void xtensa_timer_initialize(void) count = xtensa_getcount(); xtensa_setcompare(count + divisor); + /* NOTE: Timer 0 is an internal interrupt source so we do not need to + * attach any peripheral ID to the dedicated CPU interrupt. + */ + /* Attach the timer interrupt vector */ (void)irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32_timerisr);