Merged in raiden00/nuttx_h7 (pull request #730)
Master * stm32h7/rcc: update rcc defs, add SPI clock configuration and some fixes in rcc * stm32h7: initial defs for SPI * stm32h7: initial defs for MDMA, DMA, BDMA and DMAMUX Approved-by: GregoryN <gnutt@nuttx.org>
This commit is contained in:
raiden00pl
GregoryN
parent
8eac8ee52a
commit
ff0640096f
52
arch/arm/src/stm32h7/chip/stm32_dma.h
Normal file
52
arch/arm/src/stm32h7/chip/stm32_dma.h
Normal file
@ -0,0 +1,52 @@
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/************************************************************************************
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* arch/arm/src/stm32h7/chip/stm32_dma.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
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* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMA_H
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#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMA_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32H7_STM32H7X3XX)
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# include "chip/stm32h7x3xx_dma.h"
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#else
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# error "Unsupported STM32 H7 sub family"
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#endif
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#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMA_H */
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52
arch/arm/src/stm32h7/chip/stm32_spi.h
Normal file
52
arch/arm/src/stm32h7/chip/stm32_spi.h
Normal file
@ -0,0 +1,52 @@
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/************************************************************************************
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* arch/arm/src/stm32h7/chip/stm32_spi.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_SPI_H
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#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_SPI_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32H7_STM32H7X3XX)
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# include "chip/stm32h7x3xx_spi.h"
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#else
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# error "Unsupported STM32 H7 sub family"
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#endif
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#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_SPI_H */
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1229
arch/arm/src/stm32h7/chip/stm32h7x3xx_dma.h
Normal file
1229
arch/arm/src/stm32h7/chip/stm32h7x3xx_dma.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -527,22 +527,22 @@
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/* Bit definitions for RCC_D2CCIP1R reigster */
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#define RCC_D2CCIP1R_SAI1SEL_SHIFT (0) /* Bits 0-2 */
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#define RCC_D2CCIP1R_SAI1SEL_SHIFT (0) /* Bits 0-2 */
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#define RCC_D2CCIP1R_SAI1SEL_MASK (7 << RCC_D2CCIP1R_SAI1SEL_MASK)
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# define RCC_D2CCIP1R_SAI1SEL_PLL1 (0 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 000 */
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# define RCC_D2CCIP1R_SAI1SEL_PLL2 (1 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 001 */
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# define RCC_D2CCIP1R_SAI1SEL_PLL3 (2 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 010 */
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# define RCC_D2CCIP1R_SAI1SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 011 */
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# define RCC_D2CCIP1R_SAI1SEL_PER (4 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 100 */
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/* Bits 3-5: Reserved */
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#define RCC_D2CCIP1R_SAI23SEL_SHIFT (6) /* Bits 6-8 */
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/* Bits 3-5: Reserved */
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#define RCC_D2CCIP1R_SAI23SEL_SHIFT (6) /* Bits 6-8 */
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#define RCC_D2CCIP1R_SAI23SEL_MASK (7 << RCC_D2CCIP1R_SAI23SEL_SHIFT)
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# define RCC_D2CCIP1R_SAI23SEL_PLL1 (0 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 000 */
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# define RCC_D2CCIP1R_SAI23SEL_PLL2 (1 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 001 */
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# define RCC_D2CCIP1R_SAI23SEL_PLL3 (2 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 010 */
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# define RCC_D2CCIP1R_SAI23SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 011 */
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# define RCC_D2CCIP1R_SAI23SEL_PER (4 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 100 */
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/* Bits 9-11: Reserved */
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/* Bits 9-11: Reserved */
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#define RCC_D2CCIP1R_SPI123SEL_SHIFT (12) /* Bits 12-14 */
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#define RCC_D2CCIP1R_SPI123SEL_MASK (7 << RCC_D2CCIP1R_SPI123SEL_SHIFT)
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# define RCC_D2CCIP1R_SPI123SEL_PLL1 (0 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 000 */
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@ -550,7 +550,7 @@
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# define RCC_D2CCIP1R_SPI123SEL_PLL3 (2 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 010 */
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# define RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 011 */
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# define RCC_D2CCIP1R_SPI123SEL_PER (4 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 100 */
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/* Bit 15: Reserved */
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/* Bit 15: Reserved */
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#define RCC_D2CCIP1R_SPI45SEL_SHIFT (16) /* Bits 16-18 */
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#define RCC_D2CCIP1R_SPI45SEL_MASK (7 << RCC_D2CCIP1R_SPI45SEL_SHIFT)
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# define RCC_D2CCIP1R_SPI45SEL_APB (0 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 000 */
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@ -559,25 +559,25 @@
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# define RCC_D2CCIP1R_SPI45SEL_HSI (3 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 011 */
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# define RCC_D2CCIP1R_SPI45SEL_CSI (4 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 100 */
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# define RCC_D2CCIP1R_SPI45SEL_HSE (5 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 101 */
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/* Bit 19: Reserved */
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/* Bit 19: Reserved */
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#define RCC_D2CCIP1R_SPDIFSEL_SHIFT (20) /* Bits 20-21 */
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#define RCC_D2CCIP1R_SPDIFSEL_MASK (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT)
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# define RCC_D2CCIP1R_SPDIFSEL_PLL1 (0 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) /* 00 */
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# define RCC_D2CCIP1R_SPDIFSEL_PLL2 (1 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) /* 01 */
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# define RCC_D2CCIP1R_SPDIFSEL_PLL3 (2 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) /* 10 */
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# define RCC_D2CCIP1R_SPDIFSEL_HSI (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) /* 11 */
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/* Bits 22-23: Reserved */
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/* Bits 22-23: Reserved */
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#define RCC_D2CCIP1R_DFSDM1SEL_SHIFT (24) /* Bit 24 */
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#define RCC_D2CCIP1R_DFSDM1SEL_MASK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT)
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# define RCC_D2CCIP1R_DFSDM1SEL_PCLK2 (0 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) /* 0 */
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# define RCC_D2CCIP1R_DFSDM1SEL_SYSCLK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) /* 1 */
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/* Bits 25-27: Reserved */
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/* Bits 25-27: Reserved */
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#define RCC_D2CCIP1R_FDCANSEL_SHIFT (28) /* Bits 28-29 */
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#define RCC_D2CCIP1R_FDCANSEL_MASK (3 << RCC_D2CCIP1R_FDCANSEL_SHIFT)
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# define RCC_D2CCIP1R_FDCANSEL_HSE (0 << RCC_D2CCIP1R_FDCANSEL_SHIFT) /* 00 */
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# define RCC_D2CCIP1R_FDCANSEL_PLL1 (1 << RCC_D2CCIP1R_FDCANSEL_SHIFT) /* 01 */
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# define RCC_D2CCIP1R_FDCANSEL_PLL2 (2 << RCC_D2CCIP1R_FDCANSEL_SHIFT) /* 10 */
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/* Bit 30: Reserved */
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/* Bit 30: Reserved */
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#define RCC_D2CCIP1R_SWPSEL_SHIFT (31) /* Bit 31 */
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#define RCC_D2CCIP1R_SWPSEL_MASK (1 << RCC_D2CCIP1R_SWPSEL_SHIFT)
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# define RCC_D2CCIP1R_SWPSEL_PCLK (0 << RCC_D2CCIP1R_SWPSEL_SHIFT) /* 0 */
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@ -596,13 +596,66 @@
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/* TODO: Bit definitions for RCC_D3CCIPR reigster */
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/* ... */
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#define RCC_D3CCIPR_I2C4SEL_SHIFT (8) /* Bits 8-9 */
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#define RCC_D3CCIPR_I2C4SEL_MASK (3 << RCC_D3CCIPR_I2C4SEL_SHIFT)
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# define RCC_D3CCIPR_I2C4SEL_PCLK4 (0 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 00 */
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# define RCC_D3CCIPR_I2C4SEL_PLL3 (1 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 01 */
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# define RCC_D3CCIPR_I2C4SEL_HSI (2 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 10 */
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# define RCC_D3CCIPR_I2C4SEL_CSI (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 11 */
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#define RCC_D3CCIPR_LPUART1SEL_SHIFT (0) /* Bits 0-2: LPUART1 kernel clock source selection */
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#define RCC_D3CCIPR_LPUART1SEL_MASK (7 << RCC_D3CCIPR_LPUART1SEL_SHIFT)
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# define RCC_D3CCIPR_LPUART1SEL_PCLK (0 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 000 */
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# define RCC_D3CCIPR_LPUART1SEL_PLL2 (1 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 001 */
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# define RCC_D3CCIPR_LPUART1SEL_PLL3 (2 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 010 */
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# define RCC_D3CCIPR_LPUART1SEL_HSI (3 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 011 */
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# define RCC_D3CCIPR_LPUART1SEL_CSI (4 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 100 */
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# define RCC_D3CCIPR_LPUART1SEL_LSE (5 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 101 */
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/* Bits 3-7: Reserved */
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#define RCC_D3CCIPR_I2C4SEL_SHIFT (8) /* Bits 8-9: I2C4 kernel clock source selection */
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#define RCC_D3CCIPR_I2C4SEL_MASK (3 << RCC_D3CCIPR_I2C4SEL_SHIFT)
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# define RCC_D3CCIPR_I2C4SEL_PCLK4 (0 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 00 */
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# define RCC_D3CCIPR_I2C4SEL_PLL3 (1 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 01 */
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# define RCC_D3CCIPR_I2C4SEL_HSI (2 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 10 */
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# define RCC_D3CCIPR_I2C4SEL_CSI (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 11 */
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#define RCC_D3CCIPR_LPTIM2SEL_SHIFT (10) /* Bits 10-12: LPTIM2 kernel clock source selection */
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#define RCC_D3CCIPR_LPTIM2SEL_MASK (7 << RCC_D3CCIPR_LPTIM2SEL_SHIFT)
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# define RCC_D3CCIPR_LPTIM2SEL_PCLK4 (0 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 000 */
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# define RCC_D3CCIPR_LPTIM2SEL_PLL2 (1 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 001 */
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# define RCC_D3CCIPR_LPTIM2SEL_PLL3 (2 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 010 */
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# define RCC_D3CCIPR_LPTIM2SEL_LSE (3 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 011 */
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# define RCC_D3CCIPR_LPTIM2SEL_LSI (4 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 100 */
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# define RCC_D3CCIPR_LPTIM2SEL_PER (5 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 101 */
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#define RCC_D3CCIPR_LPTIM345SEL_SHIFT (13) /* Bits 13-15: LPTIM3,4,5 kernel clock source selection */
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#define RCC_D3CCIPR_LPTIM345SEL_MASK (7 << RCC_D3CCIPR_LPTIM345SEL_SHIFT)
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# define RCC_D3CCIPR_LPTIM345SEL_PCLK4 (0 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 000 */
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# define RCC_D3CCIPR_LPTIM345SEL_PLL2 (1 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 001 */
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# define RCC_D3CCIPR_LPTIM345SEL_PLL3 (2 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 010 */
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# define RCC_D3CCIPR_LPTIM345SEL_LSE (3 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 011 */
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# define RCC_D3CCIPR_LPTIM345SEL_LSI (4 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 100 */
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# define RCC_D3CCIPR_LPTIM345SEL_PER (5 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 101 */
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#define RCC_D3CCIPR_ADCSEL_SHIFT (16) /* Bits 16-17: SAR ADC kernel clock source selection */
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#define RCC_D3CCIPR_ADCSEL_MASK (3 << RCC_D3CCIPR_ADCSEL_SHIFT)
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# define RCC_D3CCIPR_ADCSEL_PLL2 (0 << RCC_D3CCIPR_ADCSEL_SHIFT) /* 00 */
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# define RCC_D3CCIPR_ADCSEL_PLL3 (1 << RCC_D3CCIPR_ADCSEL_SHIFT) /* 01 */
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# define RCC_D3CCIPR_ADCSEL_PER (2 << RCC_D3CCIPR_ADCSEL_SHIFT) /* 10 */
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/* Bits 18-20: Reserved */
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#define RCC_D3CCIPR_SAI4ASEL_SHIFT (21) /* Bits 21-23: Sub-Block A of SAI4 kernel clock source selection */
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#define RCC_D3CCIPR_SAI4ASEL_MASK (7 << RCC_D3CCIPR_SAI4ASEL_SHIFT)
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# define RCC_D3CCIPR_SAI4ASEL_PLL1 (0 << RCC_D3CCIPR_SAI4ASEL_SHIFT) /* 000 */
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# define RCC_D3CCIPR_SAI4ASEL_PLL2 (1 << RCC_D3CCIPR_SAI4ASEL_SHIFT) /* 001 */
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# define RCC_D3CCIPR_SAI4ASEL_PLL3 (2 << RCC_D3CCIPR_SAI4ASEL_SHIFT) /* 010 */
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# define RCC_D3CCIPR_SAI4ASEL_I2CCKIN (3 << RCC_D3CCIPR_SAI4ASEL_SHIFT) /* 011 */
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# define RCC_D3CCIPR_SAI4ASEL_PER (4 << RCC_D3CCIPR_SAI4ASEL_SHIFT) /* 100 */
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#define RCC_D3CCIPR_SAI4BSEL_SHIFT (24) /* Bits 24-26: Sub-Block B of SAI4 kernel clock source selection */
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#define RCC_D3CCIPR_SAI4BSEL_MASK (7 << RCC_D3CCIPR_SAI4BSEL_SHIFT)
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# define RCC_D3CCIPR_SAI4BSEL_PLL1 (0 << RCC_D3CCIPR_SAI4BSEL_SHIFT) /* 000 */
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# define RCC_D3CCIPR_SAI4BSEL_PLL2 (1 << RCC_D3CCIPR_SAI4BSEL_SHIFT) /* 001 */
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# define RCC_D3CCIPR_SAI4BSEL_PLL3 (2 << RCC_D3CCIPR_SAI4BSEL_SHIFT) /* 010 */
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# define RCC_D3CCIPR_SAI4BSEL_I2CCKIN (3 << RCC_D3CCIPR_SAI4BSEL_SHIFT) /* 011 */
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# define RCC_D3CCIPR_SAI4BSEL_PER (4 << RCC_D3CCIPR_SAI4BSEL_SHIFT) /* 100 */
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#define RCC_D3CCIPR_SPI6SEL_SHIFT (28) /* Bits 28-30: SPI6 kernel clock source selection */
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#define RCC_D3CCIPR_SPI6SEL_MASK (7 << RCC_D3CCIPR_SPI6SEL_SHIFT)
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# define RCC_D3CCIPR_SPI6SEL_PCLK4 (0 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 000 */
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# define RCC_D3CCIPR_SPI6SEL_PLL2 (1 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 001 */
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# define RCC_D3CCIPR_SPI6SEL_PLL3 (2 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 010 */
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# define RCC_D3CCIPR_SPI6SEL_HSI (3 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 011 */
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# define RCC_D3CCIPR_SPI6SEL_CSI (4 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 100 */
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# define RCC_D3CCIPR_SPI6SEL_HSE (5 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 101 */
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/* Bit 31: Reserved */
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/* ... */
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/* TODO: CIER */
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@ -885,18 +938,26 @@
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/* APB4 Peripheral Clock enable register */
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#define RCC_APB4ENR_SYSCFGEN (0x2ul) /* RCC APB4ENR: SYSCFGEN */
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#define RCC_APB4ENR_LPUART1EN (0x8ul) /* RCC APB4ENR: LPUART1EN */
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#define RCC_APB4ENR_SPI6EN (0x20ul) /* RCC APB4ENR: SPI6EN */
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#define RCC_APB4ENR_I2C4EN (0x80ul) /* RCC APB4ENR: I2C4EN */
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#define RCC_APB4ENR_LPTIM2EN (0x200ul) /* RCC APB4ENR: LPTIM2EN */
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#define RCC_APB4ENR_LPTIM3EN (0x400ul) /* RCC APB4ENR: LPTIM3EN */
|
||||
#define RCC_APB4ENR_LPTIM4EN (0x800ul) /* RCC APB4ENR: LPTIM4EN */
|
||||
#define RCC_APB4ENR_LPTIM5EN (0x1000ul) /* RCC APB4ENR: LPTIM5EN */
|
||||
#define RCC_APB4ENR_COMP12EN (0x4000ul) /* RCC APB4ENR: COMP12EN */
|
||||
#define RCC_APB4ENR_VREFEN (0x8000ul) /* RCC APB4ENR: VREFEN */
|
||||
#define RCC_APB4ENR_RTCAPBEN (0x10000ul) /* RCC APB4ENR: RTCAPBEN */
|
||||
#define RCC_APB4ENR_SAI4EN (0x200000ul) /* RCC APB4ENR: SAI4EN */
|
||||
/* Bit 0: Reserved */
|
||||
#define RCC_APB4ENR_SYSCFGEN (1 << 1) /* Bit 1: RCC APB4ENR: SYSCFGEN */
|
||||
/* Bit 2: Reserved */
|
||||
#define RCC_APB4ENR_LPUART1EN (1 << 3) /* Bit 3: RCC APB4ENR: LPUART1EN */
|
||||
/* Bit 4: Reserved */
|
||||
#define RCC_APB4ENR_SPI6EN (1 << 5) /* Bit 5: RCC APB4ENR: SPI6EN */
|
||||
/* Bit 6: Reserved */
|
||||
#define RCC_APB4ENR_I2C4EN (1 << 7) /* Bit 7: RCC APB4ENR: I2C4EN */
|
||||
/* Bit 8: Reserved */
|
||||
#define RCC_APB4ENR_LPTIM2EN (1 << 9) /* Bit 9: RCC APB4ENR: LPTIM2EN */
|
||||
#define RCC_APB4ENR_LPTIM3EN (1 << 10) /* Bit 10: RCC APB4ENR: LPTIM3EN */
|
||||
#define RCC_APB4ENR_LPTIM4EN (1 << 11) /* Bit 11: RCC APB4ENR: LPTIM4EN */
|
||||
#define RCC_APB4ENR_LPTIM5EN (1 << 12) /* Bit 12: RCC APB4ENR: LPTIM5EN */
|
||||
/* Bit 13: Reserved */
|
||||
#define RCC_APB4ENR_COMP12EN (1 << 14) /* Bit 14: RCC APB4ENR: COMP12EN */
|
||||
#define RCC_APB4ENR_VREFEN (1 << 15) /* Bit 15: RCC APB4ENR: VREFEN */
|
||||
#define RCC_APB4ENR_RTCAPBEN (1 << 16) /* Bit 16: RCC APB4ENR: RTCAPBEN */
|
||||
/* Bits 17-20: Reserved */
|
||||
#define RCC_APB4ENR_SAI4EN (1 << 21) /* Bit 21: RCC APB4ENR: SAI4EN */
|
||||
/* Bit2 22-31: Reserved */
|
||||
|
||||
/* AHB3 low power mode peripheral clock enable register */
|
||||
|
||||
|
||||
279
arch/arm/src/stm32h7/chip/stm32h7x3xx_spi.h
Normal file
279
arch/arm/src/stm32h7/chip/stm32h7x3xx_spi.h
Normal file
@ -0,0 +1,279 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32h7/chip/stm32h7x3xx_spi.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_SPI_H
|
||||
#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_SPI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#if defined(CONFIG_STM32H7_STM32H7X3XX)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Maximum allowed speed as per data sheet for all SPIs */
|
||||
|
||||
# define STM32_SPI_CLK_MAX 150000000UL
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI/I2S Control Register 1 */
|
||||
#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 */
|
||||
#define STM32_SPI_CFG1_OFFSET 0x0008 /* SPI configuration register 1 */
|
||||
#define STM32_SPI_CFG2_OFFSET 0x000C /* SPI configuration register 2 */
|
||||
#define STM32_SPI_IER_OFFSET 0x0010 /* SPI/I2S interupt enable register */
|
||||
#define STM32_SPI_SR_OFFSET 0x0014 /* SPI/I2S status register */
|
||||
#define STM32_SPI_IFCR_OFFSET 0x0018 /* SPI/I2S interrupt/status flags clear register */
|
||||
#define STM32_SPI_TXDR_OFFSET 0x0020 /* SPI/I2S transmit data register */
|
||||
#define STM32_SPI_RXDR_OFFSET 0x0030 /* SPI/I2S receive data register */
|
||||
#define STM32_SPI_CRCPOLY_OFFSET 0x0040 /* SPI/I2S SPI polynominal register */
|
||||
#define STM32_SPI_TXCRC_OFFSET 0x0044 /* SPI/I2S SPI transmitter CRC register */
|
||||
#define STM32_SPI_RXCRC_OFFSET 0x0048 /* SPI/I2S SPI receiver CRC register */
|
||||
#define STM32_SPI_UDRDR_OFFSET 0x004C /* SPI/I2S SPI underrun data register */
|
||||
#define STM32_SPI_I2SCFGR_OFFSET 0x0050 /* SPI/I2S configuration register*/
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32H7_NSPI > 0
|
||||
# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI1_CFG1 (STM32_SPI1_BASE+STM32_SPI_CFG1_OFFSET)
|
||||
# define STM32_SPI1_CFG2 (STM32_SPI1_BASE+STM32_SPI_CFG2_OFFSET)
|
||||
# define STM32_SPI1_IER (STM32_SPI1_BASE+STM32_SPI_IER_OFFSET)
|
||||
# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI1_IFCR (STM32_SPI1_BASE+STM32_SPI_IFCR_OFFSET)
|
||||
# define STM32_SPI1_TXDR (STM32_SPI1_BASE+STM32_SPI_TXDR_OFFSET)
|
||||
# define STM32_SPI1_RXDR (STM32_SPI1_BASE+STM32_SPI_RXDR_OFFSET)
|
||||
# define STM32_SPI1_CRCPOLY (STM32_SPI1_BASE+STM32_SPI_CRCPOLY_OFFSET)
|
||||
# define STM32_SPI1_TXCRC (STM32_SPI1_BASE+STM32_SPI_TXCRC_OFFSET)
|
||||
# define STM32_SPI1_RXCRC (STM32_SPI1_BASE+STM32_SPI_RXCRC_OFFSET)
|
||||
# define STM32_SPI1_UDRDR (STM32_SPI1_BASE+STM32_SPI_UDRDR_OFFSET)
|
||||
# define STM32_SPI1_I2SCFGR (STM32_SPI1_BASE+STM32_SPI_I2SCFGR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32H7_NSPI > 1
|
||||
# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI2_CFG1 (STM32_SPI2_BASE+STM32_SPI_CFG1_OFFSET)
|
||||
# define STM32_SPI2_CFG2 (STM32_SPI2_BASE+STM32_SPI_CFG2_OFFSET)
|
||||
# define STM32_SPI2_IER (STM32_SPI2_BASE+STM32_SPI_IER_OFFSET)
|
||||
# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI2_IFCR (STM32_SPI2_BASE+STM32_SPI_IFCR_OFFSET)
|
||||
# define STM32_SPI2_TXDR (STM32_SPI2_BASE+STM32_SPI_TXDR_OFFSET)
|
||||
# define STM32_SPI2_RXDR (STM32_SPI2_BASE+STM32_SPI_RXDR_OFFSET)
|
||||
# define STM32_SPI2_CRCPOLY (STM32_SPI2_BASE+STM32_SPI_CRCPOLY_OFFSET)
|
||||
# define STM32_SPI2_TXCRC (STM32_SPI2_BASE+STM32_SPI_TXCRC_OFFSET)
|
||||
# define STM32_SPI2_RXCRC (STM32_SPI2_BASE+STM32_SPI_RXCRC_OFFSET)
|
||||
# define STM32_SPI2_UDRDR (STM32_SPI2_BASE+STM32_SPI_UDRDR_OFFSET)
|
||||
# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32H7_NSPI > 2
|
||||
# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI3_CFG1 (STM32_SPI3_BASE+STM32_SPI_CFG1_OFFSET)
|
||||
# define STM32_SPI3_CFG2 (STM32_SPI3_BASE+STM32_SPI_CFG2_OFFSET)
|
||||
# define STM32_SPI3_IER (STM32_SPI3_BASE+STM32_SPI_IER_OFFSET)
|
||||
# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI3_IFCR (STM32_SPI3_BASE+STM32_SPI_IFCR_OFFSET)
|
||||
# define STM32_SPI3_TXDR (STM32_SPI3_BASE+STM32_SPI_TXDR_OFFSET)
|
||||
# define STM32_SPI3_RXDR (STM32_SPI3_BASE+STM32_SPI_RXDR_OFFSET)
|
||||
# define STM32_SPI3_CRCPOLY (STM32_SPI3_BASE+STM32_SPI_CRCPOLY_OFFSET)
|
||||
# define STM32_SPI3_TXCRC (STM32_SPI3_BASE+STM32_SPI_TXCRC_OFFSET)
|
||||
# define STM32_SPI3_RXCRC (STM32_SPI3_BASE+STM32_SPI_RXCRC_OFFSET)
|
||||
# define STM32_SPI3_UDRDR (STM32_SPI3_BASE+STM32_SPI_UDRDR_OFFSET)
|
||||
# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32H7_NSPI > 3
|
||||
# define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI4_CFG1 (STM32_SPI4_BASE+STM32_SPI_CFG1_OFFSET)
|
||||
# define STM32_SPI4_CFG2 (STM32_SPI4_BASE+STM32_SPI_CFG2_OFFSET)
|
||||
# define STM32_SPI4_IER (STM32_SPI4_BASE+STM32_SPI_IER_OFFSET)
|
||||
# define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI4_IFCR (STM32_SPI4_BASE+STM32_SPI_IFCR_OFFSET)
|
||||
# define STM32_SPI4_TXDR (STM32_SPI4_BASE+STM32_SPI_TXDR_OFFSET)
|
||||
# define STM32_SPI4_RXDR (STM32_SPI4_BASE+STM32_SPI_RXDR_OFFSET)
|
||||
# define STM32_SPI4_CRCPOLY (STM32_SPI4_BASE+STM32_SPI_CRCPOLY_OFFSET)
|
||||
# define STM32_SPI4_TXCRC (STM32_SPI4_BASE+STM32_SPI_TXCRC_OFFSET)
|
||||
# define STM32_SPI4_RXCRC (STM32_SPI4_BASE+STM32_SPI_RXCRC_OFFSET)
|
||||
# define STM32_SPI4_UDRDR (STM32_SPI4_BASE+STM32_SPI_UDRDR_OFFSET)
|
||||
# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32H7_NSPI > 4
|
||||
# define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI5_CFG1 (STM32_SPI5_BASE+STM32_SPI_CFG1_OFFSET)
|
||||
# define STM32_SPI5_CFG2 (STM32_SPI5_BASE+STM32_SPI_CFG2_OFFSET)
|
||||
# define STM32_SPI5_IER (STM32_SPI5_BASE+STM32_SPI_IER_OFFSET)
|
||||
# define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI5_IFCR (STM32_SPI5_BASE+STM32_SPI_IFCR_OFFSET)
|
||||
# define STM32_SPI5_TXDR (STM32_SPI5_BASE+STM32_SPI_TXDR_OFFSET)
|
||||
# define STM32_SPI5_RXDR (STM32_SPI5_BASE+STM32_SPI_RXDR_OFFSET)
|
||||
# define STM32_SPI5_CRCPOLY (STM32_SPI5_BASE+STM32_SPI_CRCPOLY_OFFSET)
|
||||
# define STM32_SPI5_TXCRC (STM32_SPI5_BASE+STM32_SPI_TXCRC_OFFSET)
|
||||
# define STM32_SPI5_RXCRC (STM32_SPI5_BASE+STM32_SPI_RXCRC_OFFSET)
|
||||
# define STM32_SPI5_UDRDR (STM32_SPI5_BASE+STM32_SPI_UDRDR_OFFSET)
|
||||
# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32H7_NSPI > 5
|
||||
# define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI6_CFG1 (STM32_SPI6_BASE+STM32_SPI_CFG1_OFFSET)
|
||||
# define STM32_SPI6_CFG2 (STM32_SPI6_BASE+STM32_SPI_CFG2_OFFSET)
|
||||
# define STM32_SPI6_IER (STM32_SPI6_BASE+STM32_SPI_IER_OFFSET)
|
||||
# define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI6_IFCR (STM32_SPI6_BASE+STM32_SPI_IFCR_OFFSET)
|
||||
# define STM32_SPI6_TXDR (STM32_SPI6_BASE+STM32_SPI_TXDR_OFFSET)
|
||||
# define STM32_SPI6_RXDR (STM32_SPI6_BASE+STM32_SPI_RXDR_OFFSET)
|
||||
# define STM32_SPI6_CRCPOLY (STM32_SPI6_BASE+STM32_SPI_CRCPOLY_OFFSET)
|
||||
# define STM32_SPI6_TXCRC (STM32_SPI6_BASE+STM32_SPI_TXCRC_OFFSET)
|
||||
# define STM32_SPI6_RXCRC (STM32_SPI6_BASE+STM32_SPI_RXCRC_OFFSET)
|
||||
# define STM32_SPI6_UDRDR (STM32_SPI6_BASE+STM32_SPI_UDRDR_OFFSET)
|
||||
# define STM32_SPI6_I2SCFGR (STM32_SPI6_BASE+STM32_SPI_I2SCFGR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* SPI Control Register 1 */
|
||||
|
||||
#define SPI_CR1_SPE (1 << 0) /* Bit 0: SPI Enable */
|
||||
/* Bits 1-7: Reserved */
|
||||
#define SPI_CR1_MASRX (1 << 8) /* Bit 8: */
|
||||
#define SPI_CR1_CSTART (1 << 9) /* Bit 9: master transfer start */
|
||||
#define SPI_CR1_CSUSP (1 << 10) /* Bit 10: master suspend request */
|
||||
#define SPI_CR1_HDDIR (1 << 11) /* Bit 11: RX/TX direction at Half-duplex mode */
|
||||
#define SPI_CR1_SSI (1 << 12) /* Bit 12: Internal slave select */
|
||||
#define SPI_CR1_CRC33_17 (1 << 13) /* Bit 13: 32-bit CRC polynominal configuration */
|
||||
#define SPI_CR1_RCRCINI (1 << 14) /* Bit 14: CRC calculation initialization pattern control for receiver */
|
||||
#define SPI_CR1_TCRCINI (1 << 15) /* Bit 15: CRC calculation initialization pattern control for transmitter */
|
||||
#define SPI_CR1_IOLOCK (1 << 16) /* Bit 16: locking the AF configuration of associated IOs */
|
||||
/* Bits 17-31: Reserved */
|
||||
|
||||
/* SPI Control Register 2 */
|
||||
|
||||
#define SPI_CR2_TSIZE_SHIFT (0) /* Bits 0-15 */
|
||||
#define SPI_CR2_TSIZE_MASK (0xff << SPI_CR2_TSIZE_SHIFT)
|
||||
#define SPI_CR2_TSER_SHIFT (16) /* Bits 16-31 */
|
||||
#define SPI_CR2_TSER_MASK (0xff << SPI_CR2_TSER_SHIFT)
|
||||
|
||||
/* TODO: SPI configuration register 1 */
|
||||
|
||||
/* TODO: SPI configuration register 2 */
|
||||
|
||||
/* SPI/I2S status register */
|
||||
|
||||
#define SPI_SR_RXP (1 << 0) /* Bit 0: Rx-packet available */
|
||||
#define SPI_SR_TXP (1 << 1) /* Bit 1: Tx-packet space available */
|
||||
#define SPI_SR_DXP (1 << 2) /* Bit 2: duplex packet */
|
||||
#define SPI_SR_EOT (1 << 3) /* Bit 3: end of transfer */
|
||||
#define SPI_SR_TXTF (1 << 4) /* Bit 4: transmission transfer filled */
|
||||
#define SPI_SR_UDR (1 << 5) /* Bit 5: underrun at slave transmission mode */
|
||||
#define SPI_SR_OVR (1 << 6) /* Bit 6: overrun */
|
||||
#define SPI_SR_CRCE (1 << 7) /* Bit 7: CRC error */
|
||||
#define SPI_SR_TIFRE (1 << 8) /* Bit 8: TI frame format error */
|
||||
#define SPI_SR_MODF (1 << 9) /* Bit 9: mode fault */
|
||||
#define SPI_SR_TSERF (1 << 10) /* Bit 10: additional number of SPI data to be transacted was reload */
|
||||
#define SPI_SR_SUSP (1 << 11) /* Bit 11: suspend */
|
||||
#define SPI_SR_TXC (1 << 12) /* Bit 12: TxFIFO transmission complete */
|
||||
#define SPI_SR_RXPLVL_SHIFT (13) /* Bits 13-14: RxFIFO packing level */
|
||||
#define SPI_SR_RXPLVL_MASK (1 << SPI_SR_RXPLVL_SHIFT)
|
||||
#define SPI_SR_RXWNE (1 << 15) /* Bit 15: RxFIFO word not empty */
|
||||
#define SPI_SR_CTSIZE_SHIFT (16) /* Bits 16-31: number of data frames remaining in current TSIZE session */
|
||||
#define SPI_SR_CTSIZE_MASK (1 << SPI_SR_CTSIZE_SHIFT)
|
||||
|
||||
/* SPI/I2S interrupt/status flags clear register */
|
||||
|
||||
/* Bits 0-2: Reserved */
|
||||
#define SPI_IFCR_EOTC (1 << 3) /* Bit 3: end of transfer flag clear */
|
||||
#define SPI_IFCR_TXTFC (1 << 4) /* Bit 4: transmission Transfer Flilled flag clear */
|
||||
#define SPI_IFCR_UDRC (1 << 5) /* Bit 5: underrun flag clear */
|
||||
#define SPI_IFCR_OVRC (1 << 6) /* Bit 6: overrun flag clear */
|
||||
#define SPI_IFCR_CRCEC (1 << 7) /* Bit 7: CRC error flag clear */
|
||||
#define SPI_IFCR_TIFREC (1 << 8) /* Bit 8: TI frame format error flag clear */
|
||||
#define SPI_IFCR_MODFC (1 << 9) /* Bit 9: mode fault flag clear */
|
||||
#define SPI_IFCR_TSERFC (1 << 10) /* Bit 10: TSERF flag clear*/
|
||||
#define SPI_IFCR_SUSPC (1 << 11) /* Bit 11: suspend flag clear */
|
||||
/* Bits 12-31: Reserved */
|
||||
|
||||
/* SPI/I2S transmit data register */
|
||||
|
||||
#define SPI_TXDR_TXDR_SHIFT (0) /* Bits 0-15: transmit data register */
|
||||
#define SPI_TXDR_TXDR_MASK (0xffff << SPI_TXDR_TXDR_SHIFT)
|
||||
/* Bits 16-31: write ignored */
|
||||
|
||||
/* SPI/I2S receive data register */
|
||||
|
||||
#define SPI_RXDR_RXDR_SHIFT (0) /* Bits 0-15: receive data register */
|
||||
#define SPI_RXDR_RXDR_MASK (0xffff << SPI_RXDR_RXDR_SHIFT)
|
||||
/* Bits 16-31: read zero */
|
||||
|
||||
/* SPI/I2S SPI polynominal register */
|
||||
|
||||
#define SPI_CRCPOLY_CRCPOLY_SHIFT (0) /* Bits 0-15: CRC polynominal register */
|
||||
#define SPI_CRCPOLY_CRCPOLY_MASK (0xffff << SPI_CRCPOLY_CRCPOLY_SHIFT)
|
||||
/* Bits 16-31: write ignored */
|
||||
|
||||
/* SPI/I2S SPI transmitter CRC register */
|
||||
|
||||
#define SPI_TXCRC_TXCRC_SHIFT (0) /* Bits 0-15: CRC register for transmitter */
|
||||
#define SPI_TXCRC_TXCRC_MASK (0xffff << SPI_TXCRC_TXCRC_SHIFT)
|
||||
/* Bits 16-31: write ignored */
|
||||
|
||||
/* SPI/I2S SPI receiver CRC register */
|
||||
|
||||
#define SPI_RXCRC_RXCRC_SHIFT (0) /* Bits 0-15: CRC register for receiver */
|
||||
#define SPI_RXCRC_RXCRC_MASK (0xffff << SPI_RXCRC_RXCRC_SHIFT)
|
||||
/* Bits 16-31: read zero */
|
||||
|
||||
/* SPI/I2S SPI underrun data register */
|
||||
|
||||
#define SPI_UDRDR_UDRDR_SHIFT (0) /* Bits 0-15: data at slave underrun condition*/
|
||||
#define SPI_UDRDR_UDRDR_MASK (0xffff << SPI_UDRDR_UDRDR_SHIFT)
|
||||
/* Bits 16-31: read zero */
|
||||
|
||||
/* TODO: SPI/I2S configuration register*/
|
||||
|
||||
|
||||
#endif /* CONFIG_STM32H7_STM32H7X3XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_SPI_H */
|
||||
@ -290,30 +290,36 @@ static inline void rcc_enableapb1(void)
|
||||
regval = getreg32(STM32_RCC_APB1LENR);
|
||||
|
||||
|
||||
#ifdef CONFIG_STM32F7_I2C1
|
||||
#ifdef CONFIG_STM32H7_SPI2
|
||||
/* SPI2 clock enable */
|
||||
|
||||
regval |= RCC_APB1LENR_SPI2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI3
|
||||
/* SPI3 clock enable */
|
||||
|
||||
regval |= RCC_APB1LENR_SPI3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_I2C1
|
||||
/* I2C1 clock enable */
|
||||
|
||||
regval |= RCC_APB1LENR_I2C1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_I2C2
|
||||
#ifdef CONFIG_STM32H7_I2C2
|
||||
/* I2C2 clock enable */
|
||||
|
||||
regval |= RCC_APB1LENR_I2C2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_I2C3
|
||||
#ifdef CONFIG_STM32H7_I2C3
|
||||
/* I2C3 clock enable */
|
||||
|
||||
regval |= RCC_APB1LENR_I2C3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_I2C4
|
||||
/* I2C4 clock enable */
|
||||
|
||||
regval |= RCC_APB1LENR_I2C4EN;
|
||||
#endif
|
||||
|
||||
// TODO: ...
|
||||
|
||||
putreg32(regval, STM32_RCC_APB1LENR); /* Enable APB1L peripherals */
|
||||
@ -343,6 +349,24 @@ static inline void rcc_enableapb2(void)
|
||||
|
||||
regval = getreg32(STM32_RCC_APB2ENR);
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI1
|
||||
/* SPI1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SPI1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI4
|
||||
/* SPI4 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SPI4EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI5
|
||||
/* SPI5 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SPI5EN;
|
||||
#endif
|
||||
|
||||
// TODO: ...
|
||||
|
||||
putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */
|
||||
@ -389,6 +413,18 @@ static inline void rcc_enableapb4(void)
|
||||
|
||||
regval = getreg32(STM32_RCC_APB4ENR);
|
||||
|
||||
#ifdef CONFIG_STM32H7_I2C4
|
||||
/* I2C4 clock enable */
|
||||
|
||||
regval |= RCC_APB4ENR_I2C4EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI6
|
||||
/* SPI6 clock enable */
|
||||
|
||||
regval |= RCC_APB4ENR_SPI6EN;
|
||||
#endif
|
||||
|
||||
// TODO: ...
|
||||
|
||||
putreg32(regval, STM32_RCC_APB4ENR); /* Enable peripherals */
|
||||
@ -618,6 +654,29 @@ static void stm32_stdclockconfig(void)
|
||||
putreg32(regval, STM32_RCC_D3CCIPR);
|
||||
#endif
|
||||
|
||||
/* Configure SPI source clock */
|
||||
|
||||
#if defined(STM32_RCC_D2CCIP1R_SPI123SRC)
|
||||
regval = getreg32(STM32_RCC_D2CCIP1R);
|
||||
regval &= ~RCC_D2CCIP1R_SPI123SEL_MASK;
|
||||
regval |= STM32_RCC_D2CCIP1R_SPI123SRC;
|
||||
putreg32(regval, STM32_RCC_D2CCIP1R);
|
||||
#endif
|
||||
|
||||
#if defined(STM32_RCC_D2CCIP1R_SPI45SRC)
|
||||
regval = getreg32(STM32_RCC_D2CCIP1R);
|
||||
regval &= ~RCC_D2CCIP1R_SPI45SEL_MASK;
|
||||
regval |= STM32_RCC_D2CCIP1R_SPI45SRC;
|
||||
putreg32(regval, STM32_RCC_D2CCIP1R);
|
||||
#endif
|
||||
|
||||
#if defined(STM32_RCC_D3CCIPR_SPI6SRC)
|
||||
regval = getreg32(STM32_RCC_D3CCIPR);
|
||||
regval &= ~RCC_D3CCIPR_SPI6SEL_MASK;
|
||||
regval |= STM32_RCC_D3CCIPR_SPI6SRC;
|
||||
putreg32(regval, STM32_RCC_D3CCIPR);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK)
|
||||
/* Low speed internal clock source LSI */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user