diff --git a/arch/arm/src/stm32h7/chip/stm32_dma.h b/arch/arm/src/stm32h7/chip/stm32_dma.h new file mode 100644 index 0000000000..45b96ba8c9 --- /dev/null +++ b/arch/arm/src/stm32h7/chip/stm32_dma.h @@ -0,0 +1,52 @@ +/************************************************************************************ + * arch/arm/src/stm32h7/chip/stm32_dma.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMA_H +#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMA_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_STM32H7_STM32H7X3XX) +# include "chip/stm32h7x3xx_dma.h" +#else +# error "Unsupported STM32 H7 sub family" +#endif + +#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMA_H */ diff --git a/arch/arm/src/stm32h7/chip/stm32_spi.h b/arch/arm/src/stm32h7/chip/stm32_spi.h new file mode 100644 index 0000000000..8eab3d9167 --- /dev/null +++ b/arch/arm/src/stm32h7/chip/stm32_spi.h @@ -0,0 +1,52 @@ +/************************************************************************************ + * arch/arm/src/stm32h7/chip/stm32_spi.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_SPI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_STM32H7_STM32H7X3XX) +# include "chip/stm32h7x3xx_spi.h" +#else +# error "Unsupported STM32 H7 sub family" +#endif + +#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_SPI_H */ diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_dma.h b/arch/arm/src/stm32h7/chip/stm32h7x3xx_dma.h new file mode 100644 index 0000000000..64836ad2a6 --- /dev/null +++ b/arch/arm/src/stm32h7/chip/stm32h7x3xx_dma.h @@ -0,0 +1,1229 @@ +/************************************************************************************ + * arch/arm/src/stm32h7/chip/stm32h7x3xx_dma.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_DMA_H +#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_DMA_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_STM32H7_STM32H7X3XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* DMA ******************************************************************************/ + +/* 2 DMA controllers */ + +#define DMA1 (0) +#define DMA2 (1) + +/* 8 DMA streams */ + +#define DMA_STREAM0 (0) +#define DMA_STREAM1 (1) +#define DMA_STREAM2 (2) +#define DMA_STREAM3 (3) +#define DMA_STREAM4 (4) +#define DMA_STREAM5 (5) +#define DMA_STREAM6 (6) +#define DMA_STREAM7 (7) + +/* Register Offsets *****************************************************************/ + +#define STM32_DMA_LISR_OFFSET 0x0000 /* DMA low interrupt status register */ +#define STM32_DMA_HISR_OFFSET 0x0004 /* DMA high interrupt status register */ +#define STM32_DMA_LIFCR_OFFSET 0x0008 /* DMA low interrupt flag clear register */ +#define STM32_DMA_HIFCR_OFFSET 0x000c /* DMA high interrupt flag clear register */ + +#define STM32_DMA_OFFSET(n) (0x0010+0x0018*(n)) +#define STM32_DMA_SCR_OFFSET 0x0000 /* DMA stream n configuration register */ +#define STM32_DMA_SNDTR_OFFSET 0x0004 /* DMA stream n number of data register */ +#define STM32_DMA_SPAR_OFFSET 0x0008 /* DMA stream n peripheral address register */ +#define STM32_DMA_SM0AR_OFFSET 0x000c /* DMA stream n memory 0 address register */ +#define STM32_DMA_SM1AR_OFFSET 0x0010 /* DMA stream n memory 1 address register */ +#define STM32_DMA_SFCR_OFFSET 0x0014 /* DMA stream n FIFO control register */ + +#define STM32_DMA_S0CR_OFFSET 0x0010 /* DMA stream 0 configuration register */ +#define STM32_DMA_S1CR_OFFSET 0x0028 /* DMA stream 1 configuration register */ +#define STM32_DMA_S2CR_OFFSET 0x0040 /* DMA stream 2 configuration register */ +#define STM32_DMA_S3CR_OFFSET 0x0058 /* DMA stream 3 configuration register */ +#define STM32_DMA_S4CR_OFFSET 0x0070 /* DMA stream 4 configuration register */ +#define STM32_DMA_S5CR_OFFSET 0x0088 /* DMA stream 5 configuration register */ +#define STM32_DMA_S6CR_OFFSET 0x00a0 /* DMA stream 6 configuration register */ +#define STM32_DMA_S7CR_OFFSET 0x00b8 /* DMA stream 7 configuration register */ + +#define STM32_DMA_S0NDTR_OFFSET 0x0014 /* DMA stream 0 number of data register */ +#define STM32_DMA_S1NDTR_OFFSET 0x002c /* DMA stream 1 number of data register */ +#define STM32_DMA_S2NDTR_OFFSET 0x0044 /* DMA stream 2 number of data register */ +#define STM32_DMA_S3NDTR_OFFSET 0x005c /* DMA stream 3 number of data register */ +#define STM32_DMA_S4NDTR_OFFSET 0x0074 /* DMA stream 4 number of data register */ +#define STM32_DMA_S5NDTR_OFFSET 0x008c /* DMA stream 5 number of data register */ +#define STM32_DMA_S6NDTR_OFFSET 0x00a4 /* DMA stream 6 number of data register */ +#define STM32_DMA_S7NDTR_OFFSET 0x00bc /* DMA stream 7 number of data register */ + +#define STM32_DMA_S0PAR_OFFSET 0x0018 /* DMA stream 0 peripheral address register */ +#define STM32_DMA_S1PAR_OFFSET 0x0030 /* DMA stream 1 peripheral address register */ +#define STM32_DMA_S2PAR_OFFSET 0x0048 /* DMA stream 2 peripheral address register */ +#define STM32_DMA_S3PAR_OFFSET 0x0060 /* DMA stream 3 peripheral address register */ +#define STM32_DMA_S4PAR_OFFSET 0x0078 /* DMA stream 4 peripheral address register */ +#define STM32_DMA_S5PAR_OFFSET 0x0090 /* DMA stream 5 peripheral address register */ +#define STM32_DMA_S6PAR_OFFSET 0x00a8 /* DMA stream 6 peripheral address register */ +#define STM32_DMA_S7PAR_OFFSET 0x00c0 /* DMA stream 7 peripheral address register */ + +#define STM32_DMA_S0M0AR_OFFSET 0x001c /* DMA stream 0 memory 0 address register */ +#define STM32_DMA_S1M0AR_OFFSET 0x0034 /* DMA stream 1 memory 0 address register */ +#define STM32_DMA_S2M0AR_OFFSET 0x004c /* DMA stream 2 memory 0 address register */ +#define STM32_DMA_S3M0AR_OFFSET 0x0064 /* DMA stream 3 memory 0 address register */ +#define STM32_DMA_S4M0AR_OFFSET 0x007c /* DMA stream 4 memory 0 address register */ +#define STM32_DMA_S5M0AR_OFFSET 0x0094 /* DMA stream 5 memory 0 address register */ +#define STM32_DMA_S6M0AR_OFFSET 0x00ac /* DMA stream 6 memory 0 address register */ +#define STM32_DMA_S7M0AR_OFFSET 0x00c4 /* DMA stream 7 memory 0 address register */ + +#define STM32_DMA_S0M1AR_OFFSET 0x0020 /* DMA stream 0 memory 1 address register */ +#define STM32_DMA_S1M1AR_OFFSET 0x0038 /* DMA stream 1 memory 1 address register */ +#define STM32_DMA_S2M1AR_OFFSET 0x0050 /* DMA stream 2 memory 1 address register */ +#define STM32_DMA_S3M1AR_OFFSET 0x0068 /* DMA stream 3 memory 1 address register */ +#define STM32_DMA_S4M1AR_OFFSET 0x0080 /* DMA stream 4 memory 1 address register */ +#define STM32_DMA_S5M1AR_OFFSET 0x0098 /* DMA stream 5 memory 1 address register */ +#define STM32_DMA_S6M1AR_OFFSET 0x00b0 /* DMA stream 6 memory 1 address register */ +#define STM32_DMA_S7M1AR_OFFSET 0x00c8 /* DMA stream 7 memory 1 address register */ + +#define STM32_DMA_S0FCR_OFFSET 0x0024 /* DMA stream 0 FIFO control register */ +#define STM32_DMA_S1FCR_OFFSET 0x003c /* DMA stream 1 FIFO control register */ +#define STM32_DMA_S2FCR_OFFSET 0x0054 /* DMA stream 2 FIFO control register */ +#define STM32_DMA_S3FCR_OFFSET 0x006c /* DMA stream 3 FIFO control register */ +#define STM32_DMA_S4FCR_OFFSET 0x0084 /* DMA stream 4 FIFO control register */ +#define STM32_DMA_S5FCR_OFFSET 0x009c /* DMA stream 5 FIFO control register */ +#define STM32_DMA_S6FCR_OFFSET 0x00b4 /* DMA stream 6 FIFO control register */ +#define STM32_DMA_S7FCR_OFFSET 0x00cc /* DMA stream 7 FIFO control register */ + +/* Register Addresses ***************************************************************/ + +#define STM32_DMA1_LISRC (STM32_DMA1_BASE+STM32_DMA_LISR_OFFSET) +#define STM32_DMA1_HISRC (STM32_DMA1_BASE+STM32_DMA_HISR_OFFSET) +#define STM32_DMA1_LIFCR (STM32_DMA1_BASE+STM32_DMA_LIFCR_OFFSET) +#define STM32_DMA1_HIFCR (STM32_DMA1_BASE+STM32_DMA_HIFCR_OFFSET) + +#define STM32_DMA1_SCR(n) (STM32_DMA1_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0CR (STM32_DMA1_BASE+STM32_DMA_S0CR_OFFSET) +#define STM32_DMA1_S1CR (STM32_DMA1_BASE+STM32_DMA_S1CR_OFFSET) +#define STM32_DMA1_S2CR (STM32_DMA1_BASE+STM32_DMA_S2CR_OFFSET) +#define STM32_DMA1_S3CR (STM32_DMA1_BASE+STM32_DMA_S3CR_OFFSET) +#define STM32_DMA1_S4CR (STM32_DMA1_BASE+STM32_DMA_S4CR_OFFSET) +#define STM32_DMA1_S5CR (STM32_DMA1_BASE+STM32_DMA_S5CR_OFFSET) +#define STM32_DMA1_S6CR (STM32_DMA1_BASE+STM32_DMA_S6CR_OFFSET) +#define STM32_DMA1_S7CR (STM32_DMA1_BASE+STM32_DMA_S7CR_OFFSET) + +#define STM32_DMA1_SNDTR(n) (STM32_DMA1_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0NDTR (STM32_DMA1_BASE+STM32_DMA_S0NDTR_OFFSET) +#define STM32_DMA1_S1NDTR (STM32_DMA1_BASE+STM32_DMA_S1NDTR_OFFSET) +#define STM32_DMA1_S2NDTR (STM32_DMA1_BASE+STM32_DMA_S2NDTR_OFFSET) +#define STM32_DMA1_S3NDTR (STM32_DMA1_BASE+STM32_DMA_S3NDTR_OFFSET) +#define STM32_DMA1_S4NDTR (STM32_DMA1_BASE+STM32_DMA_S4NDTR_OFFSET) +#define STM32_DMA1_S5NDTR (STM32_DMA1_BASE+STM32_DMA_S5NDTR_OFFSET) +#define STM32_DMA1_S6NDTR (STM32_DMA1_BASE+STM32_DMA_S6NDTR_OFFSET) +#define STM32_DMA1_S7NDTR (STM32_DMA1_BASE+STM32_DMA_S7NDTR_OFFSET) + +#define STM32_DMA1_SPAR(n) (STM32_DMA1_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0PAR (STM32_DMA1_BASE+STM32_DMA_S0PAR_OFFSET) +#define STM32_DMA1_S1PAR (STM32_DMA1_BASE+STM32_DMA_S1PAR_OFFSET) +#define STM32_DMA1_S2PAR (STM32_DMA1_BASE+STM32_DMA_S2PAR_OFFSET) +#define STM32_DMA1_S3PAR (STM32_DMA1_BASE+STM32_DMA_S3PAR_OFFSET) +#define STM32_DMA1_S4PAR (STM32_DMA1_BASE+STM32_DMA_S4PAR_OFFSET) +#define STM32_DMA1_S5PAR (STM32_DMA1_BASE+STM32_DMA_S5PAR_OFFSET) +#define STM32_DMA1_S6PAR (STM32_DMA1_BASE+STM32_DMA_S6PAR_OFFSET) +#define STM32_DMA1_S7PAR (STM32_DMA1_BASE+STM32_DMA_S7PAR_OFFSET) + +#define STM32_DMA1_SM0AR(n) (STM32_DMA1_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0M0AR (STM32_DMA1_BASE+STM32_DMA_S0M0AR_OFFSET) +#define STM32_DMA1_S1M0AR (STM32_DMA1_BASE+STM32_DMA_S1M0AR_OFFSET) +#define STM32_DMA1_S2M0AR (STM32_DMA1_BASE+STM32_DMA_S2M0AR_OFFSET) +#define STM32_DMA1_S3M0AR (STM32_DMA1_BASE+STM32_DMA_S3M0AR_OFFSET) +#define STM32_DMA1_S4M0AR (STM32_DMA1_BASE+STM32_DMA_S4M0AR_OFFSET) +#define STM32_DMA1_S5M0AR (STM32_DMA1_BASE+STM32_DMA_S5M0AR_OFFSET) +#define STM32_DMA1_S6M0AR (STM32_DMA1_BASE+STM32_DMA_S6M0AR_OFFSET) +#define STM32_DMA1_S7M0AR (STM32_DMA1_BASE+STM32_DMA_S7M0AR_OFFSET) + +#define STM32_DMA1_SM1AR(n) (STM32_DMA1_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0M1AR (STM32_DMA1_BASE+STM32_DMA_S0M1AR_OFFSET) +#define STM32_DMA1_S1M1AR (STM32_DMA1_BASE+STM32_DMA_S1M1AR_OFFSET) +#define STM32_DMA1_S2M1AR (STM32_DMA1_BASE+STM32_DMA_S2M1AR_OFFSET) +#define STM32_DMA1_S3M1AR (STM32_DMA1_BASE+STM32_DMA_S3M1AR_OFFSET) +#define STM32_DMA1_S4M1AR (STM32_DMA1_BASE+STM32_DMA_S4M1AR_OFFSET) +#define STM32_DMA1_S5M1AR (STM32_DMA1_BASE+STM32_DMA_S5M1AR_OFFSET) +#define STM32_DMA1_S6M1AR (STM32_DMA1_BASE+STM32_DMA_S6M1AR_OFFSET) +#define STM32_DMA1_S7M1AR (STM32_DMA1_BASE+STM32_DMA_S7M1AR_OFFSET) + +#define STM32_DMA1_SFCR(n) (STM32_DMA1_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0FCR (STM32_DMA1_BASE+STM32_DMA_S0FCR_OFFSET) +#define STM32_DMA1_S1FCR (STM32_DMA1_BASE+STM32_DMA_S1FCR_OFFSET) +#define STM32_DMA1_S2FCR (STM32_DMA1_BASE+STM32_DMA_S2FCR_OFFSET) +#define STM32_DMA1_S3FCR (STM32_DMA1_BASE+STM32_DMA_S3FCR_OFFSET) +#define STM32_DMA1_S4FCR (STM32_DMA1_BASE+STM32_DMA_S4FCR_OFFSET) +#define STM32_DMA1_S5FCR (STM32_DMA1_BASE+STM32_DMA_S5FCR_OFFSET) +#define STM32_DMA1_S6FCR (STM32_DMA1_BASE+STM32_DMA_S6FCR_OFFSET) +#define STM32_DMA1_S7FCR (STM32_DMA1_BASE+STM32_DMA_S7FCR_OFFSET) + +#define STM32_DMA2_LISRC (STM32_DMA2_BASE+STM32_DMA_LISR_OFFSET) +#define STM32_DMA2_HISRC (STM32_DMA2_BASE+STM32_DMA_HISR_OFFSET) +#define STM32_DMA2_LIFCR (STM32_DMA2_BASE+STM32_DMA_LIFCR_OFFSET) +#define STM32_DMA2_HIFCR (STM32_DMA2_BASE+STM32_DMA_HIFCR_OFFSET) + +#define STM32_DMA2_SCR(n) (STM32_DMA2_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0CR (STM32_DMA2_BASE+STM32_DMA_S0CR_OFFSET) +#define STM32_DMA2_S1CR (STM32_DMA2_BASE+STM32_DMA_S1CR_OFFSET) +#define STM32_DMA2_S2CR (STM32_DMA2_BASE+STM32_DMA_S2CR_OFFSET) +#define STM32_DMA2_S3CR (STM32_DMA2_BASE+STM32_DMA_S3CR_OFFSET) +#define STM32_DMA2_S4CR (STM32_DMA2_BASE+STM32_DMA_S4CR_OFFSET) +#define STM32_DMA2_S5CR (STM32_DMA2_BASE+STM32_DMA_S5CR_OFFSET) +#define STM32_DMA2_S6CR (STM32_DMA2_BASE+STM32_DMA_S6CR_OFFSET) +#define STM32_DMA2_S7CR (STM32_DMA2_BASE+STM32_DMA_S7CR_OFFSET) + +#define STM32_DMA2_SNDTR(n) (STM32_DMA2_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0NDTR (STM32_DMA2_BASE+STM32_DMA_S0NDTR_OFFSET) +#define STM32_DMA2_S1NDTR (STM32_DMA2_BASE+STM32_DMA_S1NDTR_OFFSET) +#define STM32_DMA2_S2NDTR (STM32_DMA2_BASE+STM32_DMA_S2NDTR_OFFSET) +#define STM32_DMA2_S3NDTR (STM32_DMA2_BASE+STM32_DMA_S3NDTR_OFFSET) +#define STM32_DMA2_S4NDTR (STM32_DMA2_BASE+STM32_DMA_S4NDTR_OFFSET) +#define STM32_DMA2_S5NDTR (STM32_DMA2_BASE+STM32_DMA_S5NDTR_OFFSET) +#define STM32_DMA2_S6NDTR (STM32_DMA2_BASE+STM32_DMA_S6NDTR_OFFSET) +#define STM32_DMA2_S7NDTR (STM32_DMA2_BASE+STM32_DMA_S7NDTR_OFFSET) + +#define STM32_DMA2_SPAR(n) (STM32_DMA2_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0PAR (STM32_DMA2_BASE+STM32_DMA_S0PAR_OFFSET) +#define STM32_DMA2_S1PAR (STM32_DMA2_BASE+STM32_DMA_S1PAR_OFFSET) +#define STM32_DMA2_S2PAR (STM32_DMA2_BASE+STM32_DMA_S2PAR_OFFSET) +#define STM32_DMA2_S3PAR (STM32_DMA2_BASE+STM32_DMA_S3PAR_OFFSET) +#define STM32_DMA2_S4PAR (STM32_DMA2_BASE+STM32_DMA_S4PAR_OFFSET) +#define STM32_DMA2_S5PAR (STM32_DMA2_BASE+STM32_DMA_S5PAR_OFFSET) +#define STM32_DMA2_S6PAR (STM32_DMA2_BASE+STM32_DMA_S6PAR_OFFSET) +#define STM32_DMA2_S7PAR (STM32_DMA2_BASE+STM32_DMA_S7PAR_OFFSET) + +#define STM32_DMA2_SM0AR(n) (STM32_DMA2_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0M0AR (STM32_DMA2_BASE+STM32_DMA_S0M0AR_OFFSET) +#define STM32_DMA2_S1M0AR (STM32_DMA2_BASE+STM32_DMA_S1M0AR_OFFSET) +#define STM32_DMA2_S2M0AR (STM32_DMA2_BASE+STM32_DMA_S2M0AR_OFFSET) +#define STM32_DMA2_S3M0AR (STM32_DMA2_BASE+STM32_DMA_S3M0AR_OFFSET) +#define STM32_DMA2_S4M0AR (STM32_DMA2_BASE+STM32_DMA_S4M0AR_OFFSET) +#define STM32_DMA2_S5M0AR (STM32_DMA2_BASE+STM32_DMA_S5M0AR_OFFSET) +#define STM32_DMA2_S6M0AR (STM32_DMA2_BASE+STM32_DMA_S6M0AR_OFFSET) +#define STM32_DMA2_S7M0AR (STM32_DMA2_BASE+STM32_DMA_S7M0AR_OFFSET) + +#define STM32_DMA2_SM1AR(n) (STM32_DMA2_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0M1AR (STM32_DMA2_BASE+STM32_DMA_S0M1AR_OFFSET) +#define STM32_DMA2_S1M1AR (STM32_DMA2_BASE+STM32_DMA_S1M1AR_OFFSET) +#define STM32_DMA2_S2M1AR (STM32_DMA2_BASE+STM32_DMA_S2M1AR_OFFSET) +#define STM32_DMA2_S3M1AR (STM32_DMA2_BASE+STM32_DMA_S3M1AR_OFFSET) +#define STM32_DMA2_S4M1AR (STM32_DMA2_BASE+STM32_DMA_S4M1AR_OFFSET) +#define STM32_DMA2_S5M1AR (STM32_DMA2_BASE+STM32_DMA_S5M1AR_OFFSET) +#define STM32_DMA2_S6M1AR (STM32_DMA2_BASE+STM32_DMA_S6M1AR_OFFSET) +#define STM32_DMA2_S7M1AR (STM32_DMA2_BASE+STM32_DMA_S7M1AR_OFFSET) + +#define STM32_DMA2_SFCR(n) (STM32_DMA2_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0FCR (STM32_DMA2_BASE+STM32_DMA_S0FCR_OFFSET) +#define STM32_DMA2_S1FCR (STM32_DMA2_BASE+STM32_DMA_S1FCR_OFFSET) +#define STM32_DMA2_S2FCR (STM32_DMA2_BASE+STM32_DMA_S2FCR_OFFSET) +#define STM32_DMA2_S3FCR (STM32_DMA2_BASE+STM32_DMA_S3FCR_OFFSET) +#define STM32_DMA2_S4FCR (STM32_DMA2_BASE+STM32_DMA_S4FCR_OFFSET) +#define STM32_DMA2_S5FCR (STM32_DMA2_BASE+STM32_DMA_S5FCR_OFFSET) +#define STM32_DMA2_S6FCR (STM32_DMA2_BASE+STM32_DMA_S6FCR_OFFSET) +#define STM32_DMA2_S7FCR (STM32_DMA2_BASE+STM32_DMA_S7FCR_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +#define DMA_STREAM_MASK 0x3f +#define DMA_STREAM_FEIF_BIT (1 << 0) /* Bit 0: Stream FIFO error interrupt flag */ +#define DMA_STREAM_DMEIF_BIT (1 << 2) /* Bit 2: Stream direct mode error interrupt flag */ +#define DMA_STREAM_TEIF_BIT (1 << 3) /* Bit 3: Stream Transfer Error flag */ +#define DMA_STREAM_HTIF_BIT (1 << 4) /* Bit 4: Stream Half Transfer flag */ +#define DMA_STREAM_TCIF_BIT (1 << 5) /* Bit 5: Stream Transfer Complete flag */ + +/* DMA interrupt status register and interrupt flag clear register field definitions */ + +#define DMA_INT_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt */ +#define DMA_INT_STREAM0_MASK (DMA_STREAM_MASK << DMA_INT_STREAM0_SHIFT) +#define DMA_INT_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt */ +#define DMA_INT_STREAM1_MASK (DMA_STREAM_MASK << DMA_INT_STREAM1_SHIFT) +#define DMA_INT_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt */ +#define DMA_INT_STREAM2_MASK (DMA_STREAM_MASK << DMA_INT_STREAM2_SHIFT) +#define DMA_INT_STREAM3_SHIFT (22) /* Bits 22-27: DMA Stream 3 interrupt */ +#define DMA_INT_STREAM3_MASK (DMA_STREAM_MASK << DMA_INT_STREAM3_SHIFT) + +#define DMA_INT_STREAM4_SHIFT (0) /* Bits 0-5: DMA Stream 4 interrupt */ +#define DMA_INT_STREAM4_MASK (DMA_STREAM_MASK << DMA_INT_STREAM4_SHIFT) +#define DMA_INT_STREAM5_SHIFT (6) /* Bits 6-11: DMA Stream 5 interrupt */ +#define DMA_INT_STREAM5_MASK (DMA_STREAM_MASK << DMA_INT_STREAM5_SHIFT) +#define DMA_INT_STREAM6_SHIFT (16) /* Bits 16-21: DMA Stream 6 interrupt */ +#define DMA_INT_STREAM6_MASK (DMA_STREAM_MASK << DMA_INT_STREAM6_SHIFT) +#define DMA_INT_STREAM7_SHIFT (22) /* Bits 22-27: DMA Stream 7 interrupt */ +#define DMA_INT_STREAM7_MASK (DMA_STREAM_MASK << DMA_INT_STREAM7_SHIFT) + +/* DMA stream configuration register */ + +#define DMA_SCR_EN (1 << 0) /* Bit 0: Stream enable */ +#define DMA_SCR_DMEIE (1 << 1) /* Bit 1: Direct mode error interrupt enable */ +#define DMA_SCR_TEIE (1 << 2) /* Bit 2: Transfer error interrupt enable */ +#define DMA_SCR_HTIE (1 << 3) /* Bit 3: Half Transfer interrupt enable */ +#define DMA_SCR_TCIE (1 << 4) /* Bit 4: Transfer complete interrupt enable */ +#define DMA_SCR_PFCTRL (1 << 5) /* Bit 5: Peripheral flow controller */ +#define DMA_SCR_DIR_SHIFT (6) /* Bits 6-7: Data transfer direction */ +#define DMA_SCR_DIR_MASK (3 << DMA_SCR_DIR_SHIFT) +# define DMA_SCR_DIR_P2M (0 << DMA_SCR_DIR_SHIFT) /* 00: Peripheral-to-memory */ +# define DMA_SCR_DIR_M2P (1 << DMA_SCR_DIR_SHIFT) /* 01: Memory-to-peripheral */ +# define DMA_SCR_DIR_M2M (2 << DMA_SCR_DIR_SHIFT) /* 10: Memory-to-memory */ +#define DMA_SCR_CIRC (1 << 8) /* Bit 8: Circular mode */ +#define DMA_SCR_PINC (1 << 9) /* Bit 9: Peripheral increment mode */ +#define DMA_SCR_MINC (1 << 10) /* Bit 10: Memory increment mode */ +#define DMA_SCR_PSIZE_SHIFT (11) /* Bits 11-12: Peripheral size */ +#define DMA_SCR_PSIZE_MASK (3 << DMA_SCR_PSIZE_SHIFT) +# define DMA_SCR_PSIZE_8BITS (0 << DMA_SCR_PSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_SCR_PSIZE_16BITS (1 << DMA_SCR_PSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_SCR_PSIZE_32BITS (2 << DMA_SCR_PSIZE_SHIFT) /* 10: 32-bits */ +#define DMA_SCR_MSIZE_SHIFT (13) /* Bits 13-14: Memory size */ +#define DMA_SCR_MSIZE_MASK (3 << DMA_SCR_MSIZE_SHIFT) +# define DMA_SCR_MSIZE_8BITS (0 << DMA_SCR_MSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_SCR_MSIZE_16BITS (1 << DMA_SCR_MSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_SCR_MSIZE_32BITS (2 << DMA_SCR_MSIZE_SHIFT) /* 10: 32-bits */ +#define DMA_SCR_PINCOS (1 << 15) /* Bit 15: Peripheral increment offset size */ +#define DMA_SCR_PL_SHIFT (16) /* Bits 16-17: Stream Priority level */ +#define DMA_SCR_PL_MASK (3 << DMA_SCR_PL_SHIFT) +# define DMA_SCR_PRILO (0 << DMA_SCR_PL_SHIFT) /* 00: Low */ +# define DMA_SCR_PRIMED (1 << DMA_SCR_PL_SHIFT) /* 01: Medium */ +# define DMA_SCR_PRIHI (2 << DMA_SCR_PL_SHIFT) /* 10: High */ +# define DMA_SCR_PRIVERYHI (3 << DMA_SCR_PL_SHIFT) /* 11: Very high */ +#define DMA_SCR_DBM (1 << 18) /* Bit 15: Double buffer mode */ +#define DMA_SCR_CT (1 << 19) /* Bit 19: Current target */ + /* Bit 20: Reserved */ +#define DMA_SCR_PBURST_SHIFT (21) /* Bits 21-22: Peripheral burst transfer configuration */ +#define DMA_SCR_PBURST_MASK (3 << DMA_SCR_PBURST_SHIFT) +# define DMA_SCR_PBURST_SINGLE (0 << DMA_SCR_PBURST_SHIFT) /* 00: Single transfer */ +# define DMA_SCR_PBURST_INCR4 (1 << DMA_SCR_PBURST_SHIFT) /* 01: Incremental burst of 4 beats */ +# define DMA_SCR_PBURST_INCR8 (2 << DMA_SCR_PBURST_SHIFT) /* 10: Incremental burst of 8 beats */ +# define DMA_SCR_PBURST_INCR16 (3 << DMA_SCR_PBURST_SHIFT) /* 11: Incremental burst of 16 beats */ +#define DMA_SCR_MBURST_SHIFT (23) /* Bits 23-24: Memory burst transfer configuration */ +#define DMA_SCR_MBURST_MASK (3 << DMA_SCR_MBURST_SHIFT) +# define DMA_SCR_MBURST_SINGLE (0 << DMA_SCR_MBURST_SHIFT) /* 00: Single transfer */ +# define DMA_SCR_MBURST_INCR4 (1 << DMA_SCR_MBURST_SHIFT) /* 01: Incremental burst of 4 beats */ +# define DMA_SCR_MBURST_INCR8 (2 << DMA_SCR_MBURST_SHIFT) /* 10: Incremental burst of 8 beats */ +# define DMA_SCR_MBURST_INCR16 (3 << DMA_SCR_MBURST_SHIFT) /* 11: Incremental burst of 16 beats */ + /* Bits 25-31: Reserved */ + +#define DMA_SCR_ALLINTS (DMA_SCR_DMEIE|DMA_SCR_TEIE|DMA_SCR_HTIE|DMA_SCR_TCIE) + +/* DMA stream number of data register */ + +#define DMA_SNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */ +#define DMA_SNDTR_NDT_MASK (0xffff << DMA_SNDTR_NDT_SHIFT) + +/* DMA stream n FIFO control register */ + +#define DMA_SFCR_FTH_SHIFT (0) /* Bits 0-1: FIFO threshold selection */ +#define DMA_SFCR_FTH_MASK (3 << DMA_SFCR_FTH_SHIFT) +# define DMA_SFCR_FTH_QUARTER (0 << DMA_SFCR_FTH_SHIFT) /* 1/4 full FIFO */ +# define DMA_SFCR_FTH_HALF (1 << DMA_SFCR_FTH_SHIFT) /* 1/2 full FIFO */ +# define DMA_SFCR_FTH_3QUARTER (2 << DMA_SFCR_FTH_SHIFT) /* 3/4 full FIFO */ +# define DMA_SFCR_FTH_FULL (3 << DMA_SFCR_FTH_SHIFT) /* full FIFO */ +#define DMA_SFCR_DMDIS (1 << 2) /* Bit 2: Direct mode disable */ +#define DMA_SFCR_FS_SHIFT (3) /* Bits 3-5: FIFO status */ +#define DMA_SFCR_FS_MASK (7 << DMA_SFCR_FS_SHIFT) +# define DMA_SFCR_FS_QUARTER (0 << DMA_SFCR_FS_SHIFT) /* 0 < fifo_level < 1/4 */ +# define DMA_SFCR_FS_HALF (1 << DMA_SFCR_FS_SHIFT) /* 1/4 = fifo_level < 1/2 */ +# define DMA_SFCR_FS_3QUARTER (2 << DMA_SFCR_FS_SHIFT) /* 1/2 = fifo_level < 3/4 */ +# define DMA_SFCR_FS_ALMOSTFULL (3 << DMA_SFCR_FS_SHIFT) /* 3/4 = fifo_level < full */ +# define DMA_SFCR_FS_EMPTY (4 << DMA_SFCR_FS_SHIFT) /* FIFO is empty */ +# define DMA_SFCR_FS_FULL (5 << DMA_SFCR_FS_SHIFT) /* FIFO is full */ + /* Bit 6: Reserved */ +#define DMA_SFCR_FEIE (1 << 7) /* Bit 7: FIFO error interrupt enable */ + /* Bits 8-31: Reserved */ + +/* MDMA ******************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_MDMA_GISR0_OFFSET 0x0000 /* MDMA global interrupt/status register */ + /* 0x0004-0x003C: Reserved */ +#define STM32_MDMA_CXISR_OFFSET(x) (0x0040+0x040*(x)) /* MDMA channel x interrupt/status register*/ +#define STM32_MDMA_C0ISR_OFFSET STM32_MDMA_CXISR_OFFSET(0) +#define STM32_MDMA_C1ISR_OFFSET STM32_MDMA_CXISR_OFFSET(1) +#define STM32_MDMA_C2ISR_OFFSET STM32_MDMA_CXISR_OFFSET(2) +#define STM32_MDMA_C3ISR_OFFSET STM32_MDMA_CXISR_OFFSET(3) +#define STM32_MDMA_C4ISR_OFFSET STM32_MDMA_CXISR_OFFSET(4) +#define STM32_MDMA_C5ISR_OFFSET STM32_MDMA_CXISR_OFFSET(5) +#define STM32_MDMA_C6ISR_OFFSET STM32_MDMA_CXISR_OFFSET(6) +#define STM32_MDMA_C7ISR_OFFSET STM32_MDMA_CXISR_OFFSET(7) +#define STM32_MDMA_C8ISR_OFFSET STM32_MDMA_CXISR_OFFSET(8) +#define STM32_MDMA_C9ISR_OFFSET STM32_MDMA_CXISR_OFFSET(9) +#define STM32_MDMA_C10ISR_OFFSET STM32_MDMA_CXISR_OFFSET(10) +#define STM32_MDMA_C11ISR_OFFSET STM32_MDMA_CXISR_OFFSET(11) +#define STM32_MDMA_C12ISR_OFFSET STM32_MDMA_CXISR_OFFSET(12) +#define STM32_MDMA_C13ISR_OFFSET STM32_MDMA_CXISR_OFFSET(13) +#define STM32_MDMA_C14ISR_OFFSET STM32_MDMA_CXISR_OFFSET(14) +#define STM32_MDMA_C15ISR_OFFSET STM32_MDMA_CXISR_OFFSET(15) + +#define STM32_MDMA_CXIFCR_OFFSET(x) (0x0044+0x040*(x)) /* MDMA channel x interrupt flag clear register */ +#define STM32_MDMA_C0IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(0) +#define STM32_MDMA_C1IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(1) +#define STM32_MDMA_C2IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(2) +#define STM32_MDMA_C3IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(3) +#define STM32_MDMA_C4IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(4) +#define STM32_MDMA_C5IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(5) +#define STM32_MDMA_C6IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(6) +#define STM32_MDMA_C7IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(7) +#define STM32_MDMA_C8IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(8) +#define STM32_MDMA_C9IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(9) +#define STM32_MDMA_C10IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(10) +#define STM32_MDMA_C11IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(11) +#define STM32_MDMA_C12IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(12) +#define STM32_MDMA_C13IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(13) +#define STM32_MDMA_C14IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(14) +#define STM32_MDMA_C15IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(15) + +#define STM32_MDMA_CXESR_OFFSET(x) (0x0048+0x040*(x)) /* MDMA channel x error status register */ +#define STM32_MDMA_C0ESR_OFFSET STM32_MDMA_CXESR_OFFSET0) +#define STM32_MDMA_C1ESR_OFFSET STM32_MDMA_CXESR_OFFSET1) +#define STM32_MDMA_C2ESR_OFFSET STM32_MDMA_CXESR_OFFSET2) +#define STM32_MDMA_C3ESR_OFFSET STM32_MDMA_CXESR_OFFSET3) +#define STM32_MDMA_C4ESR_OFFSET STM32_MDMA_CXESR_OFFSET4) +#define STM32_MDMA_C5ESR_OFFSET STM32_MDMA_CXESR_OFFSET5) +#define STM32_MDMA_C6ESR_OFFSET STM32_MDMA_CXESR_OFFSET6) +#define STM32_MDMA_C7ESR_OFFSET STM32_MDMA_CXESR_OFFSET7) +#define STM32_MDMA_C8ESR_OFFSET STM32_MDMA_CXESR_OFFSET8) +#define STM32_MDMA_C9ESR_OFFSET STM32_MDMA_CXESR_OFFSET9) +#define STM32_MDMA_C10ESR_OFFSET STM32_MDMA_CXESR_OFFSET10) +#define STM32_MDMA_C11ESR_OFFSET STM32_MDMA_CXESR_OFFSET11) +#define STM32_MDMA_C12ESR_OFFSET STM32_MDMA_CXESR_OFFSET12) +#define STM32_MDMA_C13ESR_OFFSET STM32_MDMA_CXESR_OFFSET13) +#define STM32_MDMA_C14ESR_OFFSET STM32_MDMA_CXESR_OFFSET14) +#define STM32_MDMA_C15ESR_OFFSET STM32_MDMA_CXESR_OFFSET15) + +#define STM32_MDMA_CXCR_OFFSET(x) (0x004C+0x040*(x)) /* MDMA channel x control register */ +#define STM32_MDMA_C0CR_OFFSET STM32_MDMA_CXCR_OFFSET(0) +#define STM32_MDMA_C1CR_OFFSET STM32_MDMA_CXCR_OFFSET(1) +#define STM32_MDMA_C2CR_OFFSET STM32_MDMA_CXCR_OFFSET(2) +#define STM32_MDMA_C3CR_OFFSET STM32_MDMA_CXCR_OFFSET(3) +#define STM32_MDMA_C4CR_OFFSET STM32_MDMA_CXCR_OFFSET(4) +#define STM32_MDMA_C5CR_OFFSET STM32_MDMA_CXCR_OFFSET(5) +#define STM32_MDMA_C6CR_OFFSET STM32_MDMA_CXCR_OFFSET(6) +#define STM32_MDMA_C7CR_OFFSET STM32_MDMA_CXCR_OFFSET(7) +#define STM32_MDMA_C8CR_OFFSET STM32_MDMA_CXCR_OFFSET(8) +#define STM32_MDMA_C9CR_OFFSET STM32_MDMA_CXCR_OFFSET(9) +#define STM32_MDMA_C10CR_OFFSET STM32_MDMA_CXCR_OFFSET(10) +#define STM32_MDMA_C11CR_OFFSET STM32_MDMA_CXCR_OFFSET(11) +#define STM32_MDMA_C12CR_OFFSET STM32_MDMA_CXCR_OFFSET(12) +#define STM32_MDMA_C13CR_OFFSET STM32_MDMA_CXCR_OFFSET(13) +#define STM32_MDMA_C14CR_OFFSET STM32_MDMA_CXCR_OFFSET(14) +#define STM32_MDMA_C15CR_OFFSET STM32_MDMA_CXCR_OFFSET(15) + +#define STM32_MDMA_CXTCR_OFFSET(x) (0x0050+0x040*(x)) /* MDMA channel x control register */ +#define STM32_MDMA_C0TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(0) +#define STM32_MDMA_C1TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(1) +#define STM32_MDMA_C2TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(2) +#define STM32_MDMA_C3TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(3) +#define STM32_MDMA_C4TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(4) +#define STM32_MDMA_C5TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(5) +#define STM32_MDMA_C6TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(6) +#define STM32_MDMA_C7TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(7) +#define STM32_MDMA_C8TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(8) +#define STM32_MDMA_C9TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(9) +#define STM32_MDMA_C10TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(10) +#define STM32_MDMA_C11TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(11) +#define STM32_MDMA_C12TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(12) +#define STM32_MDMA_C13TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(13) +#define STM32_MDMA_C14TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(14) +#define STM32_MDMA_C15TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(15) + +#define STM32_MDMA_CXBNDTR_OFFSET(x) (0x0054+0x040*(x)) /* MDMA channel x block number of data register */ +#define STM32_MDMA_C0BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(0) +#define STM32_MDMA_C1BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(1) +#define STM32_MDMA_C2BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(2) +#define STM32_MDMA_C3BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(3) +#define STM32_MDMA_C4BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(4) +#define STM32_MDMA_C5BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(5) +#define STM32_MDMA_C6BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(6) +#define STM32_MDMA_C7BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(7) +#define STM32_MDMA_C8BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(8) +#define STM32_MDMA_C9BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(9) +#define STM32_MDMA_C10BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(10) +#define STM32_MDMA_C11BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(11) +#define STM32_MDMA_C12BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(12) +#define STM32_MDMA_C13BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(13) +#define STM32_MDMA_C14BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(14) +#define STM32_MDMA_C15BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(15) + +#define STM32_MDMA_CXSAR_OFFSET(x) (0x0058+0x040*(x)) /* MDMA channel x source address register */ +#define STM32_MDMA_C0SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(0) +#define STM32_MDMA_C1SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(1) +#define STM32_MDMA_C2SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(2) +#define STM32_MDMA_C3SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(3) +#define STM32_MDMA_C4SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(4) +#define STM32_MDMA_C5SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(5) +#define STM32_MDMA_C6SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(6) +#define STM32_MDMA_C7SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(7) +#define STM32_MDMA_C8SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(8) +#define STM32_MDMA_C9SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(9) +#define STM32_MDMA_C10SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(10) +#define STM32_MDMA_C11SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(11) +#define STM32_MDMA_C12SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(12) +#define STM32_MDMA_C13SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(13) +#define STM32_MDMA_C14SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(14) +#define STM32_MDMA_C15SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(15) + +#define STM32_MDMA_CXDAR_OFFSET(x) (0x005C+0x040*(x)) /* MDMA channel x destination address register */ +#define STM32_MDMA_C0DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(0) +#define STM32_MDMA_C1DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(1) +#define STM32_MDMA_C2DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(2) +#define STM32_MDMA_C3DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(3) +#define STM32_MDMA_C4DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(4) +#define STM32_MDMA_C5DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(5) +#define STM32_MDMA_C6DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(6) +#define STM32_MDMA_C7DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(7) +#define STM32_MDMA_C8DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(8) +#define STM32_MDMA_C9DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(9) +#define STM32_MDMA_C10DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(10) +#define STM32_MDMA_C11DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(11) +#define STM32_MDMA_C12DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(12) +#define STM32_MDMA_C13DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(13) +#define STM32_MDMA_C14DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(14) +#define STM32_MDMA_C15DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(15) + +#define STM32_MDMA_CXBRUR_OFFSET(x) (0x0060+0x040*(x)) /* MDMA channel x block repeat address update register */ +#define STM32_MDMA_C0BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(0) +#define STM32_MDMA_C1BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(1) +#define STM32_MDMA_C2BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(2) +#define STM32_MDMA_C3BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(3) +#define STM32_MDMA_C4BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(4) +#define STM32_MDMA_C5BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(5) +#define STM32_MDMA_C6BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(6) +#define STM32_MDMA_C7BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(7) +#define STM32_MDMA_C8BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(8) +#define STM32_MDMA_C9BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(9) +#define STM32_MDMA_C10BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(10) +#define STM32_MDMA_C11BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(11) +#define STM32_MDMA_C12BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(12) +#define STM32_MDMA_C13BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(13) +#define STM32_MDMA_C14BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(14) +#define STM32_MDMA_C15BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(15) + +#define STM32_MDMA_CXLAR_OFFSET(x) (0x0064+0x040*(x)) /* MDMA channel x link address register */ +#define STM32_MDMA_C0LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(0) +#define STM32_MDMA_C1LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(1) +#define STM32_MDMA_C2LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(2) +#define STM32_MDMA_C3LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(3) +#define STM32_MDMA_C4LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(4) +#define STM32_MDMA_C5LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(5) +#define STM32_MDMA_C6LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(6) +#define STM32_MDMA_C7LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(7) +#define STM32_MDMA_C8LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(8) +#define STM32_MDMA_C9LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(9) +#define STM32_MDMA_C10LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(10) +#define STM32_MDMA_C11LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(11) +#define STM32_MDMA_C12LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(12) +#define STM32_MDMA_C13LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(13) +#define STM32_MDMA_C14LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(14) +#define STM32_MDMA_C15LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(15) + +#define STM32_MDMA_CXTBR_OFFSET(x) (0x0064+0x040*(x)) /* MDMA channel x trigger and bus selection register */ +#define STM32_MDMA_C0TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(0) +#define STM32_MDMA_C1TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(1) +#define STM32_MDMA_C2TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(2) +#define STM32_MDMA_C3TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(3) +#define STM32_MDMA_C4TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(4) +#define STM32_MDMA_C5TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(5) +#define STM32_MDMA_C6TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(6) +#define STM32_MDMA_C7TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(7) +#define STM32_MDMA_C8TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(8) +#define STM32_MDMA_C9TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(9) +#define STM32_MDMA_C10TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(10) +#define STM32_MDMA_C11TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(11) +#define STM32_MDMA_C12TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(12) +#define STM32_MDMA_C13TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(13) +#define STM32_MDMA_C14TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(14) +#define STM32_MDMA_C15TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(15) + +#define STM32_MDMA_CXMAR_OFFSET(x) (0x0068+0x040*(x)) /* MDMA channel x mask address register */ +#define STM32_MDMA_C0MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(0) +#define STM32_MDMA_C1MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(1) +#define STM32_MDMA_C2MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(2) +#define STM32_MDMA_C3MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(3) +#define STM32_MDMA_C4MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(4) +#define STM32_MDMA_C5MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(5) +#define STM32_MDMA_C6MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(6) +#define STM32_MDMA_C7MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(7) +#define STM32_MDMA_C8MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(8) +#define STM32_MDMA_C9MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(9) +#define STM32_MDMA_C10MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(10) +#define STM32_MDMA_C11MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(11) +#define STM32_MDMA_C12MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(12) +#define STM32_MDMA_C13MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(13) +#define STM32_MDMA_C14MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(14) +#define STM32_MDMA_C15MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(15) + +#define STM32_MDMA_CXMDR_OFFSET(x) (0x0070+0x040*(x)) /* MDMA channel x mask data register */ +#define STM32_MDMA_C0MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(0) +#define STM32_MDMA_C1MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(1) +#define STM32_MDMA_C2MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(2) +#define STM32_MDMA_C3MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(3) +#define STM32_MDMA_C4MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(4) +#define STM32_MDMA_C5MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(5) +#define STM32_MDMA_C6MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(6) +#define STM32_MDMA_C7MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(7) +#define STM32_MDMA_C8MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(8) +#define STM32_MDMA_C9MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(9) +#define STM32_MDMA_C10MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(10) +#define STM32_MDMA_C11MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(11) +#define STM32_MDMA_C12MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(12) +#define STM32_MDMA_C13MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(13) +#define STM32_MDMA_C14MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(14) +#define STM32_MDMA_C15MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(15) + +/* Register Addresses ***************************************************************/ + +#define STM32_MDMA_GISR0 (STM32_MDMA_BASE+STM32_MDMA_GISR0_OFFSET) + +#define STM32_MDMA_CXISR(x) (STM32_MDMA_BASE+STM32_MDMA_CXISR_OFFSET(x)) +#define STM32_MDMA_C0ISR (STM32_MDMA_BASE+STM32_MDMA_C0ISR_OFFSET) +#define STM32_MDMA_C1ISR (STM32_MDMA_BASE+STM32_MDMA_C1ISR_OFFSET) +#define STM32_MDMA_C2ISR (STM32_MDMA_BASE+STM32_MDMA_C2ISR_OFFSET) +#define STM32_MDMA_C3ISR (STM32_MDMA_BASE+STM32_MDMA_C3ISR_OFFSET) +#define STM32_MDMA_C4ISR (STM32_MDMA_BASE+STM32_MDMA_C4ISR_OFFSET) +#define STM32_MDMA_C5ISR (STM32_MDMA_BASE+STM32_MDMA_C5ISR_OFFSET) +#define STM32_MDMA_C6ISR (STM32_MDMA_BASE+STM32_MDMA_C6ISR_OFFSET) +#define STM32_MDMA_C7ISR (STM32_MDMA_BASE+STM32_MDMA_C7ISR_OFFSET) +#define STM32_MDMA_C8ISR (STM32_MDMA_BASE+STM32_MDMA_C8ISR_OFFSET) +#define STM32_MDMA_C9ISR (STM32_MDMA_BASE+STM32_MDMA_C9ISR_OFFSET) +#define STM32_MDMA_C10ISR (STM32_MDMA_BASE+STM32_MDMA_C10ISR_OFFSET) +#define STM32_MDMA_C11ISR (STM32_MDMA_BASE+STM32_MDMA_C11ISR_OFFSET) +#define STM32_MDMA_C12ISR (STM32_MDMA_BASE+STM32_MDMA_C12ISR_OFFSET) +#define STM32_MDMA_C13ISR (STM32_MDMA_BASE+STM32_MDMA_C13ISR_OFFSET) +#define STM32_MDMA_C14ISR (STM32_MDMA_BASE+STM32_MDMA_C14ISR_OFFSET) +#define STM32_MDMA_C15ISR (STM32_MDMA_BASE+STM32_MDMA_C15ISR_OFFSET) + +#define STM32_MDMA_CXIFCR(x) (STM32_MDMA_BASE+STM32_MDMA_CXIFCR_OFFSET(x)) +#define STM32_MDMA_C0IFCR (STM32_MDMA_BASE+STM32_MDMA_C0IFCR_OFFSET) +#define STM32_MDMA_C1IFCR (STM32_MDMA_BASE+STM32_MDMA_C1IFCR_OFFSET) +#define STM32_MDMA_C2IFCR (STM32_MDMA_BASE+STM32_MDMA_C2IFCR_OFFSET) +#define STM32_MDMA_C3IFCR (STM32_MDMA_BASE+STM32_MDMA_C3IFCR_OFFSET) +#define STM32_MDMA_C4IFCR (STM32_MDMA_BASE+STM32_MDMA_C4IFCR_OFFSET) +#define STM32_MDMA_C5IFCR (STM32_MDMA_BASE+STM32_MDMA_C5IFCR_OFFSET) +#define STM32_MDMA_C6IFCR (STM32_MDMA_BASE+STM32_MDMA_C6IFCR_OFFSET) +#define STM32_MDMA_C7IFCR (STM32_MDMA_BASE+STM32_MDMA_C7IFCR_OFFSET) +#define STM32_MDMA_C8IFCR (STM32_MDMA_BASE+STM32_MDMA_C8IFCR_OFFSET) +#define STM32_MDMA_C9IFCR (STM32_MDMA_BASE+STM32_MDMA_C9IFCR_OFFSET) +#define STM32_MDMA_C10IFCR (STM32_MDMA_BASE+STM32_MDMA_C10IFCR_OFFSET) +#define STM32_MDMA_C11IFCR (STM32_MDMA_BASE+STM32_MDMA_C11IFCR_OFFSET) +#define STM32_MDMA_C12IFCR (STM32_MDMA_BASE+STM32_MDMA_C12IFCR_OFFSET) +#define STM32_MDMA_C13IFCR (STM32_MDMA_BASE+STM32_MDMA_C13IFCR_OFFSET) +#define STM32_MDMA_C14IFCR (STM32_MDMA_BASE+STM32_MDMA_C14IFCR_OFFSET) +#define STM32_MDMA_C15IFCR (STM32_MDMA_BASE+STM32_MDMA_C15IFCR_OFFSET) + +#define STM32_MDMA_CXESR(x) (STM32_MDMA_BASE+STM32_MDMA_CXESR_OFFSET(x)) +#define STM32_MDMA_C0ESR (STM32_MDMA_BASE+STM32_MDMA_C0ESR_OFFSET) +#define STM32_MDMA_C1ESR (STM32_MDMA_BASE+STM32_MDMA_C1ESR_OFFSET) +#define STM32_MDMA_C2ESR (STM32_MDMA_BASE+STM32_MDMA_C2ESR_OFFSET) +#define STM32_MDMA_C3ESR (STM32_MDMA_BASE+STM32_MDMA_C3ESR_OFFSET) +#define STM32_MDMA_C4ESR (STM32_MDMA_BASE+STM32_MDMA_C4ESR_OFFSET) +#define STM32_MDMA_C5ESR (STM32_MDMA_BASE+STM32_MDMA_C5ESR_OFFSET) +#define STM32_MDMA_C6ESR (STM32_MDMA_BASE+STM32_MDMA_C6ESR_OFFSET) +#define STM32_MDMA_C7ESR (STM32_MDMA_BASE+STM32_MDMA_C7ESR_OFFSET) +#define STM32_MDMA_C8ESR (STM32_MDMA_BASE+STM32_MDMA_C8ESR_OFFSET) +#define STM32_MDMA_C9ESR (STM32_MDMA_BASE+STM32_MDMA_C9ESR_OFFSET) +#define STM32_MDMA_C10ESR (STM32_MDMA_BASE+STM32_MDMA_C10ESR_OFFSET) +#define STM32_MDMA_C11ESR (STM32_MDMA_BASE+STM32_MDMA_C11ESR_OFFSET) +#define STM32_MDMA_C12ESR (STM32_MDMA_BASE+STM32_MDMA_C12ESR_OFFSET) +#define STM32_MDMA_C13ESR (STM32_MDMA_BASE+STM32_MDMA_C13ESR_OFFSET) +#define STM32_MDMA_C14ESR (STM32_MDMA_BASE+STM32_MDMA_C14ESR_OFFSET) +#define STM32_MDMA_C15ESR (STM32_MDMA_BASE+STM32_MDMA_C15ESR_OFFSET) + +#define STM32_MDMA_CXCR(x) (STM32_MDMA_BASE+STM32_MDMA_CXCR_OFFSET(x)) +#define STM32_MDMA_C0CR (STM32_MDMA_BASE+STM32_MDMA_C0CR_OFFSET) +#define STM32_MDMA_C1CR (STM32_MDMA_BASE+STM32_MDMA_C1CR_OFFSET) +#define STM32_MDMA_C2CR (STM32_MDMA_BASE+STM32_MDMA_C2CR_OFFSET) +#define STM32_MDMA_C3CR (STM32_MDMA_BASE+STM32_MDMA_C3CR_OFFSET) +#define STM32_MDMA_C4CR (STM32_MDMA_BASE+STM32_MDMA_C4CR_OFFSET) +#define STM32_MDMA_C5CR (STM32_MDMA_BASE+STM32_MDMA_C5CR_OFFSET) +#define STM32_MDMA_C6CR (STM32_MDMA_BASE+STM32_MDMA_C6CR_OFFSET) +#define STM32_MDMA_C7CR (STM32_MDMA_BASE+STM32_MDMA_C7CR_OFFSET) +#define STM32_MDMA_C8CR (STM32_MDMA_BASE+STM32_MDMA_C8CR_OFFSET) +#define STM32_MDMA_C9CR (STM32_MDMA_BASE+STM32_MDMA_C9CR_OFFSET) +#define STM32_MDMA_C10CR (STM32_MDMA_BASE+STM32_MDMA_C10CR_OFFSET) +#define STM32_MDMA_C11CR (STM32_MDMA_BASE+STM32_MDMA_C11CR_OFFSET) +#define STM32_MDMA_C12CR (STM32_MDMA_BASE+STM32_MDMA_C12CR_OFFSET) +#define STM32_MDMA_C13CR (STM32_MDMA_BASE+STM32_MDMA_C13CR_OFFSET) +#define STM32_MDMA_C14CR (STM32_MDMA_BASE+STM32_MDMA_C14CR_OFFSET) +#define STM32_MDMA_C15CR (STM32_MDMA_BASE+STM32_MDMA_C15CR_OFFSET) + +#define STM32_MDMA_CXTCR(x) (STM32_MDMA_BASE+STM32_MDMA_CXTCR_OFFSET(x)) +#define STM32_MDMA_C0TCR (STM32_MDMA_BASE+STM32_MDMA_C0TCR_OFFSET) +#define STM32_MDMA_C1TCR (STM32_MDMA_BASE+STM32_MDMA_C1TCR_OFFSET) +#define STM32_MDMA_C2TCR (STM32_MDMA_BASE+STM32_MDMA_C2TCR_OFFSET) +#define STM32_MDMA_C3TCR (STM32_MDMA_BASE+STM32_MDMA_C3TCR_OFFSET) +#define STM32_MDMA_C4TCR (STM32_MDMA_BASE+STM32_MDMA_C4TCR_OFFSET) +#define STM32_MDMA_C5TCR (STM32_MDMA_BASE+STM32_MDMA_C5TCR_OFFSET) +#define STM32_MDMA_C6TCR (STM32_MDMA_BASE+STM32_MDMA_C6TCR_OFFSET) +#define STM32_MDMA_C7TCR (STM32_MDMA_BASE+STM32_MDMA_C7TCR_OFFSET) +#define STM32_MDMA_C8TCR (STM32_MDMA_BASE+STM32_MDMA_C8TCR_OFFSET) +#define STM32_MDMA_C9TCR (STM32_MDMA_BASE+STM32_MDMA_C9TCR_OFFSET) +#define STM32_MDMA_C10TCR (STM32_MDMA_BASE+STM32_MDMA_C10TCR_OFFSET) +#define STM32_MDMA_C11TCR (STM32_MDMA_BASE+STM32_MDMA_C11TCR_OFFSET) +#define STM32_MDMA_C12TCR (STM32_MDMA_BASE+STM32_MDMA_C12TCR_OFFSET) +#define STM32_MDMA_C13TCR (STM32_MDMA_BASE+STM32_MDMA_C13TCR_OFFSET) +#define STM32_MDMA_C14TCR (STM32_MDMA_BASE+STM32_MDMA_C14TCR_OFFSET) +#define STM32_MDMA_C15TCR (STM32_MDMA_BASE+STM32_MDMA_C15TCR_OFFSET) + +#define STM32_MDMA_CXBNDTR(x) (STM32_MDMA_BASE+STM32_MDMA_CXBNDTR_OFFSET(x)) +#define STM32_MDMA_C0BNDTR (STM32_MDMA_BASE+STM32_MDMA_C0BNDTR_OFFSET) +#define STM32_MDMA_C1BNDTR (STM32_MDMA_BASE+STM32_MDMA_C1BNDTR_OFFSET) +#define STM32_MDMA_C2BNDTR (STM32_MDMA_BASE+STM32_MDMA_C2BNDTR_OFFSET) +#define STM32_MDMA_C3BNDTR (STM32_MDMA_BASE+STM32_MDMA_C3BNDTR_OFFSET) +#define STM32_MDMA_C4BNDTR (STM32_MDMA_BASE+STM32_MDMA_C4BNDTR_OFFSET) +#define STM32_MDMA_C5BNDTR (STM32_MDMA_BASE+STM32_MDMA_C5BNDTR_OFFSET) +#define STM32_MDMA_C6BNDTR (STM32_MDMA_BASE+STM32_MDMA_C6BNDTR_OFFSET) +#define STM32_MDMA_C7BNDTR (STM32_MDMA_BASE+STM32_MDMA_C7BNDTR_OFFSET) +#define STM32_MDMA_C8BNDTR (STM32_MDMA_BASE+STM32_MDMA_C8BNDTR_OFFSET) +#define STM32_MDMA_C9BNDTR (STM32_MDMA_BASE+STM32_MDMA_C9BNDTR_OFFSET) +#define STM32_MDMA_C10BNDTR (STM32_MDMA_BASE+STM32_MDMA_C10BNDTR_OFFSET) +#define STM32_MDMA_C11BNDTR (STM32_MDMA_BASE+STM32_MDMA_C11BNDTR_OFFSET) +#define STM32_MDMA_C12BNDTR (STM32_MDMA_BASE+STM32_MDMA_C12BNDTR_OFFSET) +#define STM32_MDMA_C13BNDTR (STM32_MDMA_BASE+STM32_MDMA_C13BNDTR_OFFSET) +#define STM32_MDMA_C14BNDTR (STM32_MDMA_BASE+STM32_MDMA_C14BNDTR_OFFSET) +#define STM32_MDMA_C15BNDTR (STM32_MDMA_BASE+STM32_MDMA_C15BNDTR_OFFSET) + +#define STM32_MDMA_CXBRUR(x) (STM32_MDMA_BASE+STM32_MDMA_CXBRUR_OFFSET(x)) +#define STM32_MDMA_C0BRUR (STM32_MDMA_BASE+STM32_MDMA_C0BRUR_OFFSET) +#define STM32_MDMA_C1BRUR (STM32_MDMA_BASE+STM32_MDMA_C1BRUR_OFFSET) +#define STM32_MDMA_C2BRUR (STM32_MDMA_BASE+STM32_MDMA_C2BRUR_OFFSET) +#define STM32_MDMA_C3BRUR (STM32_MDMA_BASE+STM32_MDMA_C3BRUR_OFFSET) +#define STM32_MDMA_C4BRUR (STM32_MDMA_BASE+STM32_MDMA_C4BRUR_OFFSET) +#define STM32_MDMA_C5BRUR (STM32_MDMA_BASE+STM32_MDMA_C5BRUR_OFFSET) +#define STM32_MDMA_C6BRUR (STM32_MDMA_BASE+STM32_MDMA_C6BRUR_OFFSET) +#define STM32_MDMA_C7BRUR (STM32_MDMA_BASE+STM32_MDMA_C7BRUR_OFFSET) +#define STM32_MDMA_C8BRUR (STM32_MDMA_BASE+STM32_MDMA_C8BRUR_OFFSET) +#define STM32_MDMA_C9BRUR (STM32_MDMA_BASE+STM32_MDMA_C9BRUR_OFFSET) +#define STM32_MDMA_C10BRUR (STM32_MDMA_BASE+STM32_MDMA_C10BRUR_OFFSET) +#define STM32_MDMA_C11BRUR (STM32_MDMA_BASE+STM32_MDMA_C11BRUR_OFFSET) +#define STM32_MDMA_C12BRUR (STM32_MDMA_BASE+STM32_MDMA_C12BRUR_OFFSET) +#define STM32_MDMA_C13BRUR (STM32_MDMA_BASE+STM32_MDMA_C13BRUR_OFFSET) +#define STM32_MDMA_C14BRUR (STM32_MDMA_BASE+STM32_MDMA_C14BRUR_OFFSET) +#define STM32_MDMA_C15BRUR (STM32_MDMA_BASE+STM32_MDMA_C15BRUR_OFFSET) + +#define STM32_MDMA_CXLAR(x) (STM32_MDMA_BASE+STM32_MDMA_CXLAR_OFFSET(x)) +#define STM32_MDMA_C0LAR (STM32_MDMA_BASE+STM32_MDMA_C0LAR_OFFSET) +#define STM32_MDMA_C1LAR (STM32_MDMA_BASE+STM32_MDMA_C1LAR_OFFSET) +#define STM32_MDMA_C2LAR (STM32_MDMA_BASE+STM32_MDMA_C2LAR_OFFSET) +#define STM32_MDMA_C3LAR (STM32_MDMA_BASE+STM32_MDMA_C3LAR_OFFSET) +#define STM32_MDMA_C4LAR (STM32_MDMA_BASE+STM32_MDMA_C4LAR_OFFSET) +#define STM32_MDMA_C5LAR (STM32_MDMA_BASE+STM32_MDMA_C5LAR_OFFSET) +#define STM32_MDMA_C6LAR (STM32_MDMA_BASE+STM32_MDMA_C6LAR_OFFSET) +#define STM32_MDMA_C7LAR (STM32_MDMA_BASE+STM32_MDMA_C7LAR_OFFSET) +#define STM32_MDMA_C8LAR (STM32_MDMA_BASE+STM32_MDMA_C8LAR_OFFSET) +#define STM32_MDMA_C9LAR (STM32_MDMA_BASE+STM32_MDMA_C9LAR_OFFSET) +#define STM32_MDMA_C10LAR (STM32_MDMA_BASE+STM32_MDMA_C10LAR_OFFSET) +#define STM32_MDMA_C11LAR (STM32_MDMA_BASE+STM32_MDMA_C11LAR_OFFSET) +#define STM32_MDMA_C12LAR (STM32_MDMA_BASE+STM32_MDMA_C12LAR_OFFSET) +#define STM32_MDMA_C13LAR (STM32_MDMA_BASE+STM32_MDMA_C13LAR_OFFSET) +#define STM32_MDMA_C14LAR (STM32_MDMA_BASE+STM32_MDMA_C14LAR_OFFSET) +#define STM32_MDMA_C15LAR (STM32_MDMA_BASE+STM32_MDMA_C15LAR_OFFSET) + +#define STM32_MDMA_CXTBR(x) (STM32_MDMA_BASE+STM32_MDMA_CXTBR_OFFSET(x)) +#define STM32_MDMA_C0TBR (STM32_MDMA_BASE+STM32_MDMA_C0TBR_OFFSET) +#define STM32_MDMA_C1TBR (STM32_MDMA_BASE+STM32_MDMA_C1TBR_OFFSET) +#define STM32_MDMA_C2TBR (STM32_MDMA_BASE+STM32_MDMA_C2TBR_OFFSET) +#define STM32_MDMA_C3TBR (STM32_MDMA_BASE+STM32_MDMA_C3TBR_OFFSET) +#define STM32_MDMA_C4TBR (STM32_MDMA_BASE+STM32_MDMA_C4TBR_OFFSET) +#define STM32_MDMA_C5TBR (STM32_MDMA_BASE+STM32_MDMA_C5TBR_OFFSET) +#define STM32_MDMA_C6TBR (STM32_MDMA_BASE+STM32_MDMA_C6TBR_OFFSET) +#define STM32_MDMA_C7TBR (STM32_MDMA_BASE+STM32_MDMA_C7TBR_OFFSET) +#define STM32_MDMA_C8TBR (STM32_MDMA_BASE+STM32_MDMA_C8TBR_OFFSET) +#define STM32_MDMA_C9TBR (STM32_MDMA_BASE+STM32_MDMA_C9TBR_OFFSET) +#define STM32_MDMA_C10TBR (STM32_MDMA_BASE+STM32_MDMA_C10TBR_OFFSET) +#define STM32_MDMA_C11TBR (STM32_MDMA_BASE+STM32_MDMA_C11TBR_OFFSET) +#define STM32_MDMA_C12TBR (STM32_MDMA_BASE+STM32_MDMA_C12TBR_OFFSET) +#define STM32_MDMA_C13TBR (STM32_MDMA_BASE+STM32_MDMA_C13TBR_OFFSET) +#define STM32_MDMA_C14TBR (STM32_MDMA_BASE+STM32_MDMA_C14TBR_OFFSET) +#define STM32_MDMA_C15TBR (STM32_MDMA_BASE+STM32_MDMA_C15TBR_OFFSET) + +#define STM32_MDMA_CXMAR(x) (STM32_MDMA_BASE+STM32_MDMA_CXMAR_OFFSET(x)) +#define STM32_MDMA_C0MAR (STM32_MDMA_BASE+STM32_MDMA_C0MAR_OFFSET) +#define STM32_MDMA_C1MAR (STM32_MDMA_BASE+STM32_MDMA_C1MAR_OFFSET) +#define STM32_MDMA_C2MAR (STM32_MDMA_BASE+STM32_MDMA_C2MAR_OFFSET) +#define STM32_MDMA_C3MAR (STM32_MDMA_BASE+STM32_MDMA_C3MAR_OFFSET) +#define STM32_MDMA_C4MAR (STM32_MDMA_BASE+STM32_MDMA_C4MAR_OFFSET) +#define STM32_MDMA_C5MAR (STM32_MDMA_BASE+STM32_MDMA_C5MAR_OFFSET) +#define STM32_MDMA_C6MAR (STM32_MDMA_BASE+STM32_MDMA_C6MAR_OFFSET) +#define STM32_MDMA_C7MAR (STM32_MDMA_BASE+STM32_MDMA_C7MAR_OFFSET) +#define STM32_MDMA_C8MAR (STM32_MDMA_BASE+STM32_MDMA_C8MAR_OFFSET) +#define STM32_MDMA_C9MAR (STM32_MDMA_BASE+STM32_MDMA_C9MAR_OFFSET) +#define STM32_MDMA_C10MAR (STM32_MDMA_BASE+STM32_MDMA_C10MAR_OFFSET) +#define STM32_MDMA_C11MAR (STM32_MDMA_BASE+STM32_MDMA_C11MAR_OFFSET) +#define STM32_MDMA_C12MAR (STM32_MDMA_BASE+STM32_MDMA_C12MAR_OFFSET) +#define STM32_MDMA_C13MAR (STM32_MDMA_BASE+STM32_MDMA_C13MAR_OFFSET) +#define STM32_MDMA_C14MAR (STM32_MDMA_BASE+STM32_MDMA_C14MAR_OFFSET) +#define STM32_MDMA_C15MAR (STM32_MDMA_BASE+STM32_MDMA_C15MAR_OFFSET) + +#define STM32_MDMA_CXMDR(x) (STM32_MDMA_BASE+STM32_MDMA_CXMDR_OFFSET(x)) +#define STM32_MDMA_C0MDR (STM32_MDMA_BASE+STM32_MDMA_C0MDR_OFFSET) +#define STM32_MDMA_C1MDR (STM32_MDMA_BASE+STM32_MDMA_C1MDR_OFFSET) +#define STM32_MDMA_C2MDR (STM32_MDMA_BASE+STM32_MDMA_C2MDR_OFFSET) +#define STM32_MDMA_C3MDR (STM32_MDMA_BASE+STM32_MDMA_C3MDR_OFFSET) +#define STM32_MDMA_C4MDR (STM32_MDMA_BASE+STM32_MDMA_C4MDR_OFFSET) +#define STM32_MDMA_C5MDR (STM32_MDMA_BASE+STM32_MDMA_C5MDR_OFFSET) +#define STM32_MDMA_C6MDR (STM32_MDMA_BASE+STM32_MDMA_C6MDR_OFFSET) +#define STM32_MDMA_C7MDR (STM32_MDMA_BASE+STM32_MDMA_C7MDR_OFFSET) +#define STM32_MDMA_C8MDR (STM32_MDMA_BASE+STM32_MDMA_C8MDR_OFFSET) +#define STM32_MDMA_C9MDR (STM32_MDMA_BASE+STM32_MDMA_C9MDR_OFFSET) +#define STM32_MDMA_C10MDR (STM32_MDMA_BASE+STM32_MDMA_C10MDR_OFFSET) +#define STM32_MDMA_C11MDR (STM32_MDMA_BASE+STM32_MDMA_C11MDR_OFFSET) +#define STM32_MDMA_C12MDR (STM32_MDMA_BASE+STM32_MDMA_C12MDR_OFFSET) +#define STM32_MDMA_C13MDR (STM32_MDMA_BASE+STM32_MDMA_C13MDR_OFFSET) +#define STM32_MDMA_C14MDR (STM32_MDMA_BASE+STM32_MDMA_C14MDR_OFFSET) +#define STM32_MDMA_C15MDR (STM32_MDMA_BASE+STM32_MDMA_C15MDR_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +/* TODO: MDMA global interrupt/status register */ + +/* TODO: MDMA channel x interrupt/status register*/ + +/* TODO: MDMA channel x interrupt flag clear register */ + +/* TODO: MDMA channel x error status register */ + +/* TODO: MDMA channel x control register */ + +/* TODO: MDMA channel x control register */ + +/* TODO: MDMA channel x block number of data register */ + +/* TODO: MDMA channel x source address register */ + +/* TODO: MDMA channel x destination address register */ + +/* TODO: MDMA channel x block repeat address update register */ + +/* TODO: MDMA channel x link address register */ + +/* TODO: MDMA channel x trigger and bus selection register */ + +/* TODO: MDMA channel x mask address register */ + +/* TODO: MDMA channel x mask data register */ + +/* BDMA ******************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_BDMA_ISR_OFFSET 0x0000 /* BDMA interrupt status register */ +#define STM32_BDMA_IFCR_OFFSET 0x0004 /* BDMA interrupt flag clear register */ +#define STM32_BDMA_CCRX_OFFSET(x) (0x0008+x*0x0014) /* BDMA channel x configuration register */ +#define STM32_BDMA_CCR0_OFFSET STM32_BDMA_CCR0_OFFSET +#define STM32_BDMA_CCR1_OFFSET STM32_BDMA_CCR1_OFFSET +#define STM32_BDMA_CCR2_OFFSET STM32_BDMA_CCR2_OFFSET +#define STM32_BDMA_CCR3_OFFSET STM32_BDMA_CCR3_OFFSET +#define STM32_BDMA_CCR4_OFFSET STM32_BDMA_CCR4_OFFSET +#define STM32_BDMA_CCR5_OFFSET STM32_BDMA_CCR5_OFFSET +#define STM32_BDMA_CCR6_OFFSET STM32_BDMA_CCR6_OFFSET +#define STM32_BDMA_CCR7_OFFSET STM32_BDMA_CCR7_OFFSET +#define STM32_BDMA_CNDTRX_OFFSET(x) (0x000C+x*0x0014) /* BDMA channel x number of data to transfer register */ +#define STM32_BDMA_CNDTR0_OFFSET STM32_BDMA_CNDTR0_OFFSET +#define STM32_BDMA_CNDTR1_OFFSET STM32_BDMA_CNDTR1_OFFSET +#define STM32_BDMA_CNDTR2_OFFSET STM32_BDMA_CNDTR2_OFFSET +#define STM32_BDMA_CNDTR3_OFFSET STM32_BDMA_CNDTR3_OFFSET +#define STM32_BDMA_CNDTR4_OFFSET STM32_BDMA_CNDTR4_OFFSET +#define STM32_BDMA_CNDTR5_OFFSET STM32_BDMA_CNDTR5_OFFSET +#define STM32_BDMA_CNDTR6_OFFSET STM32_BDMA_CNDTR6_OFFSET +#define STM32_BDMA_CNDTR7_OFFSET STM32_BDMA_CNDTR7_OFFSET +#define STM32_BDMA_CPARX_OFFSET(x) (0x0010+x*0x0014) /* BDMA channel x peripheral address register */ +#define STM32_BDMA_CPAR0_OFFSET STM32_BDMA_CPAR0_OFFSET +#define STM32_BDMA_CPAR1_OFFSET STM32_BDMA_CPAR1_OFFSET +#define STM32_BDMA_CPAR2_OFFSET STM32_BDMA_CPAR2_OFFSET +#define STM32_BDMA_CPAR3_OFFSET STM32_BDMA_CPAR3_OFFSET +#define STM32_BDMA_CPAR4_OFFSET STM32_BDMA_CPAR4_OFFSET +#define STM32_BDMA_CPAR5_OFFSET STM32_BDMA_CPAR5_OFFSET +#define STM32_BDMA_CPAR6_OFFSET STM32_BDMA_CPAR6_OFFSET +#define STM32_BDMA_CPAR7_OFFSET STM32_BDMA_CPAR7_OFFSET +#define STM32_BDMA_CM0ARX_OFFSET(x) (0x0014+x*0x0014) /* BDMA channel x memory 0 address register */ +#define STM32_BDMA_CM0AR0_OFFSET STM32_BDMA_CM0AR0_OFFSET +#define STM32_BDMA_CM0AR1_OFFSET STM32_BDMA_CM0AR1_OFFSET +#define STM32_BDMA_CM0AR2_OFFSET STM32_BDMA_CM0AR2_OFFSET +#define STM32_BDMA_CM0AR3_OFFSET STM32_BDMA_CM0AR3_OFFSET +#define STM32_BDMA_CM0AR4_OFFSET STM32_BDMA_CM0AR4_OFFSET +#define STM32_BDMA_CM0AR5_OFFSET STM32_BDMA_CM0AR5_OFFSET +#define STM32_BDMA_CM0AR6_OFFSET STM32_BDMA_CM0AR6_OFFSET +#define STM32_BDMA_CM0AR7_OFFSET STM32_BDMA_CM0AR7_OFFSET +#define STM32_BDMA_CM1ARX_OFFSET(x) (0x0018+x*0x0014) /* BDMA channel x memory 1 address register */ +#define STM32_BDMA_CM1AR0_OFFSET STM32_BDMA_CM1AR0_OFFSET +#define STM32_BDMA_CM1AR1_OFFSET STM32_BDMA_CM1AR1_OFFSET +#define STM32_BDMA_CM1AR2_OFFSET STM32_BDMA_CM1AR2_OFFSET +#define STM32_BDMA_CM1AR3_OFFSET STM32_BDMA_CM1AR3_OFFSET +#define STM32_BDMA_CM1AR4_OFFSET STM32_BDMA_CM1AR4_OFFSET +#define STM32_BDMA_CM1AR5_OFFSET STM32_BDMA_CM1AR5_OFFSET +#define STM32_BDMA_CM1AR6_OFFSET STM32_BDMA_CM1AR6_OFFSET +#define STM32_BDMA_CM1AR7_OFFSET STM32_BDMA_CM1AR7_OFFSET + +/* Register Addresses ***************************************************************/ + +#define STM32_BDMA_ISR (STM32_BDMA_BASE+STM32_BDMA_ISR_OFFSET) +#define STM32_BDMA_IFCR (STM32_BDMA_BASE+STM32_BDMA_IFCR_OFFSET) + +#define STM32_BDMA_CCRX(x) (STM32_BDMA_BASE+STM32_BDMA_CCRX_OFFSET(x)) +#define STM32_BDMA_CCR0 (STM32_BDMA_BASE+STM32_BDMA_CCR0_OFFSET) +#define STM32_BDMA_CCR1 (STM32_BDMA_BASE+STM32_BDMA_CCR1_OFFSET) +#define STM32_BDMA_CCR2 (STM32_BDMA_BASE+STM32_BDMA_CCR2_OFFSET) +#define STM32_BDMA_CCR3 (STM32_BDMA_BASE+STM32_BDMA_CCR3_OFFSET) +#define STM32_BDMA_CCR4 (STM32_BDMA_BASE+STM32_BDMA_CCR4_OFFSET) +#define STM32_BDMA_CCR5 (STM32_BDMA_BASE+STM32_BDMA_CCR5_OFFSET) +#define STM32_BDMA_CCR6 (STM32_BDMA_BASE+STM32_BDMA_CCR6_OFFSET) +#define STM32_BDMA_CCR7 (STM32_BDMA_BASE+STM32_BDMA_CCR7_OFFSET) + +#define STM32_BDMA_CNDTRX(x) (STM32_BDMA_BASE+STM32_BDMA_CNDTRX_OFFSET(x)) +#define STM32_BDMA_CNDTR0 (STM32_BDMA_BASE+STM32_BDMA_CNDTR0_OFFSET) +#define STM32_BDMA_CNDTR1 (STM32_BDMA_BASE+STM32_BDMA_CNDTR1_OFFSET) +#define STM32_BDMA_CNDTR2 (STM32_BDMA_BASE+STM32_BDMA_CNDTR2_OFFSET) +#define STM32_BDMA_CNDTR3 (STM32_BDMA_BASE+STM32_BDMA_CNDTR3_OFFSET) +#define STM32_BDMA_CNDTR4 (STM32_BDMA_BASE+STM32_BDMA_CNDTR4_OFFSET) +#define STM32_BDMA_CNDTR5 (STM32_BDMA_BASE+STM32_BDMA_CNDTR5_OFFSET) +#define STM32_BDMA_CNDTR6 (STM32_BDMA_BASE+STM32_BDMA_CNDTR6_OFFSET) +#define STM32_BDMA_CNDTR7 (STM32_BDMA_BASE+STM32_BDMA_CNDTR7_OFFSET) + +#define STM32_BDMA_CPARX(x) (STM32_BDMA_BASE+STM32_BDMA_CPARX_OFFSET(x)) +#define STM32_BDMA_CPAR0 (STM32_BDMA_BASE+STM32_BDMA_CPAR0_OFFSET) +#define STM32_BDMA_CPAR1 (STM32_BDMA_BASE+STM32_BDMA_CPAR1_OFFSET) +#define STM32_BDMA_CPAR2 (STM32_BDMA_BASE+STM32_BDMA_CPAR2_OFFSET) +#define STM32_BDMA_CPAR3 (STM32_BDMA_BASE+STM32_BDMA_CPAR3_OFFSET) +#define STM32_BDMA_CPAR4 (STM32_BDMA_BASE+STM32_BDMA_CPAR4_OFFSET) +#define STM32_BDMA_CPAR5 (STM32_BDMA_BASE+STM32_BDMA_CPAR5_OFFSET) +#define STM32_BDMA_CPAR6 (STM32_BDMA_BASE+STM32_BDMA_CPAR6_OFFSET) +#define STM32_BDMA_CPAR7 (STM32_BDMA_BASE+STM32_BDMA_CPAR7_OFFSET) + +#define STM32_BDMA_CM0ARX(x) (STM32_BDMA_BASE+STM32_BDMA_CM0ARX_OFFSET(x)) +#define STM32_BDMA_CM0AR0 (STM32_BDMA_BASE+STM32_BDMA_CM0AR0_OFFSET) +#define STM32_BDMA_CM0AR1 (STM32_BDMA_BASE+STM32_BDMA_CM0AR1_OFFSET) +#define STM32_BDMA_CM0AR2 (STM32_BDMA_BASE+STM32_BDMA_CM0AR2_OFFSET) +#define STM32_BDMA_CM0AR3 (STM32_BDMA_BASE+STM32_BDMA_CM0AR3_OFFSET) +#define STM32_BDMA_CM0AR4 (STM32_BDMA_BASE+STM32_BDMA_CM0AR4_OFFSET) +#define STM32_BDMA_CM0AR5 (STM32_BDMA_BASE+STM32_BDMA_CM0AR5_OFFSET) +#define STM32_BDMA_CM0AR6 (STM32_BDMA_BASE+STM32_BDMA_CM0AR6_OFFSET) +#define STM32_BDMA_CM0AR7 (STM32_BDMA_BASE+STM32_BDMA_CM0AR7_OFFSET) + +#define STM32_BDMA_CM1ARX(x) (STM32_BDMA_BASE+STM32_BDMA_CM1ARX_OFFSET(x)) +#define STM32_BDMA_CM1AR0 (STM32_BDMA_BASE+STM32_BDMA_CM1AR0_OFFSET) +#define STM32_BDMA_CM1AR1 (STM32_BDMA_BASE+STM32_BDMA_CM1AR1_OFFSET) +#define STM32_BDMA_CM1AR2 (STM32_BDMA_BASE+STM32_BDMA_CM1AR2_OFFSET) +#define STM32_BDMA_CM1AR3 (STM32_BDMA_BASE+STM32_BDMA_CM1AR3_OFFSET) +#define STM32_BDMA_CM1AR4 (STM32_BDMA_BASE+STM32_BDMA_CM1AR4_OFFSET) +#define STM32_BDMA_CM1AR5 (STM32_BDMA_BASE+STM32_BDMA_CM1AR5_OFFSET) +#define STM32_BDMA_CM1AR6 (STM32_BDMA_BASE+STM32_BDMA_CM1AR6_OFFSET) +#define STM32_BDMA_CM1AR7 (STM32_BDMA_BASE+STM32_BDMA_CM1AR7_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +/* TODO: BDMA interrupt status register */ + +/* TODO: BDMA interrupt flag clear register */ + +/* TODO: BDMA channel x configuration register */ + +/* TODO: BDMA channel x number of data to transfer register */ + +/* TODO: BDMA channel x peripheral address register */ + +/* TODO: BDMA channel x memory 0 address register */ + +/* TODO: BDMA channel x memory 1 address register */ + +/* DMAMUX ***************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX12 request line multiplexer channel x configuration register */ +#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0) +#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1) +#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2) +#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3) +#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4) +#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5) +#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6) +#define STM32_DMAMUX_C7CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(7) +#define STM32_DMAMUX_C8CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(8) +#define STM32_DMAMUX_C9CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(9) +#define STM32_DMAMUX_C10CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(10) +#define STM32_DMAMUX_C11CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(11) +#define STM32_DMAMUX_C12CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(12) +#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13) +#define STM32_DMAMUX_C14CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(14) +#define STM32_DMAMUX_C15CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(15) + /* 0x040-0x07C: Reserved */ +#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX12 request line multiplexer interrupt channel status register */ +#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX12 request line multiplexer interrupt clear flag register */ + /* 0x088-0x0FC: Reserved */ +#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX12 request generator channel x configuration register */ +#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0) +#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1) +#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2) +#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3) +#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX12 request generator interrupt status register */ +#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX12 request generator interrupt clear flag register */ + /* 0x148-0x3FC: Reserved */ + +/* Register Addresses ***************************************************************/ + +#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_CXCR_OFFSET(x)) +#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C0CR_OFFSET) +#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C1CR_OFFSET) +#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C2CR_OFFSET) +#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C3CR_OFFSET) +#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C4CR_OFFSET) +#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C5CR_OFFSET) +#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C6CR_OFFSET) +#define STM32_DMAMUX1_C7CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C7CR_OFFSET) +#define STM32_DMAMUX1_C8CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C8CR_OFFSET) +#define STM32_DMAMUX1_C9CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C9CR_OFFSET) +#define STM32_DMAMUX1_C10CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C10CR_OFFSET) +#define STM32_DMAMUX1_C11CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C11CR_OFFSET) +#define STM32_DMAMUX1_C12CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C12CR_OFFSET) +#define STM32_DMAMUX1_C13CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C12CR_OFFSET) +#define STM32_DMAMUX1_C14CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C13CR_OFFSET) +#define STM32_DMAMUX1_C15CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C14CR_OFFSET) + +#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CSR_OFFSET) +#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CFR_OFFSET) + +#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGXCR_OFFSET(x)) +#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG0CR_OFFSET) +#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG1CR_OFFSET) +#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG2CR_OFFSET) +#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG3CR_OFFSET) + +#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGSR_OFFSET) +#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGCFR_OFFSET) + +#define STM32_DMAMUX2_CXCR(x) (STM32_DMAMUX2_BASE+STM32_DMAMUX_CXCR_OFFSET(x)) +#define STM32_DMAMUX2_C0CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C0CR_OFFSET) +#define STM32_DMAMUX2_C1CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C1CR_OFFSET) +#define STM32_DMAMUX2_C2CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C2CR_OFFSET) +#define STM32_DMAMUX2_C3CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C3CR_OFFSET) +#define STM32_DMAMUX2_C4CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C4CR_OFFSET) +#define STM32_DMAMUX2_C5CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C5CR_OFFSET) +#define STM32_DMAMUX2_C6CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C6CR_OFFSET) +#define STM32_DMAMUX2_C7CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C7CR_OFFSET) +#define STM32_DMAMUX2_C8CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C8CR_OFFSET) +#define STM32_DMAMUX2_C9CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C9CR_OFFSET) +#define STM32_DMAMUX2_C10CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C10CR_OFFSET) +#define STM32_DMAMUX2_C11CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C11CR_OFFSET) +#define STM32_DMAMUX2_C12CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C12CR_OFFSET) +#define STM32_DMAMUX2_C13CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C12CR_OFFSET) +#define STM32_DMAMUX2_C14CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C13CR_OFFSET) +#define STM32_DMAMUX2_C15CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C14CR_OFFSET) + +#define STM32_DMAMUX2_CSR (STM32_DMAMUX2_BASE+STM32_DMAMUX_CSR_OFFSET) +#define STM32_DMAMUX2_CFR (STM32_DMAMUX2_BASE+STM32_DMAMUX_CFR_OFFSET) + +#define STM32_DMAMUX2_RGXCR(x) (STM32_DMAMUX2_BASE+STM32_DMAMUX_RGXCR_OFFSET(x)) +#define STM32_DMAMUX2_RG0CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RG0CR_OFFSET) +#define STM32_DMAMUX2_RG1CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RG1CR_OFFSET) +#define STM32_DMAMUX2_RG2CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RG2CR_OFFSET) +#define STM32_DMAMUX2_RG3CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RG3CR_OFFSET) + +#define STM32_DMAMUX2_RGSR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RGSR_OFFSET) +#define STM32_DMAMUX2_RGCFR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RGCFR_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +/* TODO: DMAMUX12 request line multiplexer channel x configuration register */ + +/* TODO: DMAMUX12 request line multiplexer interrupt channel status register */ + +/* TODO: DMAMUX12 request line multiplexer interrupt clear flag register */ + +/* TODO: DMAMUX12 request generator channel x configuration register */ + +/* TODO: DMAMUX12 request generator interrupt status register */ + +/* TODO: DMAMUX12 request generator interrupt clear flag register */ + +/* DMAMUX1 mapping ****************************************************/ + +/* NOTE: DMAMUX1 channels 0 to 7 are connected to DMA1 channels 0 to 7. + * DMAMUX1 channels 8 to 15 are connected to DMA2 channels 0 to 7. + */ + +#define DMAMUX1_REQ_GEN0 (1) +#define DMAMUX1_REQ_GEN1 (2) +#define DMAMUX1_REQ_GEN2 (3) +#define DMAMUX1_REQ_GEN3 (4) +#define DMAMUX1_REQ_GEN4 (5) +#define DMAMUX1_REQ_GEN5 (6) +#define DMAMUX1_REQ_GEN6 (7) +#define DMAMUX1_REQ_GEN7 (8) +#define DMAMUX1_ADC1 (9) +#define DMAMUX1_ADC2 (10) +#define DMAMUX1_TIM1_CH1 (11) +#define DMAMUX1_TIM1_CH2 (12) +#define DMAMUX1_TIM1_CH3 (13) +#define DMAMUX1_TIM1_CH4 (14) +#define DMAMUX1_TIM1_UP (15) +#define DMAMUX1_TIM1_TRIG (16) +#define DMAMUX1_TIM1_COM (17) +#define DMAMUX1_TIM2_CH1 (18) +#define DMAMUX1_TIM2_CH2 (19) +#define DMAMUX1_TIM2_CH3 (20) +#define DMAMUX1_TIM2_CH4 (21) +#define DMAMUX1_TIM2_UP (22) +#define DMAMUX1_TIM3_CH1 (23) +#define DMAMUX1_TIM3_CH2 (24) +#define DMAMUX1_TIM3_CH3 (25) +#define DMAMUX1_TIM3_CH4 (26) +#define DMAMUX1_TIM3_UP (27) +#define DMAMUX1_TIM3_TRIG (28) +#define DMAMUX1_TIM4_CH1 (29) +#define DMAMUX1_TIM4_CH2 (30) +#define DMAMUX1_TIM4_CH3 (31) +#define DMAMUX1_TIM4_UP (32) +#define DMAMUX1_I2C1_RX (33) +#define DMAMUX1_I2C1_TX (34) +#define DMAMUX1_I2C2_RX (35) +#define DMAMUX1_I2C2_TX (36) +#define DMAMUX1_SPI1_RX (37) +#define DMAMUX1_SPI1_TX (38) +#define DMAMUX1_SPI2_RX (39) +#define DMAMUX1_SPI2_TX (40) +#define DMAMUX1_USART1_TX (41) +#define DMAMUX1_USART1_RX (42) +#define DMAMUX1_USART2_RX (43) +#define DMAMUX1_USART2_TX (44) +#define DMAMUX1_USART3_RX (45) +#define DMAMUX1_USART3_TX (46) +#define DMAMUX1_TIM8_CH1 (47) +#define DMAMUX1_TIM8_CH2 (48) +#define DMAMUX1_TIM8_CH3 (49) +#define DMAMUX1_TIM8_CH4 (50) +#define DMAMUX1_TIM8_UP (51) +#define DMAMUX1_TIM8_TRIG (52) +#define DMAMUX1_TIM8_COM (53) +/* DMAMUX1 54: Reserved */ +#define DMAMUX1_TIM5_CH1 (55) +#define DMAMUX1_TIM5_CH2 (56) +#define DMAMUX1_TIM5_CH3 (57) +#define DMAMUX1_TIM5_CH4 (58) +#define DMAMUX1_TIM5_UP (59) +#define DMAMUX1_TIM5_TRIG (60) +#define DMAMUX1_SPI3_RX (61) +#define DMAMUX1_SPI3_TX (62) +#define DMAMUX1_UART4_RX (63) +#define DMAMUX1_UART4_TX (64) +#define DMAMUX1_UART5_RX (65) +#define DMAMUX1_UART5_TX (66) +#define DMAMUX1_DAC_CH1 (67) +#define DMAMUX1_DAC_CH2 (68) +#define DMAMUX1_TIM6_UP (69) +#define DMAMUX1_TIM7_UP (70) +#define DMAMUX1_USART6_RX (71) +#define DMAMUX1_USART6_TX (72) +#define DMAMUX1_I2C3_RX (73) +#define DMAMUX1_I2C3_TX (74) +#define DMAMUX1_DCMI (75) +#define DMAMUX1_CRYPT_IN (76) +#define DMAMUX1_CRYPT_OUT (77) +#define DMAMUX1_HASH_IN (78) +#define DMAMUX1_UART7_RX (70) +#define DMAMUX1_UART7_TX (80) +#define DMAMUX1_UART8_RX (81) +#define DMAMUX1_UART8_TX (82) +#define DMAMUX1_SPI4_RX (83) +#define DMAMUX1_SPI4_TX (84) +#define DMAMUX1_SPI5_RX (85) +#define DMAMUX1_SPI5_TX (86) +#define DMAMUX1_SAI1A (87) +#define DMAMUX1_SAI1B (88) +#define DMAMUX1_SAI2A (89) +#define DMAMUX1_SAI2B (90) +#define DMAMUX1_SWPMI_RX (91) +#define DMAMUX1_SWPMI_TX (92) +#define DMAMUX1_SPDIFRX_DAT (93) +#define DMAMUX1_SPDIFRX_CTRL (94) +#define DMAMUX1_HR_REQ1 (95) +#define DMAMUX1_HR_REQ2 (96) +#define DMAMUX1_HR_REQ3 (97) +#define DMAMUX1_HR_REQ4 (98) +#define DMAMUX1_HR_REQ5 (99) +#define DMAMUX1_HR_REQ6 (100) +#define DMAMUX1_DFSDM1_0 (101) +#define DMAMUX1_DFSDM1_1 (102) +#define DMAMUX1_DFSDM1_2 (103) +#define DMAMUX1_DFSDM1_3 (104) +#define DMAMUX1_TIM15_CH1 (105) +#define DMAMUX1_TIM15_UP (106) +#define DMAMUX1_TIM15_TRIG (107) +#define DMAMUX1_TIM15_COM (108) +#define DMAMUX1_TIM16_CH1 (109) +#define DMAMUX1_TIM16_UP (110) +#define DMAMUX1_TIM17_CH1 (111) +#define DMAMUX1_TIM17_UP (112) +#define DMAMUX1_SAI3A (113) +#define DMAMUX1_SAI3B (114) +#define DMAMUX1_ADC3 (115) +/* DMAMUX1 116-127: Reserved */ + +/* DMAMUX2 mapping ****************************************************/ + +/* NOTE: DMAMUX2 channels 0 to 7 are connected to BDMA channels 0 to 7 */ + +#define DMAMUX2_REQ_GEN0 (1) +#define DMAMUX2_REQ_GEN1 (2) +#define DMAMUX2_REQ_GEN2 (3) +#define DMAMUX2_REQ_GEN3 (4) +#define DMAMUX2_REQ_GEN4 (5) +#define DMAMUX2_REQ_GEN5 (6) +#define DMAMUX2_REQ_GEN6 (7) +#define DMAMUX2_REQ_GEN7 (8) +#define DMAMUX2_LPUART1_RX (9) +#define DMAMUX2_LPUART1_TX (10) +#define DMAMUX2_SPI6_RX (11) +#define DMAMUX2_SPI6_TX (12) +#define DMAMUX2_I2C4_RX (13) +#define DMAMUX2_I2C4_TX (14) +#define DMAMUX2_SAI4A (15) +#define DMAMUX2_SAI4B (16) +#define DMAMUX2_ADC3 (17) +/* DMAMUX2 18-32: Reserved */ + +#endif /* CONFIG_STM32H7_STM32H7X3XX */ +#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_DMA_H */ diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h b/arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h index 6a34ff411d..d96cf15a69 100644 --- a/arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h +++ b/arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h @@ -527,22 +527,22 @@ /* Bit definitions for RCC_D2CCIP1R reigster */ -#define RCC_D2CCIP1R_SAI1SEL_SHIFT (0) /* Bits 0-2 */ +#define RCC_D2CCIP1R_SAI1SEL_SHIFT (0) /* Bits 0-2 */ #define RCC_D2CCIP1R_SAI1SEL_MASK (7 << RCC_D2CCIP1R_SAI1SEL_MASK) # define RCC_D2CCIP1R_SAI1SEL_PLL1 (0 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 000 */ # define RCC_D2CCIP1R_SAI1SEL_PLL2 (1 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 001 */ # define RCC_D2CCIP1R_SAI1SEL_PLL3 (2 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 010 */ # define RCC_D2CCIP1R_SAI1SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 011 */ # define RCC_D2CCIP1R_SAI1SEL_PER (4 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 100 */ - /* Bits 3-5: Reserved */ -#define RCC_D2CCIP1R_SAI23SEL_SHIFT (6) /* Bits 6-8 */ + /* Bits 3-5: Reserved */ +#define RCC_D2CCIP1R_SAI23SEL_SHIFT (6) /* Bits 6-8 */ #define RCC_D2CCIP1R_SAI23SEL_MASK (7 << RCC_D2CCIP1R_SAI23SEL_SHIFT) # define RCC_D2CCIP1R_SAI23SEL_PLL1 (0 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 000 */ # define RCC_D2CCIP1R_SAI23SEL_PLL2 (1 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 001 */ # define RCC_D2CCIP1R_SAI23SEL_PLL3 (2 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 010 */ # define RCC_D2CCIP1R_SAI23SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 011 */ # define RCC_D2CCIP1R_SAI23SEL_PER (4 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 100 */ - /* Bits 9-11: Reserved */ + /* Bits 9-11: Reserved */ #define RCC_D2CCIP1R_SPI123SEL_SHIFT (12) /* Bits 12-14 */ #define RCC_D2CCIP1R_SPI123SEL_MASK (7 << RCC_D2CCIP1R_SPI123SEL_SHIFT) # define RCC_D2CCIP1R_SPI123SEL_PLL1 (0 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 000 */ @@ -550,7 +550,7 @@ # define RCC_D2CCIP1R_SPI123SEL_PLL3 (2 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 010 */ # define RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 011 */ # define RCC_D2CCIP1R_SPI123SEL_PER (4 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 100 */ - /* Bit 15: Reserved */ + /* Bit 15: Reserved */ #define RCC_D2CCIP1R_SPI45SEL_SHIFT (16) /* Bits 16-18 */ #define RCC_D2CCIP1R_SPI45SEL_MASK (7 << RCC_D2CCIP1R_SPI45SEL_SHIFT) # define RCC_D2CCIP1R_SPI45SEL_APB (0 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 000 */ @@ -559,25 +559,25 @@ # define RCC_D2CCIP1R_SPI45SEL_HSI (3 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 011 */ # define RCC_D2CCIP1R_SPI45SEL_CSI (4 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 100 */ # define RCC_D2CCIP1R_SPI45SEL_HSE (5 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 101 */ - /* Bit 19: Reserved */ + /* Bit 19: Reserved */ #define RCC_D2CCIP1R_SPDIFSEL_SHIFT (20) /* Bits 20-21 */ #define RCC_D2CCIP1R_SPDIFSEL_MASK (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) # define RCC_D2CCIP1R_SPDIFSEL_PLL1 (0 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) /* 00 */ # define RCC_D2CCIP1R_SPDIFSEL_PLL2 (1 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) /* 01 */ # define RCC_D2CCIP1R_SPDIFSEL_PLL3 (2 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) /* 10 */ # define RCC_D2CCIP1R_SPDIFSEL_HSI (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) /* 11 */ - /* Bits 22-23: Reserved */ + /* Bits 22-23: Reserved */ #define RCC_D2CCIP1R_DFSDM1SEL_SHIFT (24) /* Bit 24 */ #define RCC_D2CCIP1R_DFSDM1SEL_MASK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) # define RCC_D2CCIP1R_DFSDM1SEL_PCLK2 (0 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) /* 0 */ # define RCC_D2CCIP1R_DFSDM1SEL_SYSCLK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) /* 1 */ - /* Bits 25-27: Reserved */ + /* Bits 25-27: Reserved */ #define RCC_D2CCIP1R_FDCANSEL_SHIFT (28) /* Bits 28-29 */ #define RCC_D2CCIP1R_FDCANSEL_MASK (3 << RCC_D2CCIP1R_FDCANSEL_SHIFT) # define RCC_D2CCIP1R_FDCANSEL_HSE (0 << RCC_D2CCIP1R_FDCANSEL_SHIFT) /* 00 */ # define RCC_D2CCIP1R_FDCANSEL_PLL1 (1 << RCC_D2CCIP1R_FDCANSEL_SHIFT) /* 01 */ # define RCC_D2CCIP1R_FDCANSEL_PLL2 (2 << RCC_D2CCIP1R_FDCANSEL_SHIFT) /* 10 */ - /* Bit 30: Reserved */ + /* Bit 30: Reserved */ #define RCC_D2CCIP1R_SWPSEL_SHIFT (31) /* Bit 31 */ #define RCC_D2CCIP1R_SWPSEL_MASK (1 << RCC_D2CCIP1R_SWPSEL_SHIFT) # define RCC_D2CCIP1R_SWPSEL_PCLK (0 << RCC_D2CCIP1R_SWPSEL_SHIFT) /* 0 */ @@ -596,13 +596,66 @@ /* TODO: Bit definitions for RCC_D3CCIPR reigster */ -/* ... */ -#define RCC_D3CCIPR_I2C4SEL_SHIFT (8) /* Bits 8-9 */ -#define RCC_D3CCIPR_I2C4SEL_MASK (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) -# define RCC_D3CCIPR_I2C4SEL_PCLK4 (0 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 00 */ -# define RCC_D3CCIPR_I2C4SEL_PLL3 (1 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 01 */ -# define RCC_D3CCIPR_I2C4SEL_HSI (2 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 10 */ -# define RCC_D3CCIPR_I2C4SEL_CSI (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 11 */ +#define RCC_D3CCIPR_LPUART1SEL_SHIFT (0) /* Bits 0-2: LPUART1 kernel clock source selection */ +#define RCC_D3CCIPR_LPUART1SEL_MASK (7 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_PCLK (0 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 000 */ +# define RCC_D3CCIPR_LPUART1SEL_PLL2 (1 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 001 */ +# define RCC_D3CCIPR_LPUART1SEL_PLL3 (2 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 010 */ +# define RCC_D3CCIPR_LPUART1SEL_HSI (3 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 011 */ +# define RCC_D3CCIPR_LPUART1SEL_CSI (4 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 100 */ +# define RCC_D3CCIPR_LPUART1SEL_LSE (5 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 101 */ + /* Bits 3-7: Reserved */ +#define RCC_D3CCIPR_I2C4SEL_SHIFT (8) /* Bits 8-9: I2C4 kernel clock source selection */ +#define RCC_D3CCIPR_I2C4SEL_MASK (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) +# define RCC_D3CCIPR_I2C4SEL_PCLK4 (0 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 00 */ +# define RCC_D3CCIPR_I2C4SEL_PLL3 (1 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 01 */ +# define RCC_D3CCIPR_I2C4SEL_HSI (2 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 10 */ +# define RCC_D3CCIPR_I2C4SEL_CSI (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 11 */ +#define RCC_D3CCIPR_LPTIM2SEL_SHIFT (10) /* Bits 10-12: LPTIM2 kernel clock source selection */ +#define RCC_D3CCIPR_LPTIM2SEL_MASK (7 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_PCLK4 (0 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 000 */ +# define RCC_D3CCIPR_LPTIM2SEL_PLL2 (1 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 001 */ +# define RCC_D3CCIPR_LPTIM2SEL_PLL3 (2 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 010 */ +# define RCC_D3CCIPR_LPTIM2SEL_LSE (3 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 011 */ +# define RCC_D3CCIPR_LPTIM2SEL_LSI (4 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 100 */ +# define RCC_D3CCIPR_LPTIM2SEL_PER (5 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 101 */ +#define RCC_D3CCIPR_LPTIM345SEL_SHIFT (13) /* Bits 13-15: LPTIM3,4,5 kernel clock source selection */ +#define RCC_D3CCIPR_LPTIM345SEL_MASK (7 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_PCLK4 (0 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 000 */ +# define RCC_D3CCIPR_LPTIM345SEL_PLL2 (1 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 001 */ +# define RCC_D3CCIPR_LPTIM345SEL_PLL3 (2 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 010 */ +# define RCC_D3CCIPR_LPTIM345SEL_LSE (3 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 011 */ +# define RCC_D3CCIPR_LPTIM345SEL_LSI (4 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 100 */ +# define RCC_D3CCIPR_LPTIM345SEL_PER (5 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 101 */ +#define RCC_D3CCIPR_ADCSEL_SHIFT (16) /* Bits 16-17: SAR ADC kernel clock source selection */ +#define RCC_D3CCIPR_ADCSEL_MASK (3 << RCC_D3CCIPR_ADCSEL_SHIFT) +# define RCC_D3CCIPR_ADCSEL_PLL2 (0 << RCC_D3CCIPR_ADCSEL_SHIFT) /* 00 */ +# define RCC_D3CCIPR_ADCSEL_PLL3 (1 << RCC_D3CCIPR_ADCSEL_SHIFT) /* 01 */ +# define RCC_D3CCIPR_ADCSEL_PER (2 << RCC_D3CCIPR_ADCSEL_SHIFT) /* 10 */ + /* Bits 18-20: Reserved */ +#define RCC_D3CCIPR_SAI4ASEL_SHIFT (21) /* Bits 21-23: Sub-Block A of SAI4 kernel clock source selection */ +#define RCC_D3CCIPR_SAI4ASEL_MASK (7 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +# define RCC_D3CCIPR_SAI4ASEL_PLL1 (0 << RCC_D3CCIPR_SAI4ASEL_SHIFT) /* 000 */ +# define RCC_D3CCIPR_SAI4ASEL_PLL2 (1 << RCC_D3CCIPR_SAI4ASEL_SHIFT) /* 001 */ +# define RCC_D3CCIPR_SAI4ASEL_PLL3 (2 << RCC_D3CCIPR_SAI4ASEL_SHIFT) /* 010 */ +# define RCC_D3CCIPR_SAI4ASEL_I2CCKIN (3 << RCC_D3CCIPR_SAI4ASEL_SHIFT) /* 011 */ +# define RCC_D3CCIPR_SAI4ASEL_PER (4 << RCC_D3CCIPR_SAI4ASEL_SHIFT) /* 100 */ +#define RCC_D3CCIPR_SAI4BSEL_SHIFT (24) /* Bits 24-26: Sub-Block B of SAI4 kernel clock source selection */ +#define RCC_D3CCIPR_SAI4BSEL_MASK (7 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +# define RCC_D3CCIPR_SAI4BSEL_PLL1 (0 << RCC_D3CCIPR_SAI4BSEL_SHIFT) /* 000 */ +# define RCC_D3CCIPR_SAI4BSEL_PLL2 (1 << RCC_D3CCIPR_SAI4BSEL_SHIFT) /* 001 */ +# define RCC_D3CCIPR_SAI4BSEL_PLL3 (2 << RCC_D3CCIPR_SAI4BSEL_SHIFT) /* 010 */ +# define RCC_D3CCIPR_SAI4BSEL_I2CCKIN (3 << RCC_D3CCIPR_SAI4BSEL_SHIFT) /* 011 */ +# define RCC_D3CCIPR_SAI4BSEL_PER (4 << RCC_D3CCIPR_SAI4BSEL_SHIFT) /* 100 */ +#define RCC_D3CCIPR_SPI6SEL_SHIFT (28) /* Bits 28-30: SPI6 kernel clock source selection */ +#define RCC_D3CCIPR_SPI6SEL_MASK (7 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_PCLK4 (0 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 000 */ +# define RCC_D3CCIPR_SPI6SEL_PLL2 (1 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 001 */ +# define RCC_D3CCIPR_SPI6SEL_PLL3 (2 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 010 */ +# define RCC_D3CCIPR_SPI6SEL_HSI (3 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 011 */ +# define RCC_D3CCIPR_SPI6SEL_CSI (4 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 100 */ +# define RCC_D3CCIPR_SPI6SEL_HSE (5 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 101 */ + /* Bit 31: Reserved */ /* ... */ /* TODO: CIER */ @@ -885,18 +938,26 @@ /* APB4 Peripheral Clock enable register */ -#define RCC_APB4ENR_SYSCFGEN (0x2ul) /* RCC APB4ENR: SYSCFGEN */ -#define RCC_APB4ENR_LPUART1EN (0x8ul) /* RCC APB4ENR: LPUART1EN */ -#define RCC_APB4ENR_SPI6EN (0x20ul) /* RCC APB4ENR: SPI6EN */ -#define RCC_APB4ENR_I2C4EN (0x80ul) /* RCC APB4ENR: I2C4EN */ -#define RCC_APB4ENR_LPTIM2EN (0x200ul) /* RCC APB4ENR: LPTIM2EN */ -#define RCC_APB4ENR_LPTIM3EN (0x400ul) /* RCC APB4ENR: LPTIM3EN */ -#define RCC_APB4ENR_LPTIM4EN (0x800ul) /* RCC APB4ENR: LPTIM4EN */ -#define RCC_APB4ENR_LPTIM5EN (0x1000ul) /* RCC APB4ENR: LPTIM5EN */ -#define RCC_APB4ENR_COMP12EN (0x4000ul) /* RCC APB4ENR: COMP12EN */ -#define RCC_APB4ENR_VREFEN (0x8000ul) /* RCC APB4ENR: VREFEN */ -#define RCC_APB4ENR_RTCAPBEN (0x10000ul) /* RCC APB4ENR: RTCAPBEN */ -#define RCC_APB4ENR_SAI4EN (0x200000ul) /* RCC APB4ENR: SAI4EN */ + /* Bit 0: Reserved */ +#define RCC_APB4ENR_SYSCFGEN (1 << 1) /* Bit 1: RCC APB4ENR: SYSCFGEN */ + /* Bit 2: Reserved */ +#define RCC_APB4ENR_LPUART1EN (1 << 3) /* Bit 3: RCC APB4ENR: LPUART1EN */ + /* Bit 4: Reserved */ +#define RCC_APB4ENR_SPI6EN (1 << 5) /* Bit 5: RCC APB4ENR: SPI6EN */ + /* Bit 6: Reserved */ +#define RCC_APB4ENR_I2C4EN (1 << 7) /* Bit 7: RCC APB4ENR: I2C4EN */ + /* Bit 8: Reserved */ +#define RCC_APB4ENR_LPTIM2EN (1 << 9) /* Bit 9: RCC APB4ENR: LPTIM2EN */ +#define RCC_APB4ENR_LPTIM3EN (1 << 10) /* Bit 10: RCC APB4ENR: LPTIM3EN */ +#define RCC_APB4ENR_LPTIM4EN (1 << 11) /* Bit 11: RCC APB4ENR: LPTIM4EN */ +#define RCC_APB4ENR_LPTIM5EN (1 << 12) /* Bit 12: RCC APB4ENR: LPTIM5EN */ + /* Bit 13: Reserved */ +#define RCC_APB4ENR_COMP12EN (1 << 14) /* Bit 14: RCC APB4ENR: COMP12EN */ +#define RCC_APB4ENR_VREFEN (1 << 15) /* Bit 15: RCC APB4ENR: VREFEN */ +#define RCC_APB4ENR_RTCAPBEN (1 << 16) /* Bit 16: RCC APB4ENR: RTCAPBEN */ + /* Bits 17-20: Reserved */ +#define RCC_APB4ENR_SAI4EN (1 << 21) /* Bit 21: RCC APB4ENR: SAI4EN */ + /* Bit2 22-31: Reserved */ /* AHB3 low power mode peripheral clock enable register */ diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_spi.h b/arch/arm/src/stm32h7/chip/stm32h7x3xx_spi.h new file mode 100644 index 0000000000..24712781af --- /dev/null +++ b/arch/arm/src/stm32h7/chip/stm32h7x3xx_spi.h @@ -0,0 +1,279 @@ +/************************************************************************************ + * arch/arm/src/stm32h7/chip/stm32h7x3xx_spi.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_SPI_H +#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_SPI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_STM32H7_STM32H7X3XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Maximum allowed speed as per data sheet for all SPIs */ + +# define STM32_SPI_CLK_MAX 150000000UL + +/* Register Offsets *****************************************************************/ + +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI/I2S Control Register 1 */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 */ +#define STM32_SPI_CFG1_OFFSET 0x0008 /* SPI configuration register 1 */ +#define STM32_SPI_CFG2_OFFSET 0x000C /* SPI configuration register 2 */ +#define STM32_SPI_IER_OFFSET 0x0010 /* SPI/I2S interupt enable register */ +#define STM32_SPI_SR_OFFSET 0x0014 /* SPI/I2S status register */ +#define STM32_SPI_IFCR_OFFSET 0x0018 /* SPI/I2S interrupt/status flags clear register */ +#define STM32_SPI_TXDR_OFFSET 0x0020 /* SPI/I2S transmit data register */ +#define STM32_SPI_RXDR_OFFSET 0x0030 /* SPI/I2S receive data register */ +#define STM32_SPI_CRCPOLY_OFFSET 0x0040 /* SPI/I2S SPI polynominal register */ +#define STM32_SPI_TXCRC_OFFSET 0x0044 /* SPI/I2S SPI transmitter CRC register */ +#define STM32_SPI_RXCRC_OFFSET 0x0048 /* SPI/I2S SPI receiver CRC register */ +#define STM32_SPI_UDRDR_OFFSET 0x004C /* SPI/I2S SPI underrun data register */ +#define STM32_SPI_I2SCFGR_OFFSET 0x0050 /* SPI/I2S configuration register*/ + +/* Register Addresses ***************************************************************/ + +#if STM32H7_NSPI > 0 +# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_CFG1 (STM32_SPI1_BASE+STM32_SPI_CFG1_OFFSET) +# define STM32_SPI1_CFG2 (STM32_SPI1_BASE+STM32_SPI_CFG2_OFFSET) +# define STM32_SPI1_IER (STM32_SPI1_BASE+STM32_SPI_IER_OFFSET) +# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI1_IFCR (STM32_SPI1_BASE+STM32_SPI_IFCR_OFFSET) +# define STM32_SPI1_TXDR (STM32_SPI1_BASE+STM32_SPI_TXDR_OFFSET) +# define STM32_SPI1_RXDR (STM32_SPI1_BASE+STM32_SPI_RXDR_OFFSET) +# define STM32_SPI1_CRCPOLY (STM32_SPI1_BASE+STM32_SPI_CRCPOLY_OFFSET) +# define STM32_SPI1_TXCRC (STM32_SPI1_BASE+STM32_SPI_TXCRC_OFFSET) +# define STM32_SPI1_RXCRC (STM32_SPI1_BASE+STM32_SPI_RXCRC_OFFSET) +# define STM32_SPI1_UDRDR (STM32_SPI1_BASE+STM32_SPI_UDRDR_OFFSET) +# define STM32_SPI1_I2SCFGR (STM32_SPI1_BASE+STM32_SPI_I2SCFGR_OFFSET) +#endif + +#if STM32H7_NSPI > 1 +# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_CFG1 (STM32_SPI2_BASE+STM32_SPI_CFG1_OFFSET) +# define STM32_SPI2_CFG2 (STM32_SPI2_BASE+STM32_SPI_CFG2_OFFSET) +# define STM32_SPI2_IER (STM32_SPI2_BASE+STM32_SPI_IER_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI2_IFCR (STM32_SPI2_BASE+STM32_SPI_IFCR_OFFSET) +# define STM32_SPI2_TXDR (STM32_SPI2_BASE+STM32_SPI_TXDR_OFFSET) +# define STM32_SPI2_RXDR (STM32_SPI2_BASE+STM32_SPI_RXDR_OFFSET) +# define STM32_SPI2_CRCPOLY (STM32_SPI2_BASE+STM32_SPI_CRCPOLY_OFFSET) +# define STM32_SPI2_TXCRC (STM32_SPI2_BASE+STM32_SPI_TXCRC_OFFSET) +# define STM32_SPI2_RXCRC (STM32_SPI2_BASE+STM32_SPI_RXCRC_OFFSET) +# define STM32_SPI2_UDRDR (STM32_SPI2_BASE+STM32_SPI_UDRDR_OFFSET) +# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET) +#endif + +#if STM32H7_NSPI > 2 +# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI3_CFG1 (STM32_SPI3_BASE+STM32_SPI_CFG1_OFFSET) +# define STM32_SPI3_CFG2 (STM32_SPI3_BASE+STM32_SPI_CFG2_OFFSET) +# define STM32_SPI3_IER (STM32_SPI3_BASE+STM32_SPI_IER_OFFSET) +# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI3_IFCR (STM32_SPI3_BASE+STM32_SPI_IFCR_OFFSET) +# define STM32_SPI3_TXDR (STM32_SPI3_BASE+STM32_SPI_TXDR_OFFSET) +# define STM32_SPI3_RXDR (STM32_SPI3_BASE+STM32_SPI_RXDR_OFFSET) +# define STM32_SPI3_CRCPOLY (STM32_SPI3_BASE+STM32_SPI_CRCPOLY_OFFSET) +# define STM32_SPI3_TXCRC (STM32_SPI3_BASE+STM32_SPI_TXCRC_OFFSET) +# define STM32_SPI3_RXCRC (STM32_SPI3_BASE+STM32_SPI_RXCRC_OFFSET) +# define STM32_SPI3_UDRDR (STM32_SPI3_BASE+STM32_SPI_UDRDR_OFFSET) +# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET) +#endif + +#if STM32H7_NSPI > 3 +# define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI4_CFG1 (STM32_SPI4_BASE+STM32_SPI_CFG1_OFFSET) +# define STM32_SPI4_CFG2 (STM32_SPI4_BASE+STM32_SPI_CFG2_OFFSET) +# define STM32_SPI4_IER (STM32_SPI4_BASE+STM32_SPI_IER_OFFSET) +# define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI4_IFCR (STM32_SPI4_BASE+STM32_SPI_IFCR_OFFSET) +# define STM32_SPI4_TXDR (STM32_SPI4_BASE+STM32_SPI_TXDR_OFFSET) +# define STM32_SPI4_RXDR (STM32_SPI4_BASE+STM32_SPI_RXDR_OFFSET) +# define STM32_SPI4_CRCPOLY (STM32_SPI4_BASE+STM32_SPI_CRCPOLY_OFFSET) +# define STM32_SPI4_TXCRC (STM32_SPI4_BASE+STM32_SPI_TXCRC_OFFSET) +# define STM32_SPI4_RXCRC (STM32_SPI4_BASE+STM32_SPI_RXCRC_OFFSET) +# define STM32_SPI4_UDRDR (STM32_SPI4_BASE+STM32_SPI_UDRDR_OFFSET) +# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET) +#endif + +#if STM32H7_NSPI > 4 +# define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI5_CFG1 (STM32_SPI5_BASE+STM32_SPI_CFG1_OFFSET) +# define STM32_SPI5_CFG2 (STM32_SPI5_BASE+STM32_SPI_CFG2_OFFSET) +# define STM32_SPI5_IER (STM32_SPI5_BASE+STM32_SPI_IER_OFFSET) +# define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI5_IFCR (STM32_SPI5_BASE+STM32_SPI_IFCR_OFFSET) +# define STM32_SPI5_TXDR (STM32_SPI5_BASE+STM32_SPI_TXDR_OFFSET) +# define STM32_SPI5_RXDR (STM32_SPI5_BASE+STM32_SPI_RXDR_OFFSET) +# define STM32_SPI5_CRCPOLY (STM32_SPI5_BASE+STM32_SPI_CRCPOLY_OFFSET) +# define STM32_SPI5_TXCRC (STM32_SPI5_BASE+STM32_SPI_TXCRC_OFFSET) +# define STM32_SPI5_RXCRC (STM32_SPI5_BASE+STM32_SPI_RXCRC_OFFSET) +# define STM32_SPI5_UDRDR (STM32_SPI5_BASE+STM32_SPI_UDRDR_OFFSET) +# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET) +#endif + +#if STM32H7_NSPI > 5 +# define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI6_CFG1 (STM32_SPI6_BASE+STM32_SPI_CFG1_OFFSET) +# define STM32_SPI6_CFG2 (STM32_SPI6_BASE+STM32_SPI_CFG2_OFFSET) +# define STM32_SPI6_IER (STM32_SPI6_BASE+STM32_SPI_IER_OFFSET) +# define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI6_IFCR (STM32_SPI6_BASE+STM32_SPI_IFCR_OFFSET) +# define STM32_SPI6_TXDR (STM32_SPI6_BASE+STM32_SPI_TXDR_OFFSET) +# define STM32_SPI6_RXDR (STM32_SPI6_BASE+STM32_SPI_RXDR_OFFSET) +# define STM32_SPI6_CRCPOLY (STM32_SPI6_BASE+STM32_SPI_CRCPOLY_OFFSET) +# define STM32_SPI6_TXCRC (STM32_SPI6_BASE+STM32_SPI_TXCRC_OFFSET) +# define STM32_SPI6_RXCRC (STM32_SPI6_BASE+STM32_SPI_RXCRC_OFFSET) +# define STM32_SPI6_UDRDR (STM32_SPI6_BASE+STM32_SPI_UDRDR_OFFSET) +# define STM32_SPI6_I2SCFGR (STM32_SPI6_BASE+STM32_SPI_I2SCFGR_OFFSET) +#endif + +/* Register Bitfield Definitions ****************************************************/ + +/* SPI Control Register 1 */ + +#define SPI_CR1_SPE (1 << 0) /* Bit 0: SPI Enable */ + /* Bits 1-7: Reserved */ +#define SPI_CR1_MASRX (1 << 8) /* Bit 8: */ +#define SPI_CR1_CSTART (1 << 9) /* Bit 9: master transfer start */ +#define SPI_CR1_CSUSP (1 << 10) /* Bit 10: master suspend request */ +#define SPI_CR1_HDDIR (1 << 11) /* Bit 11: RX/TX direction at Half-duplex mode */ +#define SPI_CR1_SSI (1 << 12) /* Bit 12: Internal slave select */ +#define SPI_CR1_CRC33_17 (1 << 13) /* Bit 13: 32-bit CRC polynominal configuration */ +#define SPI_CR1_RCRCINI (1 << 14) /* Bit 14: CRC calculation initialization pattern control for receiver */ +#define SPI_CR1_TCRCINI (1 << 15) /* Bit 15: CRC calculation initialization pattern control for transmitter */ +#define SPI_CR1_IOLOCK (1 << 16) /* Bit 16: locking the AF configuration of associated IOs */ + /* Bits 17-31: Reserved */ + +/* SPI Control Register 2 */ + +#define SPI_CR2_TSIZE_SHIFT (0) /* Bits 0-15 */ +#define SPI_CR2_TSIZE_MASK (0xff << SPI_CR2_TSIZE_SHIFT) +#define SPI_CR2_TSER_SHIFT (16) /* Bits 16-31 */ +#define SPI_CR2_TSER_MASK (0xff << SPI_CR2_TSER_SHIFT) + +/* TODO: SPI configuration register 1 */ + +/* TODO: SPI configuration register 2 */ + +/* SPI/I2S status register */ + +#define SPI_SR_RXP (1 << 0) /* Bit 0: Rx-packet available */ +#define SPI_SR_TXP (1 << 1) /* Bit 1: Tx-packet space available */ +#define SPI_SR_DXP (1 << 2) /* Bit 2: duplex packet */ +#define SPI_SR_EOT (1 << 3) /* Bit 3: end of transfer */ +#define SPI_SR_TXTF (1 << 4) /* Bit 4: transmission transfer filled */ +#define SPI_SR_UDR (1 << 5) /* Bit 5: underrun at slave transmission mode */ +#define SPI_SR_OVR (1 << 6) /* Bit 6: overrun */ +#define SPI_SR_CRCE (1 << 7) /* Bit 7: CRC error */ +#define SPI_SR_TIFRE (1 << 8) /* Bit 8: TI frame format error */ +#define SPI_SR_MODF (1 << 9) /* Bit 9: mode fault */ +#define SPI_SR_TSERF (1 << 10) /* Bit 10: additional number of SPI data to be transacted was reload */ +#define SPI_SR_SUSP (1 << 11) /* Bit 11: suspend */ +#define SPI_SR_TXC (1 << 12) /* Bit 12: TxFIFO transmission complete */ +#define SPI_SR_RXPLVL_SHIFT (13) /* Bits 13-14: RxFIFO packing level */ +#define SPI_SR_RXPLVL_MASK (1 << SPI_SR_RXPLVL_SHIFT) +#define SPI_SR_RXWNE (1 << 15) /* Bit 15: RxFIFO word not empty */ +#define SPI_SR_CTSIZE_SHIFT (16) /* Bits 16-31: number of data frames remaining in current TSIZE session */ +#define SPI_SR_CTSIZE_MASK (1 << SPI_SR_CTSIZE_SHIFT) + +/* SPI/I2S interrupt/status flags clear register */ + + /* Bits 0-2: Reserved */ +#define SPI_IFCR_EOTC (1 << 3) /* Bit 3: end of transfer flag clear */ +#define SPI_IFCR_TXTFC (1 << 4) /* Bit 4: transmission Transfer Flilled flag clear */ +#define SPI_IFCR_UDRC (1 << 5) /* Bit 5: underrun flag clear */ +#define SPI_IFCR_OVRC (1 << 6) /* Bit 6: overrun flag clear */ +#define SPI_IFCR_CRCEC (1 << 7) /* Bit 7: CRC error flag clear */ +#define SPI_IFCR_TIFREC (1 << 8) /* Bit 8: TI frame format error flag clear */ +#define SPI_IFCR_MODFC (1 << 9) /* Bit 9: mode fault flag clear */ +#define SPI_IFCR_TSERFC (1 << 10) /* Bit 10: TSERF flag clear*/ +#define SPI_IFCR_SUSPC (1 << 11) /* Bit 11: suspend flag clear */ + /* Bits 12-31: Reserved */ + +/* SPI/I2S transmit data register */ + +#define SPI_TXDR_TXDR_SHIFT (0) /* Bits 0-15: transmit data register */ +#define SPI_TXDR_TXDR_MASK (0xffff << SPI_TXDR_TXDR_SHIFT) + /* Bits 16-31: write ignored */ + +/* SPI/I2S receive data register */ + +#define SPI_RXDR_RXDR_SHIFT (0) /* Bits 0-15: receive data register */ +#define SPI_RXDR_RXDR_MASK (0xffff << SPI_RXDR_RXDR_SHIFT) + /* Bits 16-31: read zero */ + +/* SPI/I2S SPI polynominal register */ + +#define SPI_CRCPOLY_CRCPOLY_SHIFT (0) /* Bits 0-15: CRC polynominal register */ +#define SPI_CRCPOLY_CRCPOLY_MASK (0xffff << SPI_CRCPOLY_CRCPOLY_SHIFT) + /* Bits 16-31: write ignored */ + +/* SPI/I2S SPI transmitter CRC register */ + +#define SPI_TXCRC_TXCRC_SHIFT (0) /* Bits 0-15: CRC register for transmitter */ +#define SPI_TXCRC_TXCRC_MASK (0xffff << SPI_TXCRC_TXCRC_SHIFT) + /* Bits 16-31: write ignored */ + +/* SPI/I2S SPI receiver CRC register */ + +#define SPI_RXCRC_RXCRC_SHIFT (0) /* Bits 0-15: CRC register for receiver */ +#define SPI_RXCRC_RXCRC_MASK (0xffff << SPI_RXCRC_RXCRC_SHIFT) + /* Bits 16-31: read zero */ + +/* SPI/I2S SPI underrun data register */ + +#define SPI_UDRDR_UDRDR_SHIFT (0) /* Bits 0-15: data at slave underrun condition*/ +#define SPI_UDRDR_UDRDR_MASK (0xffff << SPI_UDRDR_UDRDR_SHIFT) + /* Bits 16-31: read zero */ + +/* TODO: SPI/I2S configuration register*/ + + +#endif /* CONFIG_STM32H7_STM32H7X3XX */ +#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_SPI_H */ diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c index 0a7563d902..573f59ee82 100644 --- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c @@ -290,30 +290,36 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1LENR); -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32H7_SPI2 + /* SPI2 clock enable */ + + regval |= RCC_APB1LENR_SPI2EN; +#endif + +#ifdef CONFIG_STM32H7_SPI3 + /* SPI3 clock enable */ + + regval |= RCC_APB1LENR_SPI3EN; +#endif + +#ifdef CONFIG_STM32H7_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1LENR_I2C1EN; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32H7_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1LENR_I2C2EN; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32H7_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1LENR_I2C3EN; #endif -#ifdef CONFIG_STM32F7_I2C4 - /* I2C4 clock enable */ - - regval |= RCC_APB1LENR_I2C4EN; -#endif - // TODO: ... putreg32(regval, STM32_RCC_APB1LENR); /* Enable APB1L peripherals */ @@ -343,6 +349,24 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); +#ifdef CONFIG_STM32H7_SPI1 + /* SPI1 clock enable */ + + regval |= RCC_APB2ENR_SPI1EN; +#endif + +#ifdef CONFIG_STM32H7_SPI4 + /* SPI4 clock enable */ + + regval |= RCC_APB2ENR_SPI4EN; +#endif + +#ifdef CONFIG_STM32H7_SPI5 + /* SPI5 clock enable */ + + regval |= RCC_APB2ENR_SPI5EN; +#endif + // TODO: ... putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ @@ -389,6 +413,18 @@ static inline void rcc_enableapb4(void) regval = getreg32(STM32_RCC_APB4ENR); +#ifdef CONFIG_STM32H7_I2C4 + /* I2C4 clock enable */ + + regval |= RCC_APB4ENR_I2C4EN; +#endif + +#ifdef CONFIG_STM32H7_SPI6 + /* SPI6 clock enable */ + + regval |= RCC_APB4ENR_SPI6EN; +#endif + // TODO: ... putreg32(regval, STM32_RCC_APB4ENR); /* Enable peripherals */ @@ -618,6 +654,29 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_D3CCIPR); #endif + /* Configure SPI source clock */ + +#if defined(STM32_RCC_D2CCIP1R_SPI123SRC) + regval = getreg32(STM32_RCC_D2CCIP1R); + regval &= ~RCC_D2CCIP1R_SPI123SEL_MASK; + regval |= STM32_RCC_D2CCIP1R_SPI123SRC; + putreg32(regval, STM32_RCC_D2CCIP1R); +#endif + +#if defined(STM32_RCC_D2CCIP1R_SPI45SRC) + regval = getreg32(STM32_RCC_D2CCIP1R); + regval &= ~RCC_D2CCIP1R_SPI45SEL_MASK; + regval |= STM32_RCC_D2CCIP1R_SPI45SRC; + putreg32(regval, STM32_RCC_D2CCIP1R); +#endif + +#if defined(STM32_RCC_D3CCIPR_SPI6SRC) + regval = getreg32(STM32_RCC_D3CCIPR); + regval &= ~RCC_D3CCIPR_SPI6SEL_MASK; + regval |= STM32_RCC_D3CCIPR_SPI6SRC; + putreg32(regval, STM32_RCC_D3CCIPR); +#endif + #if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK) /* Low speed internal clock source LSI */