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stm32g4xx: add support for ADC

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raiden00pl 2021-04-12 19:15:48 +02:00 committed by Alan Carvalho de Assis
parent fd754f88b7
commit ff2ae3e894
4 changed files with 189 additions and 204 deletions
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133
arch/arm/src/stm32/hardware/stm32_adc_v2.h
View File

@ -35,7 +35,7 @@
/* Configuration ************************************************************/ /* Configuration ************************************************************/
/* This is implementation for STM32 ADC IPv2 - F0, F3 (without F37x), G4, /* This is implementation for STM32 ADC IPv2 - F0, F3 (without F37x),
* H7, L0, L4, L4+ * H7, L0, L4, L4+
*/ */
@ -363,71 +363,6 @@
# define ADC34_CFGR1_EXTSEL_T7TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC34_CFGR1_EXTSEL_T7TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC34_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T2CC1 (15 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC34_CFGR1_EXTSEL_T2CC1 (15 << ADC_CFGR1_EXTSEL_SHIFT)
#elif defined(CONFIG_STM32_STM32G4XXX)
# define ADC12_CFGR1_EXTSEL_T1CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T1CC2 (1 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T2CC2 (3 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T4CC4 (5 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_EXTI11 (6 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T8TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T8TRGO2 (8 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T1TRGO2 (10 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T3CC4 (15 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T20TRGO (16 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T20TRGO2 (17 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T20CC1 (18 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T20CC2 (19 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T20CC3 (20 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_HRT1TRG1 (21 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_HRT1TRG3 (22 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_HRT1TRG5 (23 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_HRT1TRG6 (24 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_HRT1TRG7 (25 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_HRT1TRG8 (26 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_HRT1TRG9 (27 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_HRT1TRG10 (28 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_LPTIMOUT (29 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_T7TRGO (30 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_RSVD1 (31 << ADC_CFGR1_EXTSEL_SHIFT) /* 11111: Reserved */
# define ADC34_CFGR1_EXTSEL_T3CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T2CC3 (1 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T8CC1 (3 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_EXTI2 (5 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T4CC1 (6 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T8TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T8TRGO2 (8 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T1TRGO2 (10 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T2CC1 (15 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T20TRGO (16 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T20TRGO2 (17 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T20CC1 (18 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG2 (19 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG4 (20 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG1 (21 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG3 (22 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG5 (23 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG6 (24 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG7 (25 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG8 (26 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG9 (27 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG10 (28 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_LPTIMOUT (29 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T7TRGO (30 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_RSVD1 (31 << ADC_CFGR1_EXTSEL_SHIFT) /* 11111: Reserved */
#else #else
# error TODO EXTSEL # error TODO EXTSEL
#endif #endif
@ -654,72 +589,6 @@
# define ADC34_JSQR_JEXTSEL_T2TRGO (13 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC34_JSQR_JEXTSEL_T2TRGO (13 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T7TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC34_JSQR_JEXTSEL_T7TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)
#elif defined(CONFIG_STM32_STM32G4XXX)
# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_EXTI15 (6 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T8TRGO2 (10 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T20TRGO (16 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T20TRGO2 (17 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T20CC4 (18 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_HRT1TRG2 (19 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_HRT1TRG4 (20 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_HRT1TRG5 (21 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_HRT1TRG6 (22 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_HRT1TRG7 (23 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_HRT1TRG8 (24 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_HRT1TRG9 (25 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_HRT1TRG10 (26 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T16CC1 (27 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_RSVD1 (28 << ADC_JSQR_JEXTSEL_SHIFT) /* 11100: Reserved */
# define ADC12_JSQR_JEXTSEL_LPTIMOUT (29 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T7TRGO (30 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_RSVD2 (31 << ADC_JSQR_JEXTSEL_SHIFT) /* 11111: Reserved */
# define ADC34_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T8CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T4CC3 (4 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T4CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T8TRGO2 (10 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T1CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_EXTI3 (13 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T20TRGO (16 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T20TRGO2 (17 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T20CC2 (18 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG2 (19 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG4 (20 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG5 (21 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG6 (22 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG7 (23 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG8 (24 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG9 (25 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG10 (26 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG1 (27 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG3 (28 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_LPTIMOUT (29 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T7TRGO (30 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_RSVD1 (31 << ADC_JSQR_JEXTSEL_SHIFT) /* 11111: Reserved */
#else #else
# error TODO JEXTSEL # error TODO JEXTSEL
#endif #endif

216
arch/arm/src/stm32/hardware/stm32_adc_v2g4.h
View File

@ -32,6 +32,15 @@
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
/* Configuration ************************************************************/
#define HAVE_IP_ADC_V2
#undef HAVE_IP_ADC_V1 /* No ADC IPv1 */
#undef HAVE_ADC_CLOCK_HSI /* No ADC clock from HSI */
#undef HAVE_ADC_POWERDOWN /* No ADC power down */
#define HAVE_ADC_VBAT /* VBAT channel support */
#undef HAVE_BASIC_ADC
/* Base addresses ***********************************************************/ /* Base addresses ***********************************************************/
#define STM32_ADC1_OFFSET 0x0000 #define STM32_ADC1_OFFSET 0x0000
@ -308,6 +317,17 @@
#define ADC_CR_ADCALDIF (1 << 30) /* Bit 30: Differential mode for calibration */ #define ADC_CR_ADCALDIF (1 << 30) /* Bit 30: Differential mode for calibration */
#define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */ #define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */
/* For complaince with the ADC driver we also define ADVREGEN like
* for previous chips. For new chips ST decided to better describe
* the mechanism behind ADVREGEN bits.
*/
#define ADC_CR_ADVREGEN_SHIFT (28)
#define ADC_CR_ADVREGEN_MASK (3 << ADC_CR_ADVREGEN_SHIFT)
# define ADC_CR_ADVREGEN_INTER (0 << ADC_CR_ADVREGEN_SHIFT)
# define ADC_CR_ADVREGEN_ENABLED (1 << ADC_CR_ADVREGEN_SHIFT)
# define ADC_CR_ADVREGEN_DISABLED (2 << ADC_CR_ADVREGEN_SHIFT)
/* ADC configuration register 1 (CFGR1) */ /* ADC configuration register 1 (CFGR1) */
#define ADC_CFGR1_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */ #define ADC_CFGR1_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */
@ -320,38 +340,70 @@
# define ADC_CFGR1_RES_6BIT (0x3 << ADC_CFGR1_RES_SHIFT) /* 6-bit resolution */ # define ADC_CFGR1_RES_6BIT (0x3 << ADC_CFGR1_RES_SHIFT) /* 6-bit resolution */
#define ADC_CFGR1_EXTSEL_SHIFT (5) /* Bits 5-9: External trigger selection for regular group */ #define ADC_CFGR1_EXTSEL_SHIFT (5) /* Bits 5-9: External trigger selection for regular group */
#define ADC_CFGR1_EXTSEL_MASK (0x1f << ADC_CFGR1_EXTSEL_SHIFT) #define ADC_CFGR1_EXTSEL_MASK (0x1f << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_0 (0 << ADC_CFGR1_EXTSEL_SHIFT) /* TODO: Figure out what events go here! */ # define ADC12_CFGR1_EXTSEL_T1CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_1 (1 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T1CC2 (1 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_2 (2 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_3 (3 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T2CC2 (3 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_4 (4 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_5 (5 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T4CC4 (5 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_6 (6 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_EXTI11 (6 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_7 (7 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T8TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_8 (8 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T8TRGO2 (8 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_9 (9 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_10 (10 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T1TRGO2 (10 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_11 (11 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_12 (12 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_13 (13 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_14 (14 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_15 (15 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T3CC4 (15 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_16 (16 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC34_CFGR1_EXTSEL_T20TRGO (16 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_17 (17 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC34_CFGR1_EXTSEL_T20TRGO2 (17 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_18 (18 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T20CC1 (18 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_19 (19 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T20CC2 (19 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_20 (20 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T20CC3 (20 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_21 (21 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_HRT1TRG1 (21 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_22 (22 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_HRT1TRG3 (22 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_23 (23 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_HRT1TRG5 (23 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_24 (24 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_HRT1TRG6 (24 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_25 (25 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_HRT1TRG7 (25 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_26 (26 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_HRT1TRG8 (26 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_27 (27 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_HRT1TRG9 (27 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_28 (28 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_HRT1TRG10 (28 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_29 (29 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_LPTIMOUT (29 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_30 (30 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_T7TRGO (30 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC_CFGR1_EXTSEL_EVENT_31 (31 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC12_CFGR1_EXTSEL_RSVD1 (31 << ADC_CFGR1_EXTSEL_SHIFT) /* 11111: Reserved */
# define ADC34_CFGR1_EXTSEL_T3CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T2CC3 (1 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T8CC1 (3 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_EXTI2 (5 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T4CC1 (6 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T8TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T8TRGO2 (8 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T1TRGO2 (10 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T2CC1 (15 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T20TRGO (16 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T20TRGO2 (17 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T20CC1 (18 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG2 (19 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG4 (20 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG1 (21 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG3 (22 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG5 (23 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG6 (24 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG7 (25 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG8 (26 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG9 (27 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_HRT1TRG10 (28 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_LPTIMOUT (29 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_T7TRGO (30 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC34_CFGR1_EXTSEL_RSVD1 (31 << ADC_CFGR1_EXTSEL_SHIFT) /* 11111: Reserved */
#define ADC_CFGR1_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ #define ADC_CFGR1_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */
#define ADC_CFGR1_EXTEN_MASK (0x3 << ADC_CFGR1_EXTEN_SHIFT) #define ADC_CFGR1_EXTEN_MASK (0x3 << ADC_CFGR1_EXTEN_SHIFT)
# define ADC_CFGR1_EXTEN_NONE (0x0 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection disabled */ # define ADC_CFGR1_EXTEN_NONE (0x0 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection disabled */
@ -603,38 +655,70 @@
# define ADC_JSQR_JL_4 (0x3 << ADC_JSQR_JL_SHIFT) /* 4 conversions */ # define ADC_JSQR_JL_4 (0x3 << ADC_JSQR_JL_SHIFT) /* 4 conversions */
#define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-6: External trigger selection for injected group */ #define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-6: External trigger selection for injected group */
#define ADC_JSQR_JEXTSEL_MASK (0x1f << ADC_JSQR_JEXTSEL_SHIFT) #define ADC_JSQR_JEXTSEL_MASK (0x1f << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_0 (0 << ADC_JSQR_JEXTSEL_SHIFT) /* TODO: Figure out what events go here! */ # define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_1 (1 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_2 (2 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_3 (3 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_4 (4 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_5 (5 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_6 (6 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_EXTI15 (6 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_7 (7 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_8 (8 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_9 (9 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_10 (10 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T8TRGO2 (10 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_11 (11 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_12 (12 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_13 (13 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_14 (14 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_15 (15 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_16 (16 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T20TRGO (16 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_17 (17 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T20TRGO2 (17 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_18 (18 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T20CC4 (18 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_19 (19 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_HRT1TRG2 (19 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_20 (20 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_HRT1TRG4 (20 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_21 (21 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_HRT1TRG5 (21 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_22 (22 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_HRT1TRG6 (22 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_23 (23 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_HRT1TRG7 (23 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_24 (24 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_HRT1TRG8 (24 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_25 (25 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_HRT1TRG9 (25 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_26 (26 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_HRT1TRG10 (26 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_27 (27 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T16CC1 (27 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_28 (28 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_RSVD1 (28 << ADC_JSQR_JEXTSEL_SHIFT) /* 11100: Reserved */
# define ADC_JSQR_JEXTSEL_EVENT_29 (29 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_LPTIMOUT (29 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_30 (30 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T7TRGO (30 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL_EVENT_31 (31 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_RSVD2 (31 << ADC_JSQR_JEXTSEL_SHIFT) /* 11111: Reserved */
# define ADC34_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T8CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T4CC3 (4 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T4CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T8TRGO2 (10 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T1CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_EXTI3 (13 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T20TRGO (16 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T20TRGO2 (17 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T20CC2 (18 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG2 (19 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG4 (20 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG5 (21 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG6 (22 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG7 (23 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG8 (24 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG9 (25 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG10 (26 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG1 (27 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_HRT1TRG3 (28 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_LPTIMOUT (29 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T7TRGO (30 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_RSVD1 (31 << ADC_JSQR_JEXTSEL_SHIFT) /* 11111: Reserved */
#define ADC_JSQR_JEXTEN_SHIFT (7) /* Bits 7-8: External trigger enable and polarity selection for injected channels */ #define ADC_JSQR_JEXTEN_SHIFT (7) /* Bits 7-8: External trigger enable and polarity selection for injected channels */
#define ADC_JSQR_JEXTEN_MASK (0x3 << ADC_JSQR_JEXTEN_SHIFT) #define ADC_JSQR_JEXTEN_MASK (0x3 << ADC_JSQR_JEXTEN_SHIFT)
# define ADC_JSQR_JEXTEN_NONE (0x0 << ADC_JSQR_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ # define ADC_JSQR_JEXTEN_NONE (0x0 << ADC_JSQR_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
@ -769,8 +853,8 @@
# define ADC_CCR_PRESC_128 (0xa << ADC_CCR_PRESC_SHIFT) /* 1010: Input ADC clock divided by 128 */ # define ADC_CCR_PRESC_128 (0xa << ADC_CCR_PRESC_SHIFT) /* 1010: Input ADC clock divided by 128 */
# define ADC_CCR_PRESC_256 (0xb << ADC_CCR_PRESC_SHIFT) /* 1011: Input ADC clock divided by 256 */ # define ADC_CCR_PRESC_256 (0xb << ADC_CCR_PRESC_SHIFT) /* 1011: Input ADC clock divided by 256 */
#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */ #define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */
#define ADC_CCR_TSENSESEL (1 << 23) /* Bit 23: Temperature sensor enable */ #define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */
#define ADC_CCR_VBATSEL (1 << 24) /* Bit 24: VBAT enable */ #define ADC_CCR_VBATEN (1 << 24) /* Bit 24: VBAT enable */
/* Common regular data register for dual mode */ /* Common regular data register for dual mode */

34
arch/arm/src/stm32/stm32_adc.c
View File

@ -141,10 +141,16 @@
# define RCC_RSTR_ADC123RST RCC_APB2RSTR_ADCRST # define RCC_RSTR_ADC123RST RCC_APB2RSTR_ADCRST
# endif # endif
#elif defined(HAVE_IP_ADC_V2) #elif defined(HAVE_IP_ADC_V2)
# ifdef STM32_RCC_AHB2RSTR_OFFSET
# define STM32_RCC_RSTR STM32_RCC_AHB2RSTR
# define RCC_RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST
# define RCC_RSTR_ADC34RST RCC_AHB2RSTR_ADC345RST
# else
# define STM32_RCC_RSTR STM32_RCC_AHBRSTR # define STM32_RCC_RSTR STM32_RCC_AHBRSTR
# define RCC_RSTR_ADC12RST RCC_AHBRSTR_ADC12RST # define RCC_RSTR_ADC12RST RCC_AHBRSTR_ADC12RST
# define RCC_RSTR_ADC34RST RCC_AHBRSTR_ADC34RST # define RCC_RSTR_ADC34RST RCC_AHBRSTR_ADC34RST
# endif # endif
#endif
/* ADC Channels/DMA *********************************************************/ /* ADC Channels/DMA *********************************************************/
@ -213,6 +219,31 @@
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP16_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP16_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP17_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP17_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP18_SHIFT)) (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP18_SHIFT))
#elif defined(CONFIG_STM32_STM32G4XXX)
# if defined(ADC_HAVE_DMA) || (CONFIG_STM32_ADC_MAX_SAMPLES == 1)
# define ADC_SMPR_DEFAULT ADC_SMPR_47p5
# else /* Slow down sampling frequency */
# define ADC_SMPR_DEFAULT ADC_SMPR_640p5
# endif
# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP0_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR1_SMP1_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR1_SMP2_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR1_SMP3_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR1_SMP4_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR1_SMP5_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR1_SMP6_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR1_SMP7_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR1_SMP8_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR1_SMP9_SHIFT))
# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP10_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP11_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP12_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP13_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP14_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP15_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP16_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP17_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP18_SHIFT))
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F37XX) || \ #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F37XX) || \
defined(CONFIG_STM32_STM32F4XXX) defined(CONFIG_STM32_STM32F4XXX)
# if defined(CONFIG_STM32_STM32F37XX) # if defined(CONFIG_STM32_STM32F37XX)
@ -289,7 +320,8 @@
#if defined(CONFIG_STM32_STM32F10XX) #if defined(CONFIG_STM32_STM32F10XX)
# define ADC_CHANNELS_NUMBER 18 # define ADC_CHANNELS_NUMBER 18
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F4XXX) defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F4XXX) || \
defined(CONFIG_STM32_STM32G4XXX)
# define ADC_CHANNELS_NUMBER 19 # define ADC_CHANNELS_NUMBER 19
#elif defined(CONFIG_STM32_STM32L15XX) #elif defined(CONFIG_STM32_STM32L15XX)
# define ADC_CHANNELS_NUMBER 32 # define ADC_CHANNELS_NUMBER 32

4
arch/arm/src/stm32/stm32_adc.h
View File

@ -610,7 +610,7 @@
* for other 3 ADC's * for other 3 ADC's
*/ */
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) #if defined(HAVE_IP_ADC_V2)
# define ADC1_EXTSEL_T1CC1 ADC12_CFGR1_EXTSEL_T1CC1 # define ADC1_EXTSEL_T1CC1 ADC12_CFGR1_EXTSEL_T1CC1
# define ADC1_EXTSEL_T1CC2 ADC12_CFGR1_EXTSEL_T1CC2 # define ADC1_EXTSEL_T1CC2 ADC12_CFGR1_EXTSEL_T1CC2
# define ADC1_EXTSEL_T1CC3 ADC12_CFGR1_EXTSEL_T1CC3 # define ADC1_EXTSEL_T1CC3 ADC12_CFGR1_EXTSEL_T1CC3
@ -1102,7 +1102,7 @@
* NOTE: Assumptions like for EXTSEL definitions (look above) * NOTE: Assumptions like for EXTSEL definitions (look above)
*/ */
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) #if defined(HAVE_IP_ADC_V2)
# define ADC1_JEXTSEL_T1CC1 ADC12_JSQR_JEXTSEL_T1CC1 # define ADC1_JEXTSEL_T1CC1 ADC12_JSQR_JEXTSEL_T1CC1
# define ADC1_JEXTSEL_T1CC2 ADC12_JSQR_JEXTSEL_T1CC2 # define ADC1_JEXTSEL_T1CC2 ADC12_JSQR_JEXTSEL_T1CC2
# define ADC1_JEXTSEL_T1CC3 ADC12_JSQR_JEXTSEL_T1CC3 # define ADC1_JEXTSEL_T1CC3 ADC12_JSQR_JEXTSEL_T1CC3