Finish ethernet register bit definitions
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2714 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -72,7 +72,7 @@
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/* Control registers */
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#define LPC17_ETH_COMMAND_OFFSET 0x0100 /* Command register */
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#define LPC17_ETH_CMD_OFFSET 0x0100 /* Command register */
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#define LPC17_ETH_STAT_OFFSET 0x0104 /* Status register */
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#define LPC17_ETH_RXDESC_OFFSET 0x0108 /* Receive descriptor base address register */
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#define LPC17_ETH_RXSTAT_OFFSET 0x010c /* Receive status base address register */
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@ -129,7 +129,7 @@
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/* Control registers */
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#define LPC17_ETH_COMMAND (LPC17_ETH_BASE+LPC17_ETH_COMMAND_OFFSET)
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#define LPC17_ETH_CMD (LPC17_ETH_BASE+LPC17_ETH_CMD_OFFSET)
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#define LPC17_ETH_STAT (LPC17_ETH_BASE+LPC17_ETH_STAT_OFFSET)
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#define LPC17_ETH_RXDESC (LPC17_ETH_BASE+LPC17_ETH_RXDESC_OFFSET)
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#define LPC17_ETH_RXSTAT (LPC17_ETH_BASE+LPC17_ETH_RXSTAT_OFFSET)
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@ -165,104 +165,339 @@
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/* Register bit definitions *********************************************************/
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/* MAC registers */
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/* MAC configuration register 1 (MAC1) */
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/* MAC configuration register 1 */
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#define ETH_MAC1_
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/* MAC configuration register 2 */
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#define ETH_MAC2_
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/* Back-to-Back Inter-Packet-Gap register */
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#define ETH_IPGT_
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/* Non Back-to-Back Inter-Packet-Gap register */
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#define ETH_IPGR_
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/* Collision window / Retry register */
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#define ETH_CLRT_
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/* Maximum Frame register */
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#define ETH_MAXF_
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/* PHY Support register */
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#define ETH_SUPP_
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/* Test register */
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#define ETH_TEST_
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/* MII Mgmt Configuration register */
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#define ETH_MCFG_
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/* MII Mgmt Command register */
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#define ETH_MCMD_
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/* MII Mgmt Address register */
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#define ETH_MADR_
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/* MII Mgmt Write Data register */
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#define ETH_MWTD_
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/* MII Mgmt Read Data register */
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#define ETH_MRDD_
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/* MII Mgmt Indicators register */
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#define ETH_MIND_
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/* Station Address 0 register */
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#define ETH_SA0_
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/* Station Address 1 register */
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#define ETH_SA1_
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/* Station Address 2 register */
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#define ETH_SA2_
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#define ETH_MAC1_RE (1 << 0) /* Bit 0: Receive enable */
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#define ETH_MAC1_PARF (1 << 1) /* Bit 1: Passall all receive frames */
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#define ETH_MAC1_RFC (1 << 2) /* Bit 2: RX flow control */
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#define ETH_MAC1_TFC (1 << 3) /* Bit 3: TX flow control */
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#define ETH_MAC1_LPBK (1 << 4) /* Bit 4: Loopback */
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/* Bits 5-7: Reserved */
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#define ETH_MAC1_TXRST (1 << 8) /* Bit 8: Reset TX */
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#define ETH_MAC1_MCSTXRST (1 << 9) /* Bit 9: Reset MCS/TX */
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#define ETH_MAC1_RXRST (1 << 10) /* Bit 10: Reset RX */
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#define ETH_MAC1_MCSRXRST (1 << 11) /* Bit 11: Reset MCS/RX */
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/* Bits 12-13: Reserved */
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#define ETH_MAC1_SIMRST (1 << 14) /* Bit 14: Simulation reset */
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#define ETH_MAC1_SOFTRST (1 << 15) /* Bit 15: Soft reset */
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/* Bits 16-31: Reserved */
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/* MAC configuration register 2 (MAC2) */
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#define ETH_MAC2_FD (1 << 0) /* Bit 0: Full duplex */
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#define ETH_MAC2_FLC (1 << 1) /* Bit 1: Frame length checking */
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#define ETH_MAC2_HFE (1 << 2) /* Bit 2: Huge fram enable */
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#define ETH_MAC2_DCRC (1 << 3) /* Bit 3: Delayed CRC */
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#define ETH_MAC2_CRCEN (1 << 4) /* Bit 4: CRC enable */
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#define ETH_MAC2_PADCRCEN (1 << 5) /* Bit 5: Pad/CRC enable */
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#define ETH_MAC2_VLANPADEN (1 << 6) /* Bit 6: VLAN pad enable */
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#define ETH_MAC2_AUTOPADEN (1 << 7) /* Bit 7: Auto detect pad enable */
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#define ETH_MAC2_PPE (1 << 8) /* Bit 8: Pure preamble enforcement */
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#define ETH_MAC2_LPE (1 << 9) /* Bit 9: Long preamble enforcement */
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/* Bits 10-11: Reserved */
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#define ETH_MAC2_NBKOFF (1 << 12) /* Bit 12: No backoff */
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#define ETH_MAC2_BPNBKOFF (1 << 13) /* Bit 13: Back pressure/no backoff */
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#define ETH_MAC2_EXDEF (1 << 14) /* Bit 14: Excess defer */
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/* Bits 15-31: Reserved */
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/* Back-to-Back Inter-Packet-Gap register (IPGT) */
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#define ETH_IPGT_SHIFT (0) /* Bits 0-6 */
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#define ETH_IPGT_MASK (0x7f << ETH_IPGT_SHIFT)
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/* Bits 7-31: Reserved */
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/* Non Back-to-Back Inter-Packet-Gap register (IPGR) */
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#define ETH_IPGR_GAP2_SHIFT (0) /* Bits 0-6: Gap part 2 */
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#define ETH_IPGR_GAP2_MASK (0x7f << ETH_IPGR_GAP2_SHIFT)
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/* Bit 7: Reserved */
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#define ETH_IPGR_GAP1_SHIFT (8) /* Bits 8-18: Gap part 1 */
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#define ETH_IPGR_GAP1_MASK (0x7f << ETH_IPGR_GAP2_SHIFT)
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/* Bits 15-31: Reserved */
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/* Collision window / Retry register (CLRT) */
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#define ETH_CLRT_RMAX_SHIFT (0) /* Bits 0-3: Retransmission maximum */
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#define ETH_CLRT_RMAX_MASK (15 << ETH_CLRT_RMAX_SHIFT)
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/* Bits 4-7: Reserved */
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#define ETH_CLRT_COLWIN_SHIFT (8) /* Bits 8-13: Collision window */
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#define ETH_CLRT_COLWIN_MASK (0x3f << ETH_CLRT_COLWIN_SHIFT)
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/* Bits 14-31: Reserved */
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/* Maximum Frame register (MAXF) */
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#define ETH_MAXF_SHIFT (0) /* Bits 0-15 */
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#define ETH_MAXF_MASK (0xffff << ETH_MAXF_SHIFT)
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/* Bits 16-31: Reserved */
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/* PHY Support register (SUPP) */
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/* Bits 0-7: Reserved */
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#define ETH_SUPP_SPEED (1 << 8) /* Bit 8: 0=10Bps 1=100Bps */
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/* Bits 9-31: Reserved */
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/* Test register (TEST) */
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#define ETH_TEST_SPQ (1 << 0) /* Bit 0: Shortcut pause quanta */
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#define ETH_TEST_TP (1 << 1) /* Bit 1: Test pause */
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#define ETH_TEST_TBP (1 << 2) /* Bit 2: Test packpressure */
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/* Bits 3-31: Reserved */
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/* MII Mgmt Configuration register (MCFG) */
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#define ETH_MCFG_SCANINC (1 << 0) /* Bit 0: Scan increment */
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#define ETH_MCFG_SUPPRE (1 << 1) /* Bit 1: Suppress preamble */
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#define ETH_MCFG_CLKSEL_SHIFT (2) /* Bits 2-5:Clock select */
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#define ETH_MCFG_CLKSEL_MASK (15 << ETH_MCFG_CLKSEL_SHIFT)
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# define ETH_MCFG_CLKSEL_DIV4 (0 << ETH_MCFG_CLKSEL_SHIFT)
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# define ETH_MCFG_CLKSEL_DIV6 (2 << ETH_MCFG_CLKSEL_SHIFT)
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# define ETH_MCFG_CLKSEL_DIV8 (3 << ETH_MCFG_CLKSEL_SHIFT)
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# define ETH_MCFG_CLKSEL_DIV10 (4 << ETH_MCFG_CLKSEL_SHIFT)
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# define ETH_MCFG_CLKSEL_DIV14 (5 << ETH_MCFG_CLKSEL_SHIFT)
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# define ETH_MCFG_CLKSEL_DIV20 (6 << ETH_MCFG_CLKSEL_SHIFT)
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# define ETH_MCFG_CLKSEL_DIV28 (7 << ETH_MCFG_CLKSEL_SHIFT)
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# define ETH_MCFG_CLKSEL_DIV36 (8 << ETH_MCFG_CLKSEL_SHIFT)
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# define ETH_MCFG_CLKSEL_DIV40 (9 << ETH_MCFG_CLKSEL_SHIFT)
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# define ETH_MCFG_CLKSEL_DIV44 (10 << ETH_MCFG_CLKSEL_SHIFT)
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# define ETH_MCFG_CLKSEL_DIV48 (11 << ETH_MCFG_CLKSEL_SHIFT)
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# define ETH_MCFG_CLKSEL_DIV52 (12 << ETH_MCFG_CLKSEL_SHIFT)
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# define ETH_MCFG_CLKSEL_DIV56 (13 << ETH_MCFG_CLKSEL_SHIFT)
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# define ETH_MCFG_CLKSEL_DIV60 (14 << ETH_MCFG_CLKSEL_SHIFT)
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# define ETH_MCFG_CLKSEL_DIV64 (15 << ETH_MCFG_CLKSEL_SHIFT)
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/* Bits 6-14: Reserved */
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#define ETH_MCFG_MIIRST (1 << 15) /* Bit 15: Reset MII mgmt */
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/* Bits 16-31: Reserved */
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/* MII Mgmt Command register (MCMD) */
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#define ETH_MCMD_READ (1 << 0) /* Bit 0: Single read cycle */
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#define ETH_MCMD_SCAN (1 << 1) /* Bit 1: Continuous read cycles */
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/* Bits 2-31: Reserved */
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/* MII Mgmt Address register (MADR) */
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#define ETH_MADR_REGADDR_SHIFT (0) /* Bits 0-4: Register address */
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#define ETH_MADR_REGADDR_MASK (31 << ETH_MADR_REGADDR_SHIFT)
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/* Bits 7-5: Reserved */
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#define ETH_MADR_PHYADDR_SHIFT (8) /* Bits 8-12: PHY address */
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#define ETH_MADR_PHYADDR_MASK (31 << ETH_MADR_PHYADDR_SHIFT)
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/* Bits 13-31: Reserved */
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/* MII Mgmt Write Data register (MWTD) */
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#define ETH_MWTD_SHIFT (0) /* Bits 9-15 */
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#define ETH_MWTD_MASK (0xffff << ETH_MWTD_SHIFT)
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/* Bits 16-31: Reserved */
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/* MII Mgmt Read Data register (MRDD) */
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#define ETH_MRDD_SHIFT (0) /* Bits 9-15 */
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#define ETH_MRDD_MASK (0xffff << ETH_MRDD_SHIFT)
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/* Bits 16-31: Reserved */
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/* MII Mgmt Indicators register (MIND) */
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#define ETH_MIND_BUSY (1 << 0) /* Bit 0: Busy */
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#define ETH_MIND_SCANNING (1 << 1) /* Bit 1: Scanning */
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#define ETH_MIND_NVALID (1 << 2) /* Bit 2: Not valid */
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#define ETH_MIND_MIIFAIL (1 << 3) /* Bit 3: MII link fail */
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/* Bits 4-31: Reserved */
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/* Station Address 0 register (SA0) */
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#define ETH_SA0_OCTET2_SHIFT (0) /* Bits 0-7: Station address 2nd octet */
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#define ETH_SA0_OCTET2_MASK (0xff << ETH_SA0_OCTET2_SHIFT)
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#define ETH_SA0_OCTET1_SHIFT (8) /* Bits 8-15: Station address 1st octet */
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#define ETH_SA0_OCTET1_MASK (0xff << ETH_SA0_OCTET1_SHIFT)
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/* Bits 16-31: Reserved */
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/* Station Address 1 register (SA1) */
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#define ETH_SA1_OCTET4_SHIFT (0) /* Bits 0-7: Station address 4th octet */
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#define ETH_SA1_OCTET4_MASK (0xff << ETH_SA0_OCTET4_SHIFT)
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#define ETH_SA1_OCTET3_SHIFT (8) /* Bits 8-15: Station address 3rd octet */
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#define ETH_SA1_OCTET3_MASK (0xff << ETH_SA0_OCTET3_SHIFT)
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/* Bits 16-31: Reserved */
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/* Station Address 2 register (SA2) */
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#define ETH_SA2_OCTET6_SHIFT (0) /* Bits 0-7: Station address 5th octet */
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#define ETH_SA2_OCTET6_MASK (0xff << ETH_SA0_OCTET6_SHIFT)
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#define ETH_SA2_OCTET5_SHIFT (8) /* Bits 8-15: Station address 6th octet */
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#define ETH_SA2_OCTET5_MASK (0xff << ETH_SA0_OCTET5_SHIFT)
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/* Bits 16-31: Reserved */
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/* Control registers */
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/* Command register (CMD) */
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/* Command register */
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#define ETH_COMMAND_
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#define ETH_CMD_RXEN (1 << 0) /* Bit 0: Receive enable */
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#define ETH_CMD_TXEN (1 << 1) /* Bit 1: Transmit enable */
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/* Bit 2: Reserved */
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#define ETH_CMD_REGRST (1 << 3) /* Bit 3: Reset host registers */
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#define ETH_CMD_TXRST (1 << 4) /* Bit 4: Reset transmit datapath */
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#define ETH_CMD_RXRST (1 << 5) /* Bit 5: Reset receive datapath */
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#define ETH_CMD_PRFRAME (1 << 6) /* Bit 6: Pass run frame */
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#define ETH_CMD_PRFILTER (1 << 7) /* Bit 7: Pass RX filter */
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#define ETH_CMD_TXFC (1 << 8) /* Bit 8: TX flow control */
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#define ETH_CMD_RMII (1 << 9) /* Bit 9: RMII mode */
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#define ETH_CMD_FD (1 << 10) /* Bit 10: Full duplex */
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/* Bits 11-31: Reserved */
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/* Status register */
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#define ETH_STAT_
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/* Receive descriptor base address register */
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#define ETH_RXDESC_
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/* Receive status base address register */
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#define ETH_RXSTAT_
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/* Receive number of descriptors register */
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#define ETH_RXDESCNO_
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/* Receive produce index register */
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#define ETH_RXPRODIDX_
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/* Receive consume index register */
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#define ETH_RXCONSIDX_
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/* Transmit descriptor base address register */
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#define ETH_TXDESC_
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/* Transmit status base address register */
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#define ETH_TXSTAT_
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/* Transmit number of descriptors register */
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#define ETH_TXDESCRNO_
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/* Transmit produce index register */
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#define ETH_TXPRODIDX_
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/* Transmit consume index register */
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#define ETH_TXCONSIDX_
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/* Transmit status vector 0 register */
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#define ETH_TSV0_
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/* Transmit status vector 1 register */
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#define ETH_TSV1_
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/* Receive status vector register */
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#define ETH_RSV_
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/* Flow control counter register */
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#define ETH_FCCNTR_
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/* Flow control status register */
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#define ETH_FCSTAT_
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#define ETH_STAT_RX (1 << 0) /* Bit 0: RX status */
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#define ETH_STAT_TX (1 << 1) /* Bit 1: TX status */
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/* Bits 2-31: Reserved */
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/* Receive descriptor base address register (RXDESC)
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*
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* The receive descriptor base address is a byte address aligned to a word
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* boundary i.e. LSB 1:0 are fixed to 00. The register contains the lowest
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* address in the array of descriptors.
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*/
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/* Receive status base address register (RXSTAT)
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*
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* The receive status base address is a byte address aligned to a double word
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* boundary i.e. LSB 2:0 are fixed to 000.
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*/
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/* Receive number of descriptors register (RXDESCNO) */
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#define ETH_RXDESCNO_SHIFT (0) /* Bits 0-15 */
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#define ETH_RXDESCNO_MASK (0xffff << ETH_RXDESCNO_SHIFT)
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/* Bits 16-31: Reserved */
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/* Receive produce index register (RXPRODIDX) */
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#define ETH_RXPRODIDX_SHIFT (0) /* Bits 0-15 */
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#define ETH_RXPRODIDX_MASK (0xffff << ETH_RXPRODIDX_SHIFT)
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/* Bits 16-31: Reserved */
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/* Receive consume index register (RXCONSIDX) */
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#define ETH_RXCONSIDX_SHIFT (0) /* Bits 0-15 */
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#define ETH_RXCONSIDX_MASK (0xffff << ETH_RXPRODIDX_SHIFT)
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/* Bits 16-31: Reserved */
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/* Transmit descriptor base address register (TXDESC)
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*
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* The transmit descriptor base address is a byte address aligned to a word
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* boundary i.e. LSB 1:0 are fixed to 00. The register contains the lowest
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* address in the array of descriptors.
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*/
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/* Transmit status base address register (TXSTAT)
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*
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* The transmit status base address is a byte address aligned to a word
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* boundary i.e. LSB1:0 are fixed to 00. The register contains the lowest
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* address in the array of statuses.
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*/
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/* Transmit number of descriptors register (TXDESCRNO) */
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#define ETH_TXDESCRNO_SHIFT (0) /* Bits 0-15 */
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#define ETH_TXDESCRNO_MASK (0xffff << ETH_TXDESCRNO_SHIFT)
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/* Bits 16-31: Reserved */
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/* Transmit produce index register (TXPRODIDX) */
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#define ETH_TXPRODIDX_SHIFT (0) /* Bits 0-15 */
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#define ETH_TXPRODIDX_MASK (0xffff << ETH_TXPRODIDX_SHIFT)
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/* Bits 16-31: Reserved */
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/* Transmit consume index register (TXCONSIDX) */
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#define ETH_TXCONSIDX_SHIFT (0) /* Bits 0-15 */
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#define ETH_TXCONSIDX_MASK (0xffff << ETH_TXPRODIDX_SHIFT)
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/* Bits 16-31: Reserved */
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/* Transmit status vector 0 register (TSV0) */
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#define ETH_TSV0_CRCERR (1 << 0) /* Bit 0: CRC error */
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#define ETH_TSV0_LENCHKERR (1 << 1) /* Bit 1: Length check error */
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#define ETH_TSV0_LENOOR (1 << 2) /* Bit 2: Length out of range */
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#define ETH_TSV0_DONE (1 << 3) /* Bit 3: Done */
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#define ETH_TSV0_MCAST (1 << 4) /* Bit 4: Multicast */
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#define ETH_TSV0_BCAST (1 << 5) /* Bit 5: Broadcast */
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#define ETH_TSV0_PKTDEFER (1 << 6) /* Bit 6: Packet Defer */
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#define ETH_TSV0_EXCDEFER (1 << 7) /* Bit 7: Excessive Defer */
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#define ETH_TSV0_EXCCOL (1 << 8) /* Bit 8: Excessive Collision */
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#define ETH_TSV0_LATECOL (1 << 9) /* Bit 9: Late Collision */
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#define ETH_TSV0_GIANT (1 << 10) /* Bit 10: Giant */
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#define ETH_TSV0_UNDRUN (1 << 11) /* Bit 11: Underrun */
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#define ETH_TSV0_TOTBYTES_SHIFT (12) /* Bits 12-27:Total bytes */
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#define ETH_TSV0_TOTBYTES_MASK (0xffff << ETH_TSV0_TOTBYTES_SHIFT)
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#define ETH_TSV0_CTLFRAME (1 << 28) /* Bit 28: Control frame */
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#define ETH_TSV0_PAUSE (1 << 29) /* Bit 29: Pause */
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#define ETH_TSV0_BP (1 << 30) /* Bit 30: Backpressure */
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#define ETH_TSV0_VLAN (1 << 31) /* Bit 31: VLAN */
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/* Transmit status vector 1 register (TSV1) */
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#define ETH_TSV1_TXCNT_SHIFT (0) /* Bits 0-15: Transmit byte count */
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#define ETH_TSV1_TXCNT_MASK (0xffff << ETH_TSV1_TXCNT_SHIFT)
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#define ETH_TSV1_COLCNT_SHIFT (16) /* Bits 16-19: Transmit collision count */
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#define ETH_TSV1_COLCNT_MASK (15 << ETH_TSV1_COLCNT_SHIFT)
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/* Bits 20-31: Reserved */
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/* Receive status vector register (RSV) */
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#define ETH_RSV_RXCNT_SHIFT (0) /* Bits 0-15: Received byte count */
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#define ETH_RSV_RXCNT_MASK (0xffff << ETH_RSV_RXCNT_SHIFT)
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#define ETH_RSV_PKTPI (1 << 16) /* Bit 16: Packet previously ignored */
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#define ETH_RSV_RXEPS (1 << 17) /* Bit 17: RXDV event previously seen */
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#define ETH_RSV_CEPS (1 << 18) /* Bit 18: Carrier event previously seen */
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#define ETH_RSV_RXCV (1 << 19) /* Bit 19: Receive code violation */
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#define ETH_RSV_CRCERR (1 << 20) /* Bit 20: CRC error */
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#define ETH_RSV_LENCHKERR (1 << 21) /* Bit 21: Length check error */
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#define ETH_RSV_LENOOR (1 << 22) /* Bit 22: Length out of range */
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#define ETH_RSV_RXOK (1 << 23) /* Bit 23: Receive OK */
|
||||
#define ETH_RSV_MCAST (1 << 24) /* Bit 24: Multicast */
|
||||
#define ETH_RSV_BCAST (1 << 25) /* Bit 25: Broadcast */
|
||||
#define ETH_RSV_DRIBNIB (1 << 26) /* Bit 26: Dribble Nibble */
|
||||
#define ETH_RSV_CTLFRAME (1 << 27) /* Bit 27: Control frame */
|
||||
#define ETH_RSV_PAUSE (1 << 28) /* Bit 28: Pause */
|
||||
#define ETH_RSV_UNSUPOP (1 << 29) /* Bit 29: Unsupported Opcode */
|
||||
#define ETH_RSV_VLAN (1 << 30) /* Bit 30: VLAN */
|
||||
/* Bit 31: Reserved */
|
||||
/* Flow control counter register (FCCNTR) */
|
||||
|
||||
#define ETH_FCCNTR_MCOUNT_SHIFT (0) /* Bits 0-15: Mirror count */
|
||||
#define ETH_FCCNTR_MCOUNT_MASK (0xffff << ETH_FCCNTR_MCOUNT_SHIFT)
|
||||
#define ETH_FCCNTR_PTMR_SHIFT (16) /* Bits 16-31: Pause timer */
|
||||
#define ETH_FCCNTR_PTMR_MASK (0xffff << ETH_FCCNTR_PTMR_SHIFT)
|
||||
|
||||
/* Flow control status register (FCSTAT) */
|
||||
|
||||
#define ETH_FCSTAT_MCOUNT_SHIFT (0) /* Bits 0-15: Current mirror count */
|
||||
#define ETH_FCSTAT_MCOUNT_MASK (0xffff << ETH_FCSTAT_MCOUNT_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
/* Rx filter registers */
|
||||
/* Receive filter control register (RXFLCTRL) */
|
||||
|
||||
/* Receive filter control register */
|
||||
#define ETH_RXFLCTRL_
|
||||
/* Receive filter WoL status register */
|
||||
#define ETH_RXFLWOLST_
|
||||
/* Receive filter WoL clear register */
|
||||
#define ETH_RXFLWOLCLR_
|
||||
/* Hash filter table LSBs register */
|
||||
#define ETH_HASHFLL_
|
||||
/* Hash filter table MSBs register */
|
||||
#define ETH_HASHFLH_
|
||||
#define ETH_RXFLCTRL_UCASTEN (1 << 0) /* Bit 0: Accept all unicast frames */
|
||||
#define ETH_RXFLCTRL_BCASTEN (1 << 1) /* Bit 1: Accept all broadcast frames */
|
||||
#define ETH_RXFLCTRL_MCASTEN (1 << 2) /* Bit 2: Accept all multicast frames */
|
||||
#define ETH_RXFLCTRL_UCASTHASHEN (1 << 3) /* Bit 3: Accept hashed unicast */
|
||||
#define ETH_RXFLCTRL_MCASTHASHEN (1 << 4) /* Bit 4: Accect hashed multicast */
|
||||
#define ETH_RXFLCTRL_PERFEN (1 << 5) /* Bit 5: Accept perfect dest match */
|
||||
/* Bits 6-11: Reserved */
|
||||
#define ETH_RXFLCTRL_MPKTEN (1 << 12) /* Bit 12: Magic pkt filter WoL int */
|
||||
#define ETH_RXFLCTRL_RXFILEN (1 << 13) /* Bit 13: Perfect math WoL interrupt */
|
||||
/* Bits 14-31: Reserved */
|
||||
/* Receive filter WoL status register (RXFLWOLST) AND
|
||||
* Receive filter WoL clear register (RXFLWOLCLR)
|
||||
*/
|
||||
|
||||
#define ETH_RXFLWOL_UCAST (1 << 0) /* Bit 0: Unicast frame WoL */
|
||||
#define ETH_RXFLWOL_BCAST (1 << 1) /* Bit 1: Broadcast frame WoL */
|
||||
#define ETH_RXFLWOL_MCAST (1 << 2) /* Bit 2: Multicast frame WoL */
|
||||
#define ETH_RXFLWOL_UCASTHASH (1 << 3) /* Bit 3: Unicast hash filter WoL */
|
||||
#define ETH_RXFLWOL_MCASTHASH (1 << 4) /* Bit 4: Multiicast hash filter WoL */
|
||||
#define ETH_RXFLWOL_PERF (1 << 5) /* Bit 5: Perfect addr match WoL */
|
||||
/* Bit 6: Reserved */
|
||||
#define ETH_RXFLWOL_RXFIL (1 << 7) /* Bit 7: Receive filter WoL */
|
||||
#define ETH_RXFLWOL_MPKT (1 << 8) /* Bit 8: Magic pkt filter WoL */
|
||||
/* Bits 9-31: Reserved */
|
||||
/* Hash filter table LSBs register (HASHFLL) AND Hash filter table MSBs register
|
||||
* (HASHFLH) Are registers containing a 32-bit value with no bitfield.
|
||||
*/
|
||||
|
||||
/* Module control registers */
|
||||
/* Interrupt status register (INTST), Interrupt enable register (INTEN), Interrupt
|
||||
* clear register (INTCLR), and Interrupt set register (INTSET) common bit field
|
||||
* definition:
|
||||
*/
|
||||
|
||||
/* Interrupt status register */
|
||||
#define ETH_INTST_
|
||||
/* Interrupt enable register */
|
||||
#define ETH_INTEN_
|
||||
/* Interrupt clear register */
|
||||
#define ETH_INTCLR_
|
||||
/* Interrupt set register */
|
||||
#define ETH_INTSET_
|
||||
#define ETH_INT_RXOVR (1 << 0) /* Bit 0: RX overrun interrupt */
|
||||
#define ETH_INT_RXERR (1 << 1) /* Bit 1: RX error interrupt */
|
||||
#define ETH_INT_RXFIN (1 << 2) /* Bit 2: RX finished interrupt */
|
||||
#define ETH_INT_RXDONE (1 << 3) /* Bit 3: RX done interrupt */
|
||||
#define ETH_INT_TXUNR (1 << 4) /* Bit 4: TX underrun interrupt */
|
||||
#define ETH_INT_TXERR (1 << 5) /* Bit 5: TX error interrupt */
|
||||
#define ETH_INT_TXFIN (1 << 6) /* Bit 6: TX finished interrupt */
|
||||
#define ETH_INT_TXDONE (1 << 7) /* Bit 7: TX done interrupt */
|
||||
/* Bits 8-11: Reserved */
|
||||
#define ETH_INT_SOFT (1 << 12) /* Bit 12: Soft interrupt */
|
||||
#define ETH_INT_WKUP (1 << 13) /* Bit 13: Wakeup interrupt */
|
||||
/* Bits 14-31: Reserved */
|
||||
/* Power-down register */
|
||||
#define ETH_PWRDOWN_
|
||||
/* Bits 0-30: Reserved */
|
||||
#define ETH_PWRDOWN_MACAHB (1 << 31) /* Power down MAC/AHB */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
|
||||
Loading…
Reference in New Issue
Block a user