PIC32MZ: Add Oscillator header file; Add logic to set up peripheral clocks on reset
This commit is contained in:
Gregory Nutt
parent
7019b48be4
commit
ff43c7ef00
@ -42,10 +42,10 @@
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#include <nuttx/config.h>
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#if defined(CHIP_PIC32MZEC) || defined(CHIP_PIC32MZ2)
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#if defined(CONFIG_ARCH_CHIP_PIC32MZEC)
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# include <chip/pic32mzec-features.h>
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#else
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# error "Unknown PIC32MZ family
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# error Unknown PIC32MZ family
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#endif
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#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_FEATURES_H */
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233
arch/mips/src/pic32mz/chip/pic32mz-osc.h
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233
arch/mips/src/pic32mz/chip/pic32mz-osc.h
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/****************************************************************************
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* arch/mips/src/pic32mz/chip/pic32mz-osc.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_OSC_H
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#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_OSC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "pic32mz-memorymap.h"
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/****************************************************************************
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* Pre-Processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define PIC32MZ_OSCCON_OFFSET 0x0000 /* Oscillator control register offset */
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#define PIC32MZ_OSCTUN_OFFSET 0x0010 /* FRC tuning register offset */
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#define PIC32MZ_SPLLCON_OFFSET 0x0020 /* System PLL control register */
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#define PIC32MZ_REFO1CON_OFFSET 0x0080 /* Reference oscillator control register 1 */
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#define PIC32MZ_REFO1TRIM_OFFSET 0x00a0 /* Reference oscillator trim register 1 */
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#define PIC32MZ_REFO2CON_OFFSET 0x00b0 /* Reference oscillator control register 2 */
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#define PIC32MZ_REFO2TRIM_OFFSET 0x00c0 /* Reference oscillator trim register 2 */
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#define PIC32MZ_REFO3CON_OFFSET 0x00d0 /* Reference oscillator control register 3 */
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#define PIC32MZ_REFO3TRIM_OFFSET 0x00e0 /* Reference oscillator trim register 3 */
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#define PIC32MZ_REFO4CON_OFFSET 0x00f0 /* Reference oscillator control register 4 */
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#define PIC32MZ_REFO4TRIM_OFFSET 0x0100 /* Reference oscillator trim register 4 */
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#define PIC32MZ_PB1DIV_OFFSET 0x0100 /* Peripheral bus 1 clock divisor control register */
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#define PIC32MZ_PB2DIV_OFFSET 0x0110 /* Peripheral bus 2 clock divisor control register */
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#define PIC32MZ_PB3DIV_OFFSET 0x0120 /* Peripheral bus 3 clock divisor control register */
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#define PIC32MZ_PB4DIV_OFFSET 0x0130 /* Peripheral bus 4 clock divisor control register */
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#define PIC32MZ_PB5DIV_OFFSET 0x0140 /* Peripheral bus 5 clock divisor control register */
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#define PIC32MZ_PB6DIV_OFFSET 0x0150 /* Peripheral bus 6 clock divisor control register */
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#define PIC32MZ_PB7DIV_OFFSET 0x0160 /* Peripheral bus 7 clock divisor control register */
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#define PIC32MZ_PB8DIV_OFFSET 0x0170 /* Peripheral bus 8 clock divisor control register */
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/* Register Addresses *******************************************************/
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#define PIC32MZ_OSCCON (PIC32MZ_OSC_K1BASE+PIC32MZ_OSCCON_OFFSET)
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#define PIC32MZ_OSCTUN (PIC32MZ_OSC_K1BASE+PIC32MZ_OSCTUN_OFFSET)
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#define PIC32MZ_SPLLCON (PIC32MZ_OSC_K1BASE+PIC32MZ_SPLLCON_OFFSET)
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#define PIC32MZ_REFO1CON (PIC32MZ_OSC_K1BASE+PIC32MZ_REFO1CON_OFFSET)
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#define PIC32MZ_REFO1TRIM (PIC32MZ_OSC_K1BASE+PIC32MZ_REFO1TRIM_OFFSET)
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#define PIC32MZ_REFO2CON (PIC32MZ_OSC_K1BASE+PIC32MZ_REFO2CON_OFFSET)
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#define PIC32MZ_REFO2TRIM (PIC32MZ_OSC_K1BASE+PIC32MZ_REFO2TRIM_OFFSET)
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#define PIC32MZ_REFO3CON (PIC32MZ_OSC_K1BASE+PIC32MZ_REFO3CON_OFFSET)
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#define PIC32MZ_REFO3TRIM (PIC32MZ_OSC_K1BASE+PIC32MZ_REFO3TRIM_OFFSET)
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#define PIC32MZ_REFO4CON (PIC32MZ_OSC_K1BASE+PIC32MZ_REFO4CON_OFFSET)
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#define PIC32MZ_REFO4TRIM (PIC32MZ_OSC_K1BASE+PIC32MZ_REFO4TRIM_OFFSET)
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#define PIC32MZ_PB1DIV (PIC32MZ_OSC_K1BASE+PIC32MZ_PB1DIV_OFFSET)
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#define PIC32MZ_PB2DIV (PIC32MZ_OSC_K1BASE+PIC32MZ_PB2DIV_OFFSET)
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#define PIC32MZ_PB3DIV (PIC32MZ_OSC_K1BASE+PIC32MZ_PB3DIV_OFFSET)
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#define PIC32MZ_PB4DIV (PIC32MZ_OSC_K1BASE+PIC32MZ_PB4DIV_OFFSET)
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#define PIC32MZ_PB5DIV (PIC32MZ_OSC_K1BASE+PIC32MZ_PB5DIV_OFFSET)
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#define PIC32MZ_PB6DIV (PIC32MZ_OSC_K1BASE+PIC32MZ_PB6DIV_OFFSET)
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#define PIC32MZ_PB7DIV (PIC32MZ_OSC_K1BASE+PIC32MZ_PB7DIV_OFFSET)
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#define PIC32MZ_PB8DIV (PIC32MZ_OSC_K1BASE+PIC32MZ_PB8DIV_OFFSET)
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/* Register Bit-Field Definitions *******************************************/
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/* Oscillator control register offset */
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#define OSCCON_OSWEN (1 << 0) /* Bit 0: Oscillator switch enable */
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#define OSCCON_SOSCEN (1 << 1) /* Bit 1: 32.768kHz secondary oscillator enable */
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#define OSCCON_CF (1 << 3) /* Bit 3: Clock fail detect */
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#define OSCCON_SLPEN (1 << 4) /* Bit 4: Sleep mode enable */
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#define OSCCON_SLOCK (1 << 5) /* Bit 5: PLL lock status */
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#define OSCCON_ULOCK (1 << 6) /* Bit 6: USB PLL lock status */
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#define OSCCON_CLKLOCK (1 << 7) /* Bit 7: Clock selection lock enable */
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#define OSCCON_NOSC_SHIFT (8) /* Bits 8-10: New oscillator selection */
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#define OSCCON_NOSC_MASK (7 << OSCCON_NOSC_SHIFT)
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# define OSCCON_NOSC_FRC (0 << OSCCON_NOSC_SHIFT) /* Internal fast RC oscillator / FRCDIV */
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# define OSCCON_NOSC_SPLL (1 << OSCCON_NOSC_SHIFT) /* System PLL */
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# define OSCCON_NOSC_POSC (2 << OSCCON_NOSC_SHIFT) /* Primary oscillator (HS or EC) */
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# define OSCCON_NOSC_SOSC (4 << OSCCON_NOSC_SHIFT) /* Secondary oscillator */
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# define OSCCON_NOSC_LPRC (5 << OSCCON_NOSC_SHIFT) /* Internal low power RC oscillator */
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# define OSCCON_NOSC_FRCDIV (7 << OSCCON_NOSC_SHIFT) /* Internal fast RC / FRCDIV */
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#define OSCCON_COSC_SHIFT (12) /* Bits 12-14: Current oscillator selection */
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#define OSCCON_COSC_MASK (7 << OSCCON_COSC_SHIFT)
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# define OSCCON_COSC_FRC (0 << OSCCON_COSC_SHIFT) /* Internal fast RC oscillator / FRCDIV */
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# define OSCCON_COSC_SPLL (1 << OSCCON_COSC_SHIFT) /* System PLL */
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# define OSCCON_COSC_POSC (2 << OSCCON_COSC_SHIFT) /* Primary oscillator (HS or EC) */
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# define OSCCON_COSC_SOSC (4 << OSCCON_COSC_SHIFT) /* Secondary oscillator */
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# define OSCCON_COSC_LPRC (5 << OSCCON_COSC_SHIFT) /* Internal low power RC oscillator */
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# define OSCCON_COSC_BFRC (5 << OSCCON_COSC_SHIFT) /* Back-up Fast RC Oscillator */
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# define OSCCON_COSC_FRCDIV (7 << OSCCON_COSC_SHIFT) /* Internal fast RC / FRCDIV */
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#define OSCCON_SOSCRDY (1 << 22) /* Bit 22: Secondary oscillator ready */
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#define OSCCON_DRMEN (1 << 23) /* Bit 23: Dream mode enable */
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#define OSCCON_FRCDIV_SHIFT (24) /* Bits 24-26: FRC oscillator divider */
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#define OSCCON_FRCDIV_MASK (7 << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV(n) ((uint32_t)((n)-1) << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV_DIV1 (0 << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV_DIV2 (1 << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV_DIV4 (2 << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV_DIV8 (3 << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV_DIV16 (4 << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV_DIV32 (5 << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV_DIV64 (6 << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV_DIV256 (7 << OSCCON_FRCDIV_SHIFT)
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/* FRC tuning register offset (6-bit, signed twos complement) */
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#define OSCTUN_SHIFT (0) /* Bits 0-5: FRC tuning bits */
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#define OSCTUN_MASK (0x3f << OSCTUN_SHIFT)
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# define OSCTUN_MIN (0x20 << OSCTUN_SHIFT)
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# define OSCTUN_CENTER (0x00 << OSCTUN_SHIFT)
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# define OSCTUN_MAX (0x1f << OSCTUN_SHIFT)
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/* System PLL control register */
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#define SPLLCON_PLLRANGE_SHIFT (0) /* Bits 0-2: System PLL Frequency Range Selection bits */
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#define SPLLCON_PLLRANGE_MASK (7 << SPLLCON_PLLRANGE_SHIFT)
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# define SPLLCON_PLLRANGE_BYPASS (0 << SPLLCON_PLLRANGE_SHIFT) /* Bypass */
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# define SPLLCON_PLLRANGE_5_10MHZ (1 << SPLLCON_PLLRANGE_SHIFT) /* 5-10 MHz */
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# define SPLLCON_PLLRANGE_8_16MHZ (2 << SPLLCON_PLLRANGE_SHIFT) /* 8-16 MHz */
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# define SPLLCON_PLLRANGE_13_26MHZ (3 << SPLLCON_PLLRANGE_SHIFT) /* 13-26 MHz */
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# define SPLLCON_PLLRANGE_21_42MHZ (4 << SPLLCON_PLLRANGE_SHIFT) /* 21-42 MHz */
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# define SPLLCON_PLLRANGE_34_64MHZ (5 << SPLLCON_PLLRANGE_SHIFT) /* 34-64 MHz */
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#define SPLLCON_PLLICLK (1 << 7) /* Bit 7: System PLL Input Clock Source bit */
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#define SPLLCON_PLLIDIV_SHIFT (8) /* Bits 8-10: System PLL Input Clock Divider bits */
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#define SPLLCON_PLLIDIV_MASK (7 << SPLLCON_PLLIDIV_SHIFT)
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# define SPLLCON_PLLIDIV(n) ((uint32_t)((n)-1) << SPLLCON_PLLIDIV_SHIFT) /* Divide by n, n=1..8 */
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#define SPLLCON_PLLMULT_SHIFT (16) /* Bits 16-22 <6:0>: System PLL Multiplier bits */
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#define SPLLCON_PLLMULT_MASK (0x7f << SPLLCON_PLLMULT_SHIFT)
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# define SPLLCON_PLLMULT(n) ((uint32_t)((n)-1) << SPLLCON_PLLMULT_SHIFT) /* Muliply by n, n=1..128 */
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#define SPLLCON_PLLODIV_SHIFT (24) /* Bits 24-26: System PLL Output Clock Divider bits */
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#define SPLLCON_PLLODIV_MASK (7 << SPLLCON_PLLODIV_SHIFT)
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# define SPLLCON_PLLODIV_2 (1 << SPLLCON_PLLODIV_SHIFT) /* PLL Divide by 2 */
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# define SPLLCON_PLLODIV_4 (2 << SPLLCON_PLLODIV_SHIFT) /* PLL Divide by 4 */
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# define SPLLCON_PLLODIV_8 (3 << SPLLCON_PLLODIV_SHIFT) /* PLL Divide by 8 */
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# define SPLLCON_PLLODIV_16 (4 << SPLLCON_PLLODIV_SHIFT) /* PLL Divide by 16 */
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# define SPLLCON_PLLODIV_32 (5 << SPLLCON_PLLODIV_SHIFT) /* PLL Divide by 32 */
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/* Reference oscillator control register n, n=1..4 */
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#define REFOCON_ROSEL_SHIFT (0) /* Bits 0-3: Reference Clock Source Select bits */
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#define REFOCON_ROSEL_MASK (15 << REFOCON_ROSEL_SHIFT)
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# define REFOCON_ROSEL_SYSCLK (0 << REFOCON_ROSEL_SHIFT) /* SYSCLK */
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# define REFOCON_ROSEL_PBCLK1 (1 << REFOCON_ROSEL_SHIFT) /* PBCLK1 */
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# define REFOCON_ROSEL_POSC (2 << REFOCON_ROSEL_SHIFT) /* POSC */
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# define REFOCON_ROSEL_FRC (3 << REFOCON_ROSEL_SHIFT) /* FRC */
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# define REFOCON_ROSEL_LPRC (4 << REFOCON_ROSEL_SHIFT) /* LPRC */
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# define REFOCON_ROSEL_SOSC (5 << REFOCON_ROSEL_SHIFT) /* SOSC */
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# define REFOCON_ROSEL_SPLL (7 << REFOCON_ROSEL_SHIFT) /* System PLL output */
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# define REFOCON_ROSEL_REFCLKI (8 << REFOCON_ROSEL_SHIFT) /* REFCLKIx */
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# define REFOCON_ROSEL_BFRC (9 << REFOCON_ROSEL_SHIFT) /* BFRC */
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#define REFOCON_ACTIVE (1 << 8) /* Bit 8: Reference Clock Request Status bit */
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#define REFOCON_DIVSWEN (1 << 9) /* Bit 9: Divider Switch Enable bit */
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#define REFOCON_RSLP (1 << 11) /* Bit 11: Reference Oscillator Module Run in Sleep bit */
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#define REFOCON_OE (1 << 12) /* Bit 12: Reference Clock Output Enable bit */
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#define REFOCON_SIDL (1 << 13) /* Bit 13: Peripheral Stop in Idle Mode bit */
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#define REFOCON_ON (1 << 15) /* Bit 15: Output Enable bit */
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#define REFOCON_RODIV_SHIFT (16) /* Bits 16-30: Reference Clock Divider bits */
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#define REFOCON_RODIV_MASK (0x7fff << REFOCON_RODIV_SHIFT)
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# define REFOCON_RODIV(n) ((uint32_t)(n) << REFOCON_RODIV_SHIFT)
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/* Reference oscillator trim register n, n=1..4 */
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#define REFOTRIM_SHIFT (23) /* Bits 23-31: Reference Oscillator Trim bits */
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#define REFOTRIM_MASK (0x1ff << REFOTRIM_SHIFT)
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/* Peripheral bus n clock divisor control register n=1..8 */
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#define PBDIV_SHIFT (0) /* Bits 0-6: Peripheral Bus Clock Divisor Control bits */
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#define PBDIV_MASK (0x7f << PBDIV_SHIFT)
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# define PBDIV(n) ((uint32_t)((n)-1) << PBDIV_SHIFT) /* PBCLK = SYSLCK/n, n=1..128 */
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#define PBDIV_PBDIVRDY (1 << 11) /* Bit 11: Peripheral Bus Clock Divisor Ready bit */
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#define PBDIV_ON (1 << 15) /* Bit 15: Peripheral Bus Output Clock Enable bit */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_OSC_H */
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@ -49,34 +49,34 @@
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********************************************************************************************/
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/* Prefetch register offsets ****************************************************************/
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#define PIC32MZ_PREFETCH_PRECON_OFFSET 0x0000 /* Prefetch module control register */
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#define PIC32MZ_PREFETCH_PRESTAT_OFFSET 0x0000 /* Prefetch module status register */
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#define PIC32MZ_PRECON_OFFSET 0x0000 /* Prefetch module control register */
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#define PIC32MZ_PRESTAT_OFFSET 0x0000 /* Prefetch module status register */
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/* Prefetch register addresses **************************************************************/
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#define PIC32MZ_PREFETCH_PRECON (PIC32MZ_PREFETCH_K1BASE+PIC32MZ_PREFETCH_PRECON_OFFSET)
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#define PIC32MZ_PREFETCH_PRESTAT (PIC32MZ_PREFETCH_K1BASE+PIC32MZ_PREFETCH_PRESTAT_OFFSET)
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#define PIC32MZ_PRECON (PIC32MZ_PREFETCH_K1BASE+PIC32MZ_PRECON_OFFSET)
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#define PIC32MZ_PRESTAT (PIC32MZ_PREFETCH_K1BASE+PIC32MZ_PRESTAT_OFFSET)
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/* Prefetch register bit field definitions **************************************************/
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/* Prefetch module control register */
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#define PREFETCH_PRECON_PFMWS_SHIFT (0) /* Bits 0-2: PFM Access Time */
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#define PREFETCH_PRECON_PFMWS_MASK (7 << PREFETCH_PRECON_PFMWS_SHIFT)
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# define PREFETCH_PRECON_PFMWS(n) ((uint32_t)(n) << PREFETCH_PRECON_PFMWS_SHIFT) /* n wait states, n=0..7 */
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#define PREFETCH_PRECON_PREFEN_SHIFT (4) /* Bit 4-5: Predictive Prefetch Enable */
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#define PREFETCH_PRECON_PREFEN_MASK (3 << PREFETCH_PRECON_PREFEN_SHIFT)
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# define PREFETCH_PRECON_PREFEN_DISABLE (0 << PREFETCH_PRECON_PREFEN_SHIFT) /* Disable predictive prefetch */
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# define PREFETCH_PRECON_PREFEN_CPUI (1 << PREFETCH_PRECON_PREFEN_SHIFT) /* Predictive prefetch CPU instructions */
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# define PREFETCH_PRECON_PREFEN_CPUID (2 << PREFETCH_PRECON_PREFEN_SHIFT) /* Predictive prefetch CPU instructions and data */
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# define PREFETCH_PRECON_PREFEN_ANY (3 << PREFETCH_PRECON_PREFEN_SHIFT) /* Predictive prefetch any address */
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#define PREFETCH_PRECON_PFMSECEN (1 << 26) /* Bit 26: Flash SEC Interrupt Enable */
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#define PRECON_PFMWS_SHIFT (0) /* Bits 0-2: PFM Access Time */
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#define PRECON_PFMWS_MASK (7 << PRECON_PFMWS_SHIFT)
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# define PRECON_PFMWS(n) ((uint32_t)(n) << PRECON_PFMWS_SHIFT) /* n wait states, n=0..7 */
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#define PRECON_PREFEN_SHIFT (4) /* Bit 4-5: Predictive Prefetch Enable */
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#define PRECON_PREFEN_MASK (3 << PRECON_PREFEN_SHIFT)
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# define PRECON_PREFEN_DISABLE (0 << PRECON_PREFEN_SHIFT) /* Disable predictive prefetch */
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# define PRECON_PREFEN_CPUI (1 << PRECON_PREFEN_SHIFT) /* Predictive prefetch CPU instructions */
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# define PRECON_PREFEN_CPUID (2 << PRECON_PREFEN_SHIFT) /* Predictive prefetch CPU instructions and data */
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# define PRECON_PREFEN_ANY (3 << PRECON_PREFEN_SHIFT) /* Predictive prefetch any address */
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#define PRECON_PFMSECEN (1 << 26) /* Bit 26: Flash SEC Interrupt Enable */
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/* Prefetch module status register */
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#define PREFETCH_PRESTAT_PFMSECCNT_SHIFT (0) /* Bits 0-7: Flash SEC Count bits */
|
||||
#define PREFETCH_PRESTAT_PFMSECCNT_MASK (0xff << PREFETCH_PRESTAT_PFMSECCNT_SHIFT)
|
||||
#define PREFETCH_PRESTAT_PFMSEC (1 << 26) /* Bit 26: Flash Single-bit Error Corrected Status */
|
||||
#define PREFETCH_PRESTAT_PFMDED (1 << 27) /* Bit 27: Flash Double-bit Error Detected Status */
|
||||
#define PRESTAT_PFMSECCNT_SHIFT (0) /* Bits 0-7: Flash SEC Count bits */
|
||||
#define PRESTAT_PFMSECCNT_MASK (0xff << PRESTAT_PFMSECCNT_SHIFT)
|
||||
#define PRESTAT_PFMSEC (1 << 26) /* Bit 26: Flash Single-bit Error Corrected Status */
|
||||
#define PRESTAT_PFMDED (1 << 27) /* Bit 27: Flash Double-bit Error Detected Status */
|
||||
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_PREFETCH_H */
|
||||
|
||||
@ -189,6 +189,9 @@
|
||||
|
||||
/* System key register: 32-bit key value */
|
||||
|
||||
#define UNLOCK_SYSKEY_0 (0xaa996655ul)
|
||||
#define UNLOCK_SYSKEY_1 (0x556699aaul)
|
||||
|
||||
/* External bus interface address pin configuration register */
|
||||
|
||||
#define CFGEBIA_EBIA0N_SHIFT (0) /* Bits 0-23: EBI address pin 0 enable */
|
||||
|
||||
@ -47,7 +47,9 @@
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip/pic32mz-features.h"
|
||||
#include "chip/pic32mz-prefetch.h"
|
||||
#include "chip/pic32mz-osc.h"
|
||||
|
||||
#include "pic32mz-lowconsole.h"
|
||||
#include "pic32mz-lowinit.h"
|
||||
@ -57,9 +59,10 @@
|
||||
****************************************************************************/
|
||||
/* Maximum Frequencies ******************************************************/
|
||||
|
||||
#define MAX_FLASH_ECC_HZ 66000000 /* Maximum FLASH speed (Hz) with ECC */
|
||||
#define MAX_FLASH_NOECC_HZ 83000000 /* Maximum FLASH speed (Hz) without ECC */
|
||||
#define MAX_PBCLOCK 80000000 /* Max peripheral bus speed (Hz) */
|
||||
#define MAX_FLASH_ECC_HZ 66000000 /* Maximum FLASH speed (Hz) with ECC */
|
||||
#define MAX_FLASH_NOECC_HZ 83000000 /* Maximum FLASH speed (Hz) without ECC */
|
||||
#define MAX_PBCLK 100000000 /* Max peripheral bus speed (Hz) */
|
||||
#define MAX_PBCLK7 200000000 /* Max peripheral bus speed (Hz) for PBCLK7 */
|
||||
|
||||
/* Sanity checks ************************************************************/
|
||||
|
||||
@ -70,13 +73,90 @@
|
||||
# error "Bad BOARD_CPU_CLOCK calculcation in board.h"
|
||||
#endif
|
||||
|
||||
#define CALC_PBCLOCK (CALC_SYSCLOCK / BOARD_PBDIV)
|
||||
#if CALC_PBCLOCK != BOARD_PBCLOCK
|
||||
# error "Bad BOARD_PBCLOCK calculcation in board.h"
|
||||
#define CALC_PBCLK1 (CALC_SYSCLOCK / BOARD_PB1DIV)
|
||||
#if CALC_PBCLK1 != BOARD_PBCLK1
|
||||
# error "Bad BOARD_PBCLK1 calculcation in board.h"
|
||||
#endif
|
||||
|
||||
#if CALC_PBCLOCK > MAX_PBCLOCK
|
||||
# error "PBCLOCK exceeds maximum value"
|
||||
#if CALC_PBCLK1 > MAX_PBCLK
|
||||
# error "PBCLK1 exceeds maximum value"
|
||||
#endif
|
||||
|
||||
#ifdef BOARD_PBCLK2_ENABLE
|
||||
# define CALC_PBCLK2 (CALC_SYSCLOCK / BOARD_PB2DIV)
|
||||
# if CALC_PBCLK2 != BOARD_PBCLK2
|
||||
# error "Bad BOARD_PBCLK2 calculcation in board.h"
|
||||
# endif
|
||||
|
||||
# if CALC_PBCLK2 > MAX_PBCLK
|
||||
# error "PBCLK2 exceeds maximum value"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef BOARD_PBCLK3_ENABLE
|
||||
# define CALC_PBCLK3 (CALC_SYSCLOCK / BOARD_PB3DIV)
|
||||
# if CALC_PBCLK3 != BOARD_PBCLK3
|
||||
# error "Bad BOARD_PBCLK3 calculcation in board.h"
|
||||
# endif
|
||||
|
||||
# if CALC_PBCLK3 > MAX_PBCLK
|
||||
# error "PBCLK3 exceeds maximum value"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef BOARD_PBCLK4_ENABLE
|
||||
# define CALC_PBCLK4 (CALC_SYSCLOCK / BOARD_PB4DIV)
|
||||
# if CALC_PBCLK4 != BOARD_PBCLK4
|
||||
# error "Bad BOARD_PBCLK4 calculcation in board.h"
|
||||
# endif
|
||||
|
||||
# if CALC_PBCLK4 > MAX_PBCLK
|
||||
# error "PBCLK4 exceeds maximum value"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef BOARD_PBCLK5_ENABLE
|
||||
# define CALC_PBCLK5 (CALC_SYSCLOCK / BOARD_PB5DIV)
|
||||
# if CALC_PBCLK5 != BOARD_PBCLK5
|
||||
# error "Bad BOARD_PBCLK5 calculcation in board.h"
|
||||
# endif
|
||||
|
||||
# if CALC_PBCLK5 > MAX_PBCLK
|
||||
# error "PBCLK5 exceeds maximum value"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef BOARD_PBCLK6_ENABLE
|
||||
# define CALC_PBCLK6 (CALC_SYSCLOCK / BOARD_PB6DIV)
|
||||
# if CALC_PBCLK6 != BOARD_PBCLK6
|
||||
# error "Bad BOARD_PBCLK6 calculcation in board.h"
|
||||
# endif
|
||||
|
||||
# if CALC_PBCLK6 > MAX_PBCLK
|
||||
# error "PBCLK6 exceeds maximum value"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef BOARD_PBCLK7_ENABLE
|
||||
# define CALC_PBCLK7 (CALC_SYSCLOCK / BOARD_PB7DIV)
|
||||
# if CALC_PBCLK7 != BOARD_PBCLK7
|
||||
# error "Bad BOARD_PBCLK7 calculcation in board.h"
|
||||
# endif
|
||||
|
||||
# if CALC_PBCLK7 > MAX_PBCLK7
|
||||
# error "PBCLK7 exceeds maximum value"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef BOARD_PBCLK8_ENABLE
|
||||
# define CALC_PBCLK8 (CALC_SYSCLOCK / BOARD_PB8DIV)
|
||||
# if CALC_PBCLK8 != BOARD_PBCLK8
|
||||
# error "Bad BOARD_PBCLK8 calculcation in board.h"
|
||||
# endif
|
||||
|
||||
# if CALC_PBCLK8 > MAX_PBCLK
|
||||
# error "PBCLK8 exceeds maximum value"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
@ -118,7 +198,6 @@ static inline void pic32mz_prefetch(void)
|
||||
unsigned int nwaits;
|
||||
unsigned int residual;
|
||||
uint32_t regval;
|
||||
|
||||
|
||||
/* Configure pre-fetch cache FLASH wait states (assuming ECC is enabled) */
|
||||
|
||||
@ -137,8 +216,8 @@ static inline void pic32mz_prefetch(void)
|
||||
* data.
|
||||
*/
|
||||
|
||||
regval = (PREFETCH_PRECON_PREFEN_CPUID | PREFETCH_PRECON_PFMWS(nwaits));
|
||||
putreg32(regval, PIC32MZ_PREFETCH_PRECON);
|
||||
regval = (PRECON_PREFEN_CPUID | PRECON_PFMWS(nwaits));
|
||||
putreg32(regval, PIC32MZ_PRECON);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -166,6 +245,123 @@ static inline void pic32mz_k0cache(void)
|
||||
UNUSED(regval);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pic32mz_pbclk
|
||||
*
|
||||
* Description:
|
||||
* Configure peripheral bus clocking
|
||||
*
|
||||
* Assumptions:
|
||||
* Interrupts are disabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void pic32mz_pbclk(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Perform the unlock sequence */
|
||||
|
||||
putreg32(UNLOCK_SYSKEY_0, PIC32MZ_SYSKEY);
|
||||
putreg32(UNLOCK_SYSKEY_1, PIC32MZ_SYSKEY);
|
||||
|
||||
/* PBCLK1
|
||||
* Peripherals: OSC2 pin
|
||||
*
|
||||
* NOTES:
|
||||
* - PBCLK1 is used by system modules and cannot be turned off
|
||||
* - PBCLK1 divided by 2 is available on the OSC2 pin in certain clock
|
||||
* modes.
|
||||
*/
|
||||
|
||||
regval = (PBDIV_ON | PBDIV(BOARD_PB1DIV));
|
||||
putreg32(regval, PIC32MZ_PB1DIV);
|
||||
|
||||
/* PBCLK2
|
||||
* Peripherals: PMP, I2C, UART, SPI
|
||||
*/
|
||||
|
||||
#ifdef BOARD_PBCLK2_ENABLE
|
||||
regval = (PBDIV_ON | PBDIV(BOARD_PB2DIV));
|
||||
#else
|
||||
regval = 0;
|
||||
#endif
|
||||
putreg32(regval, PIC32MZ_PB2DIV);
|
||||
|
||||
/* PBCLK3
|
||||
* Peripherals: ADC, Comparator, Timers, Output Compare, Input Compare
|
||||
*
|
||||
* NOTES:
|
||||
* - Timer 1 uses SOSC
|
||||
*/
|
||||
|
||||
#ifdef BOARD_PBCLK3_ENABLE
|
||||
regval = (PBDIV_ON | PBDIV(BOARD_PB3DIV));
|
||||
#else
|
||||
regval = 0;
|
||||
#endif
|
||||
putreg32(regval, PIC32MZ_PB3DIV);
|
||||
|
||||
/* PBCLK4
|
||||
* Peripherals: Ports
|
||||
*/
|
||||
|
||||
#ifdef BOARD_PBCLK4_ENABLE
|
||||
regval = (PBDIV_ON | PBDIV(BOARD_PB4DIV));
|
||||
#else
|
||||
regval = 0;
|
||||
#endif
|
||||
putreg32(regval, PIC32MZ_PB4DIV);
|
||||
|
||||
/* PBCLK5
|
||||
* Peripherals: Flash, Crypto, RND, USB, CAN, Ethernet, SQI
|
||||
*
|
||||
* NOTES:
|
||||
* - PBCLK5 is used to fetch data from/to the Flash Controller, while the
|
||||
* FRC clock is used for programming
|
||||
*/
|
||||
|
||||
#ifdef BOARD_PBCLK5_ENABLE
|
||||
regval = (PBDIV_ON | PBDIV(BOARD_PB5DIV));
|
||||
#else
|
||||
regval = 0;
|
||||
#endif
|
||||
putreg32(regval, PIC32MZ_PB5DIV);
|
||||
|
||||
/* PBCLK6
|
||||
* Peripherals:
|
||||
*/
|
||||
|
||||
#ifdef BOARD_PBCLK6_ENABLE
|
||||
regval = (PBDIV_ON | PBDIV(BOARD_PB6DIV));
|
||||
#else
|
||||
regval = 0;
|
||||
#endif
|
||||
putreg32(regval, PIC32MZ_PB6DIV);
|
||||
|
||||
/* PBCLK7
|
||||
* Peripherals: CPU, Deadman timer
|
||||
*/
|
||||
|
||||
#ifdef BOARD_PBCLK7_ENABLE
|
||||
regval = (PBDIV_ON | PBDIV(BOARD_PB7DIV));
|
||||
#else
|
||||
regval = 0;
|
||||
#endif
|
||||
putreg32(regval, PIC32MZ_PB7DIV);
|
||||
|
||||
/* PBCLK8
|
||||
* Peripherals: EBI
|
||||
*/
|
||||
|
||||
#ifdef BOARD_PBCLK8_ENABLE
|
||||
regval = (PBDIV_ON | PBDIV(BOARD_PB8DIV));
|
||||
#else
|
||||
regval = 0;
|
||||
#endif
|
||||
putreg32(regval, PIC32MZ_PB8DIV);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
@ -191,6 +387,8 @@ void pic32mz_lowinit(void)
|
||||
|
||||
pic32mz_k0cache();;
|
||||
|
||||
/* Configure peripheral clocking */
|
||||
|
||||
/* Initialize a console (probably a serial console) */
|
||||
|
||||
pic32mz_consoleinit();
|
||||
|
||||
@ -73,6 +73,72 @@
|
||||
|
||||
#define BOARD_CPU_CLOCK 200000000 /* CPU clock: 200MHz = (24MHz / 3) * 50 / 2) */
|
||||
|
||||
/* Peripheral clocks */
|
||||
/* PBCLK1
|
||||
* Peripherals: OSC2 pin
|
||||
*
|
||||
* NOTES:
|
||||
* - PBCLK1 is used by system modules and cannot be turned off
|
||||
* - PBCLK1 divided by 2 is available on the OSC2 pin in certain clock
|
||||
* modes.
|
||||
*/
|
||||
|
||||
#define BOARD_PB1DIV 5 /* Divider = 5 */
|
||||
#define BOARD_PBCLK1 40000000 /* PBCLK1 frequency = 200MHz/5 = 40MHz */
|
||||
|
||||
/* PBCLK2
|
||||
* Peripherals: PMP, I2C, UART, SPI
|
||||
*/
|
||||
|
||||
#define BOARD_PBCLK2_ENABLE 1 /* Enable PBCLK2 */
|
||||
#define BOARD_PB2DIV 5 /* Divider = 5 */
|
||||
#define BOARD_PBCLK2 40000000 /* PBCLK2 frequency = 200MHz/5 = 40MHz */
|
||||
|
||||
/* PBCLK3
|
||||
* Peripherals: ADC, Comparator, Timers, Output Compare, Input Compare
|
||||
*
|
||||
* NOTES:
|
||||
* - Timer 1 uses SOSC
|
||||
*/
|
||||
|
||||
#undef BOARD_PBCLK3_ENABLE
|
||||
|
||||
/* PBCLK4
|
||||
* Peripherals: Ports
|
||||
*/
|
||||
|
||||
#define BOARD_PBCLK4_ENABLE 1 /* Enable PBCLK4 */
|
||||
#define BOARD_PB4DIV 2 /* Divider = 2 */
|
||||
#define BOARD_PBCLK4 100000000 /* PBCLK4 frequency = 200MHz/2 = 100MHz */
|
||||
|
||||
/* PBCLK5
|
||||
* Peripherals: Flash, Crypto, RND, USB, CAN, Ethernet, SQI
|
||||
*
|
||||
* NOTES:
|
||||
* - PBCLK5 is used to fetch data from/to the Flash Controller, while the
|
||||
* FRC clock is used for programming
|
||||
*/
|
||||
|
||||
#undef BOARD_PBCLK5_ENABLE
|
||||
|
||||
/* PBCLK6
|
||||
* Peripherals:
|
||||
*/
|
||||
|
||||
#undef BOARD_PBCLK6_ENABLE
|
||||
|
||||
/* PBCLK7
|
||||
* Peripherals: CPU, Deadman timer
|
||||
*/
|
||||
|
||||
#undef BOARD_PBCLK7_ENABLE
|
||||
|
||||
/* PBCLK8
|
||||
* Peripherals: EBI
|
||||
*/
|
||||
|
||||
#undef BOARD_PBCLK8_ENABLE
|
||||
|
||||
/* Watchdog pre-scaler (re-visit) */
|
||||
|
||||
#define BOARD_WD_PRESCALER 8 /* Watchdog pre-scaler */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user