SAMA5 LCDC: Corrections from first debug sessions. Still a way to go
This commit is contained in:
Gregory Nutt
parent
3b6e63199a
commit
ff64ccb539
@ -7,6 +7,44 @@ if ARCH_CHIP_SAMA5
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comment "ATSAMA5 Configuration Options"
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# Chip Capabilities
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config SAMA5_HAVE_UART0
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bool
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default n
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config SAMA5_HAVE_UART1
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bool
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default n
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config SAMA5_HAVE_CAN0
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bool
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default n
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config SAMA5_HAVE_CAN1
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bool
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default n
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config SAMA5_HAVE_LCDC
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bool
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default n
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config SAMA5_HAVE_GMAC
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bool
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default n
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config SAMA5_HAVE_EMAC
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bool
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default n
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config SAMA5_HAVE_HSMCI2
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bool
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default n
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config SAMA5_HAVE_TC1
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bool
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default n
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choice
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prompt "Atmel AT91SAMA5 Chip Selection"
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default ARCH_CHIP_ATSAMA5D33
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@ -15,7 +53,10 @@ config ARCH_CHIP_ATSAMA5D31
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bool "Atmel ATSAMA5D31"
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select ARCH_CHIP_SAMA5D3
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select SAMA5_HAVE_EMAC
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select SAMA5_HAVE_HSMCI2
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select SAMA5_HAVE_LCDC
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select SAMA5_HAVE_UART0
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select SAMA5_HAVE_UART1
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config ARCH_CHIP_ATSAMA5D33
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bool "Atmel ATSAMA5D33"
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@ -27,13 +68,22 @@ config ARCH_CHIP_ATSAMA5D34
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bool "Atmel ATSAMA5D34"
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select ARCH_CHIP_SAMA5D3
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select SAMA5_HAVE_GMAC
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select SAMA5_HAVE_HSMCI2
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select SAMA5_HAVE_LCDC
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select SAMA5_HAVE_CAN0
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select SAMA5_HAVE_CAN1
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config ARCH_CHIP_ATSAMA5D35
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bool "Atmel ATSAMA5D35"
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select ARCH_CHIP_SAMA5D3
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select SAMA5_HAVE_EMAC
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select SAMA5_HAVE_GMAC
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select SAMA5_HAVE_HSMCI2
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select SAMA5_HAVE_UART0
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select SAMA5_HAVE_UART1
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select SAMA5_HAVE_CAN0
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select SAMA5_HAVE_CAN1
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select SAMA5_HAVE_TC1
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endchoice # Atmel AT91SAMA5 Chip Selection
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@ -62,11 +112,13 @@ config SAMA5_SMD
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config SAMA5_UART0
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bool "UART 0"
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default y
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depends on SAMA5_HAVE_UART0
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select ARCH_HAVE_UART0
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config SAMA5_UART1
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bool "UART 1"
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default n
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depends on SAMA5_HAVE_UART1
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select ARCH_HAVE_UART1
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config SAMA5_USART0
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@ -114,6 +166,7 @@ config SAMA5_HSMCI1
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config SAMA5_HSMCI2
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bool "High Speed Multimedia Card Interface 2 (HSMCI2)"
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default n
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depends on SAMA5_HAVE_HSMCI2
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select ARCH_HAVE_SDIO
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config SAMA5_SPI0
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@ -130,6 +183,7 @@ config SAMA5_TC0
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config SAMA5_TC1
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bool "Timer Counter 1 (ch. 3, 4, 5) (TC1)"
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depends on SAMA5_HAVE_TC1
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default n
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config SAMA5_PWM
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@ -257,9 +311,6 @@ config SAMA5_PIOE_IRQ
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endif # PIO_IRQ
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config SAMA5_HAVE_LCDC
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bool
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if SAMA5_LCDC
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menu "LCDC Configuration"
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@ -303,14 +354,6 @@ endif # SAMA5_LCDC_FBFIXED
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comment "Base layer configuration"
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config SAMA5_LCDC_BASE_HEIGHT
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int "Layer height (rows)"
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default 480
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config SAMA5_LCDC_BASE_WIDTH
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int "Layer width (pixels)"
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default 800
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choice
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prompt "Base layer rotation"
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default SAMA5_LCDC_BASE_ROT0
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@ -736,14 +779,6 @@ config SAMA5_LCDC_REGDEBUG
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endmenu # LCDC configuration
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endif # SAMA5_LCDC
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config SAMA5_HAVE_GMAC
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bool
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default n
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config SAMA5_HAVE_EMAC
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bool
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default n
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if SAMA5_GMAC
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menu "GMAC device driver options"
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@ -501,12 +501,12 @@
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/* LCD Controller Configuration Register 4 */
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#define LCDC_LCDCFG4_RPF_SHIFT (0) /* Bits 0-8: Number of Active Row Per Frame */
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#define LCDC_LCDCFG4_RPF_MASK (0x1ff << LCDC_LCDCFG4_RPF_SHIFT)
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# define LCDC_LCDCFG4_RPF(n) ((uint32_t)(n) << LCDC_LCDCFG4_RPF_SHIFT)
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#define LCDC_LCDCFG4_PPL_SHIFT (16) /* Bits 16-24: Number of Pixels Per Line */
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#define LCDC_LCDCFG4_PPL_MASK (0x1ff << LCDC_LCDCFG4_PPL_SHIFT)
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#define LCDC_LCDCFG4_PPL_SHIFT (0) /* Bits 0-10: Number of Pixels Per Line */
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#define LCDC_LCDCFG4_PPL_MASK (0x7ff << LCDC_LCDCFG4_PPL_SHIFT)
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# define LCDC_LCDCFG4_PPL(n) ((uint32_t)(n) << LCDC_LCDCFG4_PPL_SHIFT)
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#define LCDC_LCDCFG4_RPF_SHIFT (16) /* Bits 16-26: Number of Active Row Per Frame */
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#define LCDC_LCDCFG4_RPF_MASK (0x7ff << LCDC_LCDCFG4_RPF_SHIFT)
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# define LCDC_LCDCFG4_RPF(n) ((uint32_t)(n) << LCDC_LCDCFG4_RPF_SHIFT)
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/* LCD Controller Configuration Register 5 */
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@ -672,15 +672,15 @@
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/* Base Configuration register 2 (32-bit value) */
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/* Base Configuration register 3 */
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#define LCDC_BASECFG3_RDEF_SHIFT (0) /* Bits 0-7: R Default */
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#define LCDC_BASECFG3_RDEF_MASK (0xff << LCDC_BASECFG3_RDEF_SHIFT)
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# define LCDC_BASECFG3_RDEF(n) ((uint32_t)(n) << LCDC_BASECFG3_RDEF_SHIFT)
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#define LCDC_BASECFG3_BDEF_SHIFT (0) /* Bits 0-7: B Default */
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#define LCDC_BASECFG3_BDEF_MASK (0xff << LCDC_BASECFG3_BDEF_SHIFT)
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# define LCDC_BASECFG3_BDEF(n) ((uint32_t)(n) << LCDC_BASECFG3_BDEF_SHIFT)
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#define LCDC_BASECFG3_GDEF_SHIFT (8) /* Bits 8-15: G Default */
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#define LCDC_BASECFG3_GDEF_MASK (0xff << LCDC_BASECFG3_GDEF_SHIFT)
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# define LCDC_BASECFG3_GDEF(n) ((uint32_t)(n) << LCDC_BASECFG3_GDEF_SHIFT)
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#define LCDC_BASECFG3_BDEF_SHIFT (16) /* Bits 16-23: B Default */
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#define LCDC_BASECFG3_BDEF_MASK (0xff << LCDC_BASECFG3_BDEF_SHIFT)
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# define LCDC_BASECFG3_BDEF(n) ((uint32_t)(n) << LCDC_BASECFG3_BDEF_SHIFT)
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#define LCDC_BASECFG3_RDEF_SHIFT (16) /* Bits 16-23: R Default */
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#define LCDC_BASECFG3_RDEF_MASK (0xff << LCDC_BASECFG3_RDEF_SHIFT)
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# define LCDC_BASECFG3_RDEF(n) ((uint32_t)(n) << LCDC_BASECFG3_RDEF_SHIFT)
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/* Base Configuration register 4 */
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@ -812,39 +812,39 @@
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/* Overlay 1 Configuration 6 Register */
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#define LCDC_OVR1CFG6_RDEF_SHIFT (0) /* Bits 0-7: R Default */
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#define LCDC_OVR1CFG6_RDEF_MASK (0xff << LCDC_OVR1CFG6_RDEF_SHIFT)
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# define LCDC_OVR1CFG6_RDEF(n) ((uint32_t)(n) << LCDC_OVR1CFG6_RDEF_SHIFT)
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#define LCDC_OVR1CFG6_BDEF_SHIFT (0) /* Bits 0-7: B Default */
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#define LCDC_OVR1CFG6_BDEF_MASK (0xff << LCDC_OVR1CFG6_BDEF_SHIFT)
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# define LCDC_OVR1CFG6_BDEF(n) ((uint32_t)(n) << LCDC_OVR1CFG6_BDEF_SHIFT)
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#define LCDC_OVR1CFG6_GDEF_SHIFT (8) /* Bits 8-15: G Default */
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#define LCDC_OVR1CFG6_GDEF_MASK (0xff << LCDC_OVR1CFG6_GDEF_SHIFT)
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# define LCDC_OVR1CFG6_GDEF(n) ((uint32_t)(n) << LCDC_OVR1CFG6_GDEF_SHIFT)
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#define LCDC_OVR1CFG6_BDEF_SHIFT (16) /* Bits 16-23: B Default */
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#define LCDC_OVR1CFG6_BDEF_MASK (0xff << LCDC_OVR1CFG6_BDEF_SHIFT)
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# define LCDC_OVR1CFG6_BDEF(n) ((uint32_t)(n) << LCDC_OVR1CFG6_BDEF_SHIFT)
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#define LCDC_OVR1CFG6_RDEF_SHIFT (16) /* Bits 16-23: R Default */
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#define LCDC_OVR1CFG6_RDEF_MASK (0xff << LCDC_OVR1CFG6_RDEF_SHIFT)
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# define LCDC_OVR1CFG6_RDEF(n) ((uint32_t)(n) << LCDC_OVR1CFG6_RDEF_SHIFT)
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/* Overlay 1 Configuration 7 Register */
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#define LCDC_OVR1CFG7_RKEY_SHIFT (0) /* Bits 0-7: R Color Component Chroma Key */
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#define LCDC_OVR1CFG7_RKEY_MASK (0xff << LCDC_OVR1CFG7_RKEY_SHIFT)
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# define LCDC_OVR1CFG7_RKEY(n) ((uint32_t)(n) << LCDC_OVR1CFG7_RKEY_SHIFT)
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#define LCDC_OVR1CFG7_BKEY_SHIFT (0) /* Bits 0-7: B Color Component Chroma Key */
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#define LCDC_OVR1CFG7_BKEY_MASK (0xff << LCDC_OVR1CFG7_BKEY_SHIFT)
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# define LCDC_OVR1CFG7_BKEY(n) ((uint32_t)(n) << LCDC_OVR1CFG7_BKEY_SHIFT)
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#define LCDC_OVR1CFG7_GKEY_SHIFT (8) /* Bits 8-15: G Color Component Chroma Key */
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#define LCDC_OVR1CFG7_GKEY_MASK (0xff << LCDC_OVR1CFG7_GKEY_SHIFT)
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# define LCDC_OVR1CFG7_GKEY(n) ((uint32_t)(n) << LCDC_OVR1CFG7_GKEY_SHIFT)
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#define LCDC_OVR1CFG7_BKEY_SHIFT (16) /* Bits 16-23: B Color Component Chroma Key */
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#define LCDC_OVR1CFG7_BKEY_MASK (0xff << LCDC_OVR1CFG7_BKEY_SHIFT)
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# define LCDC_OVR1CFG7_BKEY(n) ((uint32_t)(n) << LCDC_OVR1CFG7_BKEY_SHIFT)
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#define LCDC_OVR1CFG7_RKEY_SHIFT (16) /* Bits 16-23: R Color Component Chroma Key */
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#define LCDC_OVR1CFG7_RKEY_MASK (0xff << LCDC_OVR1CFG7_RKEY_SHIFT)
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# define LCDC_OVR1CFG7_RKEY(n) ((uint32_t)(n) << LCDC_OVR1CFG7_RKEY_SHIFT)
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/* Overlay 1 Configuration 8 Register */
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#define LCDC_OVR1CFG8_RMASK_SHIFT (0) /* Bits 0-7: R Color Component Chroma Key Mask */
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#define LCDC_OVR1CFG8_RMASK_MASK (0xff << LCDC_OVR1CFG8_RMASK_SHIFT)
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# define LCDC_OVR1CFG8_RMASK(n) ((uint32_t)(n) << LCDC_OVR1CFG8_RMASK_SHIFT)
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#define LCDC_OVR1CFG8_BMASK_SHIFT (0) /* Bits 0-7: B Color Component Chroma Key Mask */
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#define LCDC_OVR1CFG8_BMASK_MASK (0xff << LCDC_OVR1CFG8_BMASK_SHIFT)
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# define LCDC_OVR1CFG8_BMASK(n) ((uint32_t)(n) << LCDC_OVR1CFG8_BMASK_SHIFT)
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#define LCDC_OVR1CFG8_GMASK_SHIFT (8) /* Bits 8-15: G Color Component Chroma Key Mask */
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#define LCDC_OVR1CFG8_GMASK_MASK (0xff << LCDC_OVR1CFG8_GMASK_SHIFT)
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# define LCDC_OVR1CFG8_GMASK(n) ((uint32_t)(n) << LCDC_OVR1CFG8_GMASK_SHIFT)
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#define LCDC_OVR1CFG8_BMASK_SHIFT (16) /* Bits 16-23: B Color Component Chroma Key Mask */
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#define LCDC_OVR1CFG8_BMASK_MASK (0xff << LCDC_OVR1CFG8_BMASK_SHIFT)
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# define LCDC_OVR1CFG8_BMASK(n) ((uint32_t)(n) << LCDC_OVR1CFG8_BMASK_SHIFT)
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#define LCDC_OVR1CFG8_RMASK_SHIFT (16) /* Bits 16-23: R Color Component Chroma Key Mask */
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#define LCDC_OVR1CFG8_RMASK_MASK (0xff << LCDC_OVR1CFG8_RMASK_SHIFT)
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# define LCDC_OVR1CFG8_RMASK(n) ((uint32_t)(n) << LCDC_OVR1CFG8_RMASK_SHIFT)
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/* Overlay 1 Configuration 9 Register */
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@ -968,39 +968,39 @@
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/* Overlay 2 Configuration 6 Register */
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#define LCDC_OVR2CFG6_RDEF_SHIFT (0) /* Bits 0-7: R Default */
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#define LCDC_OVR2CFG6_RDEF_MASK (0xff << LCDC_OVR2CFG6_RDEF_SHIFT)
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# define LCDC_OVR2CFG6_RDEF(n) ((uint32_t)(n) << LCDC_OVR2CFG6_RDEF_SHIFT)
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#define LCDC_OVR2CFG6_BDEF_SHIFT (0) /* Bits 0-7: B Default */
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#define LCDC_OVR2CFG6_BDEF_MASK (0xff << LCDC_OVR2CFG6_BDEF_SHIFT)
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# define LCDC_OVR2CFG6_BDEF(n) ((uint32_t)(n) << LCDC_OVR2CFG6_BDEF_SHIFT)
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#define LCDC_OVR2CFG6_GDEF_SHIFT (8) /* Bits 8-15: G Default */
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#define LCDC_OVR2CFG6_GDEF_MASK (0xff << LCDC_OVR2CFG6_GDEF_SHIFT)
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# define LCDC_OVR2CFG6_GDEF(n) ((uint32_t)(n) << LCDC_OVR2CFG6_GDEF_SHIFT)
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#define LCDC_OVR2CFG6_BDEF_SHIFT (16) /* Bits 16-23: B Default */
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#define LCDC_OVR2CFG6_BDEF_MASK (0xff << LCDC_OVR2CFG6_BDEF_SHIFT)
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# define LCDC_OVR2CFG6_BDEF(n) ((uint32_t)(n) << LCDC_OVR2CFG6_BDEF_SHIFT)
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#define LCDC_OVR2CFG6_RDEF_SHIFT (16) /* Bits 16-23: R Default */
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#define LCDC_OVR2CFG6_RDEF_MASK (0xff << LCDC_OVR2CFG6_RDEF_SHIFT)
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# define LCDC_OVR2CFG6_RDEF(n) ((uint32_t)(n) << LCDC_OVR2CFG6_RDEF_SHIFT)
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/* Overlay 2 Configuration 7 Register */
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#define LCDC_OVR2CFG7_RKEY_SHIFT (0) /* Bits 0-7: R Color Component Chroma Key */
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#define LCDC_OVR2CFG7_RKEY_MASK (0xff << LCDC_OVR2CFG7_RKEY_SHIFT)
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# define LCDC_OVR2CFG7_RKEY(n) ((uint32_t)(n) << LCDC_OVR2CFG7_RKEY_SHIFT)
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#define LCDC_OVR2CFG7_BKEY_SHIFT (0) /* Bits 0-7: B Color Component Chroma Key */
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#define LCDC_OVR2CFG7_BKEY_MASK (0xff << LCDC_OVR2CFG7_BKEY_SHIFT)
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# define LCDC_OVR2CFG7_BKEY(n) ((uint32_t)(n) << LCDC_OVR2CFG7_BKEY_SHIFT)
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#define LCDC_OVR2CFG7_GKEY_SHIFT (8) /* Bits 8-15: G Color Component Chroma Key */
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#define LCDC_OVR2CFG7_GKEY_MASK (0xff << LCDC_OVR2CFG7_GKEY_SHIFT)
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# define LCDC_OVR2CFG7_GKEY(n) ((uint32_t)(n) << LCDC_OVR2CFG7_GKEY_SHIFT)
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#define LCDC_OVR2CFG7_BKEY_SHIFT (16) /* Bits 16-23: B Color Component Chroma Key */
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#define LCDC_OVR2CFG7_BKEY_MASK (0xff << LCDC_OVR2CFG7_BKEY_SHIFT)
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# define LCDC_OVR2CFG7_BKEY(n) ((uint32_t)(n) << LCDC_OVR2CFG7_BKEY_SHIFT)
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#define LCDC_OVR2CFG7_RKEY_SHIFT (16) /* Bits 16-23: R Color Component Chroma Key */
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#define LCDC_OVR2CFG7_RKEY_MASK (0xff << LCDC_OVR2CFG7_RKEY_SHIFT)
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# define LCDC_OVR2CFG7_RKEY(n) ((uint32_t)(n) << LCDC_OVR2CFG7_RKEY_SHIFT)
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/* Overlay 2 Configuration 8 Register */
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#define LCDC_OVR2CFG8_RMASK_SHIFT (0) /* Bits 0-7: R Color Component Chroma Key Mask */
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#define LCDC_OVR2CFG8_RMASK_MASK (0xff << LCDC_OVR2CFG8_RMASK_SHIFT)
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# define LCDC_OVR2CFG8_RMASK(n) ((uint32_t)(n) << LCDC_OVR2CFG8_RMASK_SHIFT)
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#define LCDC_OVR2CFG8_BMASK_SHIFT (0) /* Bits 0-7: B Color Component Chroma Key Mask */
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#define LCDC_OVR2CFG8_BMASK_MASK (0xff << LCDC_OVR2CFG8_BMASK_SHIFT)
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# define LCDC_OVR2CFG8_BMASK(n) ((uint32_t)(n) << LCDC_OVR2CFG8_BMASK_SHIFT)
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#define LCDC_OVR2CFG8_GMASK_SHIFT (8) /* Bits 8-15: G Color Component Chroma Key Mask */
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#define LCDC_OVR2CFG8_GMASK_MASK (0xff << LCDC_OVR2CFG8_GMASK_SHIFT)
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# define LCDC_OVR2CFG8_GMASK(n) ((uint32_t)(n) << LCDC_OVR2CFG8_GMASK_SHIFT)
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#define LCDC_OVR2CFG8_BMASK_SHIFT (16) /* Bits 16-23: B Color Component Chroma Key Mask */
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#define LCDC_OVR2CFG8_BMASK_MASK (0xff << LCDC_OVR2CFG8_BMASK_SHIFT)
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# define LCDC_OVR2CFG8_BMASK(n) ((uint32_t)(n) << LCDC_OVR2CFG8_BMASK_SHIFT)
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#define LCDC_OVR2CFG8_RMASK_SHIFT (16) /* Bits 16-23: R Color Component Chroma Key Mask */
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#define LCDC_OVR2CFG8_RMASK_MASK (0xff << LCDC_OVR2CFG8_RMASK_SHIFT)
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# define LCDC_OVR2CFG8_RMASK(n) ((uint32_t)(n) << LCDC_OVR2CFG8_RMASK_SHIFT)
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/* Overlay 2 Configuration 9 Register */
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@ -1176,39 +1176,39 @@
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/* High-End Overlay Configuration Register 9 */
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#define LCDC_HEOCFG9_RDEF_SHIFT (0) /* Bits 0-7: R Default */
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#define LCDC_HEOCFG9_RDEF_MASK (0xff << LCDC_HEOCFG9_RDEF_SHIFT)
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# define LCDC_HEOCFG9_RDEF(n) ((uint32_t)(n) << LCDC_HEOCFG9_RDEF_SHIFT)
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#define LCDC_HEOCFG9_BDEF_SHIFT (0) /* Bits 0-7: B Default */
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#define LCDC_HEOCFG9_BDEF_MASK (0xff << LCDC_HEOCFG9_BDEF_SHIFT)
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# define LCDC_HEOCFG9_BDEF(n) ((uint32_t)(n) << LCDC_HEOCFG9_BDEF_SHIFT)
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#define LCDC_HEOCFG9_GDEF_SHIFT (8) /* Bits 8-15: G Default */
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#define LCDC_HEOCFG9_GDEF_MASK (0xff << LCDC_HEOCFG9_GDEF_SHIFT)
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# define LCDC_HEOCFG9_GDEF(n) ((uint32_t)(n) << LCDC_HEOCFG9_GDEF_SHIFT)
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#define LCDC_HEOCFG9_BDEF_SHIFT (16) /* Bits 16-23: B Default */
|
||||
#define LCDC_HEOCFG9_BDEF_MASK (0xff << LCDC_HEOCFG9_BDEF_SHIFT)
|
||||
# define LCDC_HEOCFG9_BDEF(n) ((uint32_t)(n) << LCDC_HEOCFG9_BDEF_SHIFT)
|
||||
#define LCDC_HEOCFG9_RDEF_SHIFT (16) /* Bits 16-23: R Default */
|
||||
#define LCDC_HEOCFG9_RDEF_MASK (0xff << LCDC_HEOCFG9_RDEF_SHIFT)
|
||||
# define LCDC_HEOCFG9_RDEF(n) ((uint32_t)(n) << LCDC_HEOCFG9_RDEF_SHIFT)
|
||||
|
||||
/* High-End Overlay Configuration Register 10 */
|
||||
|
||||
#define LCDC_HEOCFG10_RKEY_SHIFT (0) /* Bits 0-7: R Color Component Chroma Key */
|
||||
#define LCDC_HEOCFG10_RKEY_MASK (0xff << LCDC_HEOCFG10_RKEY_SHIFT)
|
||||
# define LCDC_HEOCFG10_RKEY(n) ((uint32_t)(n) << LCDC_HEOCFG10_RKEY_SHIFT)
|
||||
#define LCDC_HEOCFG10_BKEY_SHIFT (0) /* Bits 0-7: B Color Component Chroma Key */
|
||||
#define LCDC_HEOCFG10_BKEY_MASK (0xff << LCDC_HEOCFG10_BKEY_SHIFT)
|
||||
# define LCDC_HEOCFG10_BKEY(n) ((uint32_t)(n) << LCDC_HEOCFG10_BKEY_SHIFT)
|
||||
#define LCDC_HEOCFG10_GKEY_SHIFT (8) /* Bits 8-15: G Color Component Chroma Key */
|
||||
#define LCDC_HEOCFG10_GKEY_MASK (0xff << LCDC_HEOCFG10_GKEY_SHIFT)
|
||||
# define LCDC_HEOCFG10_GKEY(n) ((uint32_t)(n) << LCDC_HEOCFG10_GKEY_SHIFT)
|
||||
#define LCDC_HEOCFG10_BKEY_SHIFT (16) /* Bits 16-23: B Color Component Chroma Key */
|
||||
#define LCDC_HEOCFG10_BKEY_MASK (0xff << LCDC_HEOCFG10_BKEY_SHIFT)
|
||||
# define LCDC_HEOCFG10_BKEY(n) ((uint32_t)(n) << LCDC_HEOCFG10_BKEY_SHIFT)
|
||||
#define LCDC_HEOCFG10_RKEY_SHIFT (16) /* Bits 16-23: R Color Component Chroma Key */
|
||||
#define LCDC_HEOCFG10_RKEY_MASK (0xff << LCDC_HEOCFG10_RKEY_SHIFT)
|
||||
# define LCDC_HEOCFG10_RKEY(n) ((uint32_t)(n) << LCDC_HEOCFG10_RKEY_SHIFT)
|
||||
|
||||
/* High-End Overlay Configuration Register 11 */
|
||||
|
||||
#define LCDC_HEOCFG11_RMASK_SHIFT (0) /* Bits 0-7: R Color Component Chroma Key Mask */
|
||||
#define LCDC_HEOCFG11_RMASK_MASK (0xff << LCDC_HEOCFG11_RMASK_SHIFT)
|
||||
# define LCDC_HEOCFG11_RMASK(n) ((uint32_t)(n) << LCDC_HEOCFG11_RMASK_SHIFT)
|
||||
#define LCDC_HEOCFG11_BMASK_SHIFT (0) /* Bits 0-7: B Color Component Chroma Key Mask */
|
||||
#define LCDC_HEOCFG11_BMASK_MASK (0xff << LCDC_HEOCFG11_BMASK_SHIFT)
|
||||
# define LCDC_HEOCFG11_BMASK(n) ((uint32_t)(n) << LCDC_HEOCFG11_BMASK_SHIFT)
|
||||
#define LCDC_HEOCFG11_GMASK_SHIFT (8) /* Bits 8-15: G Color Component Chroma Key Mask */
|
||||
#define LCDC_HEOCFG11_GMASK_MASK (0xff << LCDC_HEOCFG11_GMASK_SHIFT)
|
||||
# define LCDC_HEOCFG11_GMASK(n) ((uint32_t)(n) << LCDC_HEOCFG11_GMASK_SHIFT)
|
||||
#define LCDC_HEOCFG11_BMASK_SHIFT (16) /* Bits 16-23: B Color Component Chroma Key Mask */
|
||||
#define LCDC_HEOCFG11_BMASK_MASK (0xff << LCDC_HEOCFG11_BMASK_SHIFT)
|
||||
# define LCDC_HEOCFG11_BMASK(n) ((uint32_t)(n) << LCDC_HEOCFG11_BMASK_SHIFT)
|
||||
#define LCDC_HEOCFG11_RMASK_SHIFT (16) /* Bits 16-23: R Color Component Chroma Key Mask */
|
||||
#define LCDC_HEOCFG11_RMASK_MASK (0xff << LCDC_HEOCFG11_RMASK_SHIFT)
|
||||
# define LCDC_HEOCFG11_RMASK(n) ((uint32_t)(n) << LCDC_HEOCFG11_RMASK_SHIFT)
|
||||
|
||||
/* High-End Overlay Configuration Register 12 */
|
||||
|
||||
@ -1653,39 +1653,39 @@
|
||||
|
||||
/* Hardware Cursor Configuration 6 Register */
|
||||
|
||||
#define LCDC_HCRCFG6_RDEF_SHIFT (0) /* Bits 0-7: R Default */
|
||||
#define LCDC_HCRCFG6_RDEF_MASK (0xff << LCDC_HCRCFG6_RDEF_SHIFT)
|
||||
# define LCDC_HCRCFG6_RDEF(n) ((uint32_t)(n) << LCDC_HCRCFG6_RDEF_SHIFT)
|
||||
#define LCDC_HCRCFG6_BDEF_SHIFT (0) /* Bits 0-7: B Default */
|
||||
#define LCDC_HCRCFG6_BDEF_MASK (0xff << LCDC_HCRCFG6_BDEF_SHIFT)
|
||||
# define LCDC_HCRCFG6_BDEF(n) ((uint32_t)(n) << LCDC_HCRCFG6_BDEF_SHIFT)
|
||||
#define LCDC_HCRCFG6_GDEF_SHIFT (8) /* Bits 8-15: G Default */
|
||||
#define LCDC_HCRCFG6_GDEF_MASK (0xff << LCDC_HCRCFG6_GDEF_SHIFT)
|
||||
# define LCDC_HCRCFG6_GDEF(n) ((uint32_t)(n) << LCDC_HCRCFG6_GDEF_SHIFT)
|
||||
#define LCDC_HCRCFG6_BDEF_SHIFT (16) /* Bits 16-23: B Default */
|
||||
#define LCDC_HCRCFG6_BDEF_MASK (0xff << LCDC_HCRCFG6_BDEF_SHIFT)
|
||||
# define LCDC_HCRCFG6_BDEF(n) ((uint32_t)(n) << LCDC_HCRCFG6_BDEF_SHIFT)
|
||||
#define LCDC_HCRCFG6_RDEF_SHIFT (16) /* Bits 16-23: R Default */
|
||||
#define LCDC_HCRCFG6_RDEF_MASK (0xff << LCDC_HCRCFG6_RDEF_SHIFT)
|
||||
# define LCDC_HCRCFG6_RDEF(n) ((uint32_t)(n) << LCDC_HCRCFG6_RDEF_SHIFT)
|
||||
|
||||
/* Hardware Cursor Configuration 7 Register */
|
||||
|
||||
#define LCDC_HCRCFG7_RKEY_SHIFT (0) /* Bits 0-7: R Color Component Chroma Key */
|
||||
#define LCDC_HCRCFG7_RKEY_MASK (0xff << LCDC_HCRCFG7_RKEY_SHIFT)
|
||||
# define LCDC_HCRCFG7_RKEY(n) ((uint32_t)(n) << LCDC_HCRCFG7_RKEY_SHIFT)
|
||||
#define LCDC_HCRCFG7_BKEY_SHIFT (0) /* Bits 0-7: B Color Component Chroma Key */
|
||||
#define LCDC_HCRCFG7_BKEY_MASK (0xff << LCDC_HCRCFG7_BKEY_SHIFT)
|
||||
# define LCDC_HCRCFG7_BKEY(n) ((uint32_t)(n) << LCDC_HCRCFG7_BKEY_SHIFT)
|
||||
#define LCDC_HCRCFG7_GKEY_SHIFT (8) /* Bits 8-15: G Color Component Chroma Key */
|
||||
#define LCDC_HCRCFG7_GKEY_MASK (0xff << LCDC_HCRCFG7_GKEY_SHIFT)
|
||||
# define LCDC_HCRCFG7_GKEY(n) ((uint32_t)(n) << LCDC_HCRCFG7_GKEY_SHIFT)
|
||||
#define LCDC_HCRCFG7_BKEY_SHIFT (16) /* Bits 16-23: B Color Component Chroma Key */
|
||||
#define LCDC_HCRCFG7_BKEY_MASK (0xff << LCDC_HCRCFG7_BKEY_SHIFT)
|
||||
# define LCDC_HCRCFG7_BKEY(n) ((uint32_t)(n) << LCDC_HCRCFG7_BKEY_SHIFT)
|
||||
#define LCDC_HCRCFG7_RKEY_SHIFT (16) /* Bits 16-23: R Color Component Chroma Key */
|
||||
#define LCDC_HCRCFG7_RKEY_MASK (0xff << LCDC_HCRCFG7_RKEY_SHIFT)
|
||||
# define LCDC_HCRCFG7_RKEY(n) ((uint32_t)(n) << LCDC_HCRCFG7_RKEY_SHIFT)
|
||||
|
||||
/* Hardware Cursor Configuration 8 Register */
|
||||
|
||||
#define LCDC_HCRCFG8_RMASK_SHIFT (0) /* Bits 0-7: R Color Component Chroma Key Mask */
|
||||
#define LCDC_HCRCFG8_RMASK_MASK (0xff << LCDC_HCRCFG8_RMASK_SHIFT)
|
||||
# define LCDC_HCRCFG8_RMASK(n) ((uint32_t)(n) << LCDC_HCRCFG8_RMASK_SHIFT)
|
||||
#define LCDC_HCRCFG8_BMASK_SHIFT (0) /* Bits 0-7: B Color Component Chroma Key Mask */
|
||||
#define LCDC_HCRCFG8_BMASK_MASK (0xff << LCDC_HCRCFG8_BMASK_SHIFT)
|
||||
# define LCDC_HCRCFG8_BMASK(n) ((uint32_t)(n) << LCDC_HCRCFG8_BMASK_SHIFT)
|
||||
#define LCDC_HCRCFG8_GMASK_SHIFT (8) /* Bits 8-15: G Color Component Chroma Key Mask */
|
||||
#define LCDC_HCRCFG8_GMASK_MASK (0xff << LCDC_HCRCFG8_GMASK_SHIFT)
|
||||
# define LCDC_HCRCFG8_GMASK(n) ((uint32_t)(n) << LCDC_HCRCFG8_GMASK_SHIFT)
|
||||
#define LCDC_HCRCFG8_BMASK_SHIFT (16) /* Bits 16-23: B Color Component Chroma Key Mask */
|
||||
#define LCDC_HCRCFG8_BMASK_MASK (0xff << LCDC_HCRCFG8_BMASK_SHIFT)
|
||||
# define LCDC_HCRCFG8_BMASK(n) ((uint32_t)(n) << LCDC_HCRCFG8_BMASK_SHIFT)
|
||||
#define LCDC_HCRCFG8_RMASK_SHIFT (16) /* Bits 16-23: R Color Component Chroma Key Mask */
|
||||
#define LCDC_HCRCFG8_RMASK_MASK (0xff << LCDC_HCRCFG8_RMASK_SHIFT)
|
||||
# define LCDC_HCRCFG8_RMASK(n) ((uint32_t)(n) << LCDC_HCRCFG8_RMASK_SHIFT)
|
||||
|
||||
/* Hardware Cursor Configuration 9 Register */
|
||||
|
||||
|
||||
@ -301,30 +301,38 @@
|
||||
|
||||
/* Framebuffer sizes in bytes */
|
||||
|
||||
#ifndef CONFIG_SAMA5_LCDC_BASE_WIDTH
|
||||
# error CONFIG_SAMA5_LCDC_BASE_WIDTH must be defined
|
||||
#ifndef BOARD_LCD_WIDTH
|
||||
# error BOARD_LCD_WIDTH must be defined in the board.h header file
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SAMA5_LCDC_BASE_HEIGHT
|
||||
# error CONFIG_SAMA5_LCDC_BASE_HEIGHT must be defined
|
||||
#ifndef BOARD_LCD_HEIGHT
|
||||
# error BOARD_LCD_HEIGHT must be defined in the board.h header file
|
||||
#endif
|
||||
|
||||
#if SAMA5_LCDC_BASE_BPP == 16
|
||||
# define SAMA5_BASE_STRIDE ((CONFIG_SAMA5_LCDC_BASE_WIDTH * 16 + 7) / 8)
|
||||
# define SAMA5_BASE_STRIDE ((BOARD_LCD_WIDTH * 16 + 7) / 8)
|
||||
#elif SAMA5_LCDC_BASE_BPP == 24
|
||||
# define SAMA5_BASE_STRIDE ((CONFIG_SAMA5_LCDC_BASE_WIDTH * 24 + 7) / 8)
|
||||
# define SAMA5_BASE_STRIDE ((BOARD_LCD_WIDTH * 24 + 7) / 8)
|
||||
#elif SAMA5_LCDC_BASE_BPP == 32
|
||||
# define SAMA5_BASE_STRIDE ((CONFIG_SAMA5_LCDC_BASE_WIDTH * 32 + 7) / 8)
|
||||
# define SAMA5_BASE_STRIDE ((BOARD_LCD_WIDTH * 32 + 7) / 8)
|
||||
#endif
|
||||
|
||||
#define SAMA5_BASE_FBSIZE (SAMA5_BASE_STRIDE * CONFIG_SAMA5_LCDC_BASE_HEIGHT)
|
||||
#define SAMA5_BASE_FBSIZE (SAMA5_BASE_STRIDE * BOARD_LCD_HEIGHT)
|
||||
|
||||
#ifndef CONFIG_SAMA5_LCDC_OVR1_MAXWIDTH
|
||||
# define CONFIG_SAMA5_LCDC_OVR1_MAXWIDTH CONFIG_SAMA5_LCDC_BASE_WIDTH
|
||||
# define CONFIG_SAMA5_LCDC_OVR1_MAXWIDTH BOARD_LCD_WIDTH
|
||||
#endif
|
||||
|
||||
#if CONFIG_SAMA5_LCDC_OVR1_MAXWIDTH > BOARD_LCD_WIDTH
|
||||
# error Width of overlay 1 exceeds the width of the display
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SAMA5_LCDC_OVR1_MAXHEIGHT
|
||||
# define CONFIG_SAMA5_LCDC_OVR1_MAXHEIGHT CONFIG_SAMA5_LCDC_BASE_HEIGHT
|
||||
# define CONFIG_SAMA5_LCDC_OVR1_MAXHEIGHT BOARD_LCD_HEIGHT
|
||||
#endif
|
||||
|
||||
#if CONFIG_SAMA5_LCDC_OVR1_MAXHEIGHT > BOARD_LCD_HEIGHT
|
||||
# error Height of overlay 1 exceeds the height of the display
|
||||
#endif
|
||||
|
||||
#if SAMA5_LCDC_OVR1_BPP == 16
|
||||
@ -338,11 +346,19 @@
|
||||
#define SAMA5_OVR1_FBSIZE (SAMA5_OVR1_STRIDE * CONFIG_SAMA5_LCDC_OVR1_MAXHEIGHT)
|
||||
|
||||
#ifndef CONFIG_SAMA5_LCDC_OVR2_MAXWIDTH
|
||||
# define CONFIG_SAMA5_LCDC_OVR2_MAXWIDTH CONFIG_SAMA5_LCDC_BASE_WIDTH
|
||||
# define CONFIG_SAMA5_LCDC_OVR2_MAXWIDTH BOARD_LCD_WIDTH
|
||||
#endif
|
||||
|
||||
#if CONFIG_SAMA5_LCDC_OVR2_MAXWIDTH > BOARD_LCD_WIDTH
|
||||
# error Width of overlay 2 exceeds the width of the display
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SAMA5_LCDC_OVR2_MAXHEIGHT
|
||||
# define CONFIG_SAMA5_LCDC_OVR2_MAXHEIGHT CONFIG_SAMA5_LCDC_BASE_HEIGHT
|
||||
# define CONFIG_SAMA5_LCDC_OVR2_MAXHEIGHT BOARD_LCD_HEIGHT
|
||||
#endif
|
||||
|
||||
#if CONFIG_SAMA5_LCDC_OVR2_MAXHEIGHT > BOARD_LCD_HEIGHT
|
||||
# error Height of overlay 2 exceeds the height of the display
|
||||
#endif
|
||||
|
||||
#if SAMA5_LCDC_OVR2_BPP == 16
|
||||
@ -356,11 +372,19 @@
|
||||
#define SAMA5_OVR2_FBSIZE (SAMA5_OVR2_STRIDE * CONFIG_SAMA5_LCDC_OVR2_MAXHEIGHT)
|
||||
|
||||
#ifndef CONFIG_SAMA5_LCDC_HEO_MAXWIDTH
|
||||
# define CONFIG_SAMA5_LCDC_HEO_MAXWIDTH CONFIG_SAMA5_LCDC_BASE_WIDTH
|
||||
# define CONFIG_SAMA5_LCDC_HEO_MAXWIDTH BOARD_LCD_WIDTH
|
||||
#endif
|
||||
|
||||
#if CONFIG_SAMA5_LCDC_HEO_MAXWIDTH > BOARD_LCD_WIDTH
|
||||
# error Width of HEO exceeds the width of the display
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SAMA5_LCDC_HEO_MAXHEIGHT
|
||||
# define CONFIG_SAMA5_LCDC_HEO_MAXHEIGHT CONFIG_SAMA5_LCDC_BASE_HEIGHT
|
||||
# define CONFIG_SAMA5_LCDC_HEO_MAXHEIGHT BOARD_LCD_HEIGHT
|
||||
#endif
|
||||
|
||||
#if CONFIG_SAMA5_LCDC_HEO_MAXHEIGHT > BOARD_LCD_HEIGHT
|
||||
# error Height of HEO exceeds the height of the display
|
||||
#endif
|
||||
|
||||
#if SAMA5_LCDC_HEO_BPP == 16
|
||||
@ -374,11 +398,19 @@
|
||||
#define SAMA5_HEO_FBSIZE (SAMA5_HEO_STRIDE * CONFIG_SAMA5_LCDC_HEO_MAXHEIGHT)
|
||||
|
||||
#ifndef CONFIG_SAMA5_LCDC_HCR_MAXWIDTH
|
||||
# define CONFIG_SAMA5_LCDC_HCR_MAXWIDTH CONFIG_SAMA5_LCDC_BASE_WIDTH
|
||||
# define CONFIG_SAMA5_LCDC_HCR_MAXWIDTH BOARD_LCD_WIDTH
|
||||
#endif
|
||||
|
||||
#if CONFIG_SAMA5_LCDC_HCR_MAXWIDTH > BOARD_LCD_WIDTH
|
||||
# error Width of the hardware cursor exceeds the width of the display
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SAMA5_LCDC_HCR_MAXHEIGHT
|
||||
# define CONFIG_SAMA5_LCDC_HCR_MAXHEIGHT CONFIG_SAMA5_LCDC_BASE_HEIGHT
|
||||
# define CONFIG_SAMA5_LCDC_HCR_MAXHEIGHT BOARD_LCD_HEIGHT
|
||||
#endif
|
||||
|
||||
#if CONFIG_SAMA5_LCDC_HCR_MAXHEIGHT > BOARD_LCD_HEIGHT
|
||||
# error Height of the hardware cursor exceeds the height of the display
|
||||
#endif
|
||||
|
||||
#if SAMA5_LCDC_HCR_BPP == 16
|
||||
@ -622,8 +654,8 @@ static void sam_show_hcr(void);
|
||||
static const struct fb_videoinfo_s g_base_videoinfo =
|
||||
{
|
||||
.fmt = SAMA5_LCDC_BASE_COLOR_FMT,
|
||||
.xres = CONFIG_SAMA5_LCDC_BASE_WIDTH,
|
||||
.yres = CONFIG_SAMA5_LCDC_BASE_HEIGHT,
|
||||
.xres = BOARD_LCD_WIDTH,
|
||||
.yres = BOARD_LCD_HEIGHT,
|
||||
.nplanes = 1,
|
||||
};
|
||||
|
||||
@ -1163,14 +1195,14 @@ static void sam_setposition(int lid, uint32_t x, uint32_t y)
|
||||
|
||||
/* Clip the position so that the window lies on the physical display */
|
||||
|
||||
if (x + w >= CONFIG_SAMA5_LCDC_BASE_WIDTH)
|
||||
if (x + w >= BOARD_LCD_WIDTH)
|
||||
{
|
||||
x = CONFIG_SAMA5_LCDC_BASE_WIDTH - w;
|
||||
x = BOARD_LCD_WIDTH - w;
|
||||
}
|
||||
|
||||
if (y + h >= CONFIG_SAMA5_LCDC_BASE_HEIGHT)
|
||||
if (y + h >= BOARD_LCD_HEIGHT)
|
||||
{
|
||||
y = CONFIG_SAMA5_LCDC_BASE_HEIGHT - h;
|
||||
y = BOARD_LCD_HEIGHT - h;
|
||||
}
|
||||
|
||||
/* Set the new position of the layer */
|
||||
@ -1450,7 +1482,7 @@ static void sam_base_disable(void)
|
||||
* successfully disabled.
|
||||
*/
|
||||
|
||||
while (sam_getreg(SAM_LCDC_BASECHSR & LCDC_BASECHSR_CH) != 0);
|
||||
while ((sam_getreg(SAM_LCDC_BASECHSR) & LCDC_BASECHSR_CH) != 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -1505,7 +1537,7 @@ static void sam_ovr1_disable(void)
|
||||
* successfully disabled.
|
||||
*/
|
||||
|
||||
while (sam_getreg(SAM_LCDC_OVR1CHSR & LCDC_OVR1CHSR_CH) != 0);
|
||||
while ((sam_getreg(SAM_LCDC_OVR1CHSR) & LCDC_OVR1CHSR_CH) != 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -1560,7 +1592,7 @@ static void sam_ovr2_disable(void)
|
||||
* successfully disabled.
|
||||
*/
|
||||
|
||||
while (sam_getreg(SAM_LCDC_OVR2CHSR & LCDC_OVR2CHSR_CH) != 0);
|
||||
while ((sam_getreg(SAM_LCDC_OVR2CHSR) & LCDC_OVR2CHSR_CH) != 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -1631,7 +1663,7 @@ static void sam_heo_disable(void)
|
||||
* successfully disabled.
|
||||
*/
|
||||
|
||||
while (sam_getreg(SAM_LCDC_HEOCHSR & LCDC_HEOCHSR_CH) != 0);
|
||||
while ((sam_getreg(SAM_LCDC_HEOCHSR) & LCDC_HEOCHSR_CH) != 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -1686,7 +1718,7 @@ static void sam_hcr_disable(void)
|
||||
* successfully disabled.
|
||||
*/
|
||||
|
||||
while (sam_getreg(SAM_LCDC_HCRCHSR & LCDC_HCRCHSR_CH) != 0);
|
||||
while ((sam_getreg(SAM_LCDC_HCRCHSR) & LCDC_HCRCHSR_CH) != 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -2002,40 +2034,41 @@ static void sam_lcd_enable(void)
|
||||
/* 1. Configure LCD timing parameters, signal polarity and clock period. */
|
||||
|
||||
div = ((2 * BOARD_MCK_FREQUENCY) / BOARD_LCD_PIXELCLOCK) - 2;
|
||||
regval = LCDC_LCDCFG0_CLKDIV(div) | LCDC_LCDCFG0_CGDISHCR |
|
||||
LCDC_LCDCFG0_CGDISHEO | LCDC_LCDCFG0_CGDISOVR1 |
|
||||
LCDC_LCDCFG0_CGDISOVR2 | LCDC_LCDCFG0_CGDISBASE |
|
||||
LCDC_LCDCFG0_CLKPWMSEL | LCDC_LCDCFG0_CLKSEL |
|
||||
LCDC_LCDCFG0_CLKPOL;
|
||||
regval = LCDC_LCDCFG0_CLKPOL | LCDC_LCDCFG0_CLKSEL |
|
||||
LCDC_LCDCFG0_CLKPWMSEL | LCDC_LCDCFG0_CGDISBASE |
|
||||
LCDC_LCDCFG0_CGDISOVR1 | LCDC_LCDCFG0_CGDISOVR2 |
|
||||
LCDC_LCDCFG0_CGDISHEO | LCDC_LCDCFG0_CGDISHCR |
|
||||
LCDC_LCDCFG0_CLKDIV(div);
|
||||
sam_putreg(SAM_LCDC_LCDCFG0, regval);
|
||||
|
||||
regval = LCDC_LCDCFG1_VSPW(BOARD_LCD_TIMING_VPW - 1) |
|
||||
LCDC_LCDCFG1_HSPW(BOARD_LCD_TIMING_HPW - 1);
|
||||
regval = LCDC_LCDCFG1_HSPW(BOARD_LCD_TIMING_HPW - 1) |
|
||||
LCDC_LCDCFG1_VSPW(BOARD_LCD_TIMING_VPW - 1);
|
||||
sam_putreg(SAM_LCDC_LCDCFG1, regval);
|
||||
|
||||
regval = LCDC_LCDCFG2_VBPW(BOARD_LCD_TIMING_VBP) |
|
||||
LCDC_LCDCFG2_VFPW(BOARD_LCD_TIMING_VFP - 1);
|
||||
regval = LCDC_LCDCFG2_VFPW(BOARD_LCD_TIMING_VFP - 1) |
|
||||
LCDC_LCDCFG2_VBPW(BOARD_LCD_TIMING_VBP);
|
||||
sam_putreg(SAM_LCDC_LCDCFG2, regval);
|
||||
|
||||
regval = LCDC_LCDCFG3_HBPW(BOARD_LCD_TIMING_HBP - 1) |
|
||||
LCDC_LCDCFG3_HFPW(BOARD_LCD_TIMING_HFP - 1);
|
||||
regval = LCDC_LCDCFG3_HFPW(BOARD_LCD_TIMING_HFP - 1) |
|
||||
LCDC_LCDCFG3_HBPW(BOARD_LCD_TIMING_HBP - 1);
|
||||
sam_putreg(SAM_LCDC_LCDCFG3, regval);
|
||||
|
||||
regval = LCDC_LCDCFG4_RPF(CONFIG_SAMA5_LCDC_BASE_HEIGHT - 1) |
|
||||
LCDC_LCDCFG4_PPL(CONFIG_SAMA5_LCDC_BASE_WIDTH - 1);
|
||||
regval = LCDC_LCDCFG4_PPL(BOARD_LCD_WIDTH - 1) |
|
||||
LCDC_LCDCFG4_RPF(BOARD_LCD_HEIGHT - 1);
|
||||
sam_putreg(SAM_LCDC_LCDCFG4, regval);
|
||||
|
||||
regval = LCDC_LCDCFG5_GUARDTIME(30) | LCDC_LCDCFG5_MODE_24BPP |
|
||||
LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS | LCDC_LCDCFG5_VSPOL |
|
||||
LCDC_LCDCFG5_HSPOL;
|
||||
regval = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL |
|
||||
LCDC_LCDCFG5_VSPDLYS | LCDC_LCDCFG5_DISPDLY |
|
||||
LCDC_LCDCFG5_MODE_24BPP | LCDC_LCDCFG5_GUARDTIME(30);
|
||||
sam_putreg(SAM_LCDC_LCDCFG5, regval);
|
||||
|
||||
regval = LCDC_LCDCFG6_PWMCVAL(0xf0) | LCDC_LCDCFG6_PWMPOL |
|
||||
LCDC_LCDCFG6_PWMPS_DIV64;
|
||||
regval = LCDC_LCDCFG6_PWMPS_DIV64 | LCDC_LCDCFG6_PWMPOL |
|
||||
LCDC_LCDCFG6_PWMCVAL(CONFIG_SAMA5_LCDC_DEFBACKLIGHT);
|
||||
sam_putreg(SAM_LCDC_LCDCFG6, regval);
|
||||
|
||||
/* 2. Enable the Pixel Clock by writing one to the CLKEN field of the
|
||||
LCDC_LCDEN register. */
|
||||
* LCDC_LCDEN register.
|
||||
*/
|
||||
|
||||
sam_putreg(SAM_LCDC_LCDEN, LCDC_LCDEN_CLK);
|
||||
|
||||
@ -2253,14 +2286,14 @@ static void sam_show_layer(struct sam_layer_s *layer,
|
||||
|
||||
/* Windows position & size check */
|
||||
|
||||
if (dispx + dispw > CONFIG_SAMA5_LCDC_BASE_WIDTH)
|
||||
if (dispx + dispw > BOARD_LCD_WIDTH)
|
||||
{
|
||||
dispw = CONFIG_SAMA5_LCDC_BASE_WIDTH - dispx;
|
||||
dispw = BOARD_LCD_WIDTH - dispx;
|
||||
}
|
||||
|
||||
if (dispy + disph > CONFIG_SAMA5_LCDC_BASE_HEIGHT)
|
||||
if (dispy + disph > BOARD_LCD_HEIGHT)
|
||||
{
|
||||
disph = CONFIG_SAMA5_LCDC_BASE_HEIGHT - dispy;
|
||||
disph = BOARD_LCD_HEIGHT - dispy;
|
||||
}
|
||||
|
||||
if (dispw <= 0)
|
||||
@ -2706,8 +2739,7 @@ static void sam_show_layer(struct sam_layer_s *layer,
|
||||
static void sam_show_base(void)
|
||||
{
|
||||
sam_show_layer(&g_base.layer, 0, 0,
|
||||
CONFIG_SAMA5_LCDC_BASE_WIDTH, CONFIG_SAMA5_LCDC_BASE_HEIGHT,
|
||||
CONFIG_SAMA5_LCDC_BASE_WIDTH, CONFIG_SAMA5_LCDC_BASE_HEIGHT);
|
||||
BOARD_LCD_WIDTH, BOARD_LCD_HEIGHT, BOARD_LCD_WIDTH, BOARD_LCD_HEIGHT);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -2733,8 +2765,8 @@ static void sam_show_hcr(uint32_t x, uint32_t y)
|
||||
/* And show the hardware cursor layer */
|
||||
|
||||
sam_show_layer(&g_hcr.layer,
|
||||
(CONFIG_SAMA5_LCDC_BASE_WIDTH - CONFIG_SAMA5_LCDC_HCR_MAXWIDTH) / 2,
|
||||
(CONFIG_SAMA5_LCDC_BASE_HEIGHT - CONFIG_SAMA5_LCDC_HCR_MAXHEIGHT) / 2,
|
||||
(BOARD_LCD_WIDTH - CONFIG_SAMA5_LCDC_HCR_MAXWIDTH) / 2,
|
||||
(BOARD_LCD_HEIGHT - CONFIG_SAMA5_LCDC_HCR_MAXHEIGHT) / 2,
|
||||
CONFIG_SAMA5_LCDC_HCR_MAXWIDTH, CONFIG_SAMA5_LCDC_HCR_MAXHEIGHT,
|
||||
CONFIG_SAMA5_LCDC_HCR_MAXWIDTH, CONFIG_SAMA5_LCDC_HCR_MAXHEIGHT);
|
||||
}
|
||||
@ -2914,14 +2946,47 @@ void fb_uninitialize(void)
|
||||
|
||||
void sam_lcdclear(nxgl_mxpixel_t color)
|
||||
{
|
||||
#if SAMA5_LCDC_BASE_BPP == 16
|
||||
uint16_t *dest = (uint16_t*)g_base.layer.framebuffer;
|
||||
int i;
|
||||
|
||||
gvdbg("Clearing display: BPP=16 color=%04x framebuffer=%08x size=%d\n",
|
||||
color, g_base.layer.framebuffer, SAMA5_BASE_FBSIZE);
|
||||
|
||||
for (i = 0; i < SAMA5_BASE_FBSIZE; i += sizeof(uint16_t))
|
||||
{
|
||||
*dest++ = (uint16_t)color;
|
||||
}
|
||||
#elif SAMA5_LCDC_BASE_BPP == 24
|
||||
uint8_t *dest = (uint8_t*)g_base.layer.framebuffer;
|
||||
uint8_t r;
|
||||
uint8_t g;
|
||||
uint8_t b;
|
||||
int i;
|
||||
|
||||
gvdbg("Clearing display: BPP=24 color=%06x framebuffer=%08x size=%d\n",
|
||||
color, g_base.layer.framebuffer, SAMA5_BASE_FBSIZE);
|
||||
|
||||
b = color & 0xff;
|
||||
g = (color >> 8) & 0xff;
|
||||
r = (color >> 16) & 0xff;
|
||||
|
||||
for (i = 0; i < SAMA5_BASE_FBSIZE; i += 3*sizeof(uint8_t))
|
||||
{
|
||||
*dest++ = b;
|
||||
*dest++ = r;
|
||||
*dest++ = g;
|
||||
}
|
||||
#elif SAMA5_LCDC_BASE_BPP == 32
|
||||
uint32_t *dest = (uint32_t*)g_base.layer.framebuffer;
|
||||
int i;
|
||||
|
||||
gvdbg("Clearing display: color=%08x framebuffer=%08x size=%d\n",
|
||||
gvdbg("Clearing display: BPP=32 color=%08x framebuffer=%08x size=%d\n",
|
||||
color, g_base.layer.framebuffer, SAMA5_BASE_FBSIZE);
|
||||
|
||||
for (i = 0; i < SAMA5_BASE_FBSIZE; i += sizeof(uint32_t))
|
||||
{
|
||||
*dest++ = color;
|
||||
*dest++ = (uint32_t)color;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -124,7 +124,6 @@
|
||||
#define BOARD_BLUE_BIT (1 << BOARD_BLUE)
|
||||
#define BOARD_RED_BIT (1 << BOARD_RED)
|
||||
|
||||
|
||||
/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
|
||||
* defined. In that case, the usage by the board port is defined in
|
||||
* include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
|
||||
|
||||
@ -162,7 +162,7 @@ CONFIG_SAMA5_LCDC=y
|
||||
# CONFIG_SAMA5_TRNG is not set
|
||||
# CONFIG_SAMA5_ARM is not set
|
||||
# CONFIG_SAMA5_FUSE is not set
|
||||
# CONFIG_SAMA5_MPDDRC is not set
|
||||
CONFIG_SAMA5_MPDDRC=y
|
||||
# CONFIG_SAMA5_PIO_IRQ is not set
|
||||
CONFIG_SAMA5_HAVE_LCDC=y
|
||||
|
||||
@ -171,7 +171,7 @@ CONFIG_SAMA5_HAVE_LCDC=y
|
||||
#
|
||||
CONFIG_SAMA5_LCDC_BACKLIGHT=y
|
||||
CONFIG_SAMA5_LCDC_DEFBACKLIGHT=0xf0
|
||||
CONFIG_SAMA5_LCDC_BACKCOLOR=0x0
|
||||
CONFIG_SAMA5_LCDC_BACKCOLOR=0x007b68ee
|
||||
CONFIG_SAMA5_LCDC_FBALLOCATED=y
|
||||
# CONFIG_SAMA5_LCDC_FBFIXED is not set
|
||||
# CONFIG_SAMA5_LCDC_FBPREALLOCATED is not set
|
||||
@ -179,8 +179,6 @@ CONFIG_SAMA5_LCDC_FBALLOCATED=y
|
||||
#
|
||||
# Base layer configuration
|
||||
#
|
||||
CONFIG_SAMA5_LCDC_BASE_HEIGHT=480
|
||||
CONFIG_SAMA5_LCDC_BASE_WIDTH=800
|
||||
CONFIG_SAMA5_LCDC_BASE_ROT0=y
|
||||
# CONFIG_SAMA5_LCDC_BASE_ROT90 is not set
|
||||
# CONFIG_SAMA5_LCDC_BASE_ROT180 is not set
|
||||
@ -205,6 +203,10 @@ CONFIG_SAMA5_HAVE_GMAC=y
|
||||
#
|
||||
# External Memory Configuration
|
||||
#
|
||||
CONFIG_SAMA5_DDRCS=y
|
||||
CONFIG_SAMA5_DDRCS_SIZE=268435456
|
||||
# CONFIG_SAMA5_DDRCS_LPDDR1 is not set
|
||||
CONFIG_SAMA5_DDRCS_LPDDR2=y
|
||||
CONFIG_SAMA5_EBICS0=y
|
||||
CONFIG_SAMA5_EBICS0_SIZE=134217728
|
||||
# CONFIG_SAMA5_EBICS0_SRAM is not set
|
||||
@ -219,12 +221,14 @@ CONFIG_SAMA5_EBICS0_NOR=y
|
||||
# CONFIG_SAMA5_EBICS2 is not set
|
||||
# CONFIG_SAMA5_EBICS3 is not set
|
||||
# CONFIG_SAMA5_BOOT_ISRAM is not set
|
||||
# CONFIG_SAMA5_BOOT_SDRAM is not set
|
||||
CONFIG_SAMA5_BOOT_CS0FLASH=y
|
||||
|
||||
#
|
||||
# Heap Configuration
|
||||
#
|
||||
CONFIG_SAMA5_ISRAM_HEAP=y
|
||||
CONFIG_SAMA5_DDRCS_HEAP=y
|
||||
|
||||
#
|
||||
# Architecture Options
|
||||
@ -288,6 +292,8 @@ CONFIG_ARCH_HAVE_IRQBUTTONS=y
|
||||
#
|
||||
# Board-Specific Options
|
||||
#
|
||||
CONFIG_SAMA5_MT47H128M16RT=y
|
||||
# CONFIG_SAMA5_MT47H64M16HR is not set
|
||||
|
||||
#
|
||||
# RTOS Features
|
||||
@ -458,8 +464,8 @@ CONFIG_NX_DISABLE_2BPP=y
|
||||
CONFIG_NX_DISABLE_4BPP=y
|
||||
CONFIG_NX_DISABLE_8BPP=y
|
||||
CONFIG_NX_DISABLE_16BPP=y
|
||||
CONFIG_NX_DISABLE_24BPP=y
|
||||
# CONFIG_NX_DISABLE_32BPP is not set
|
||||
# CONFIG_NX_DISABLE_24BPP is not set
|
||||
CONFIG_NX_DISABLE_32BPP=y
|
||||
CONFIG_NX_PACKEDMSFIRST=y
|
||||
|
||||
#
|
||||
@ -509,7 +515,7 @@ CONFIG_NXFONT_SERIF22X28B=y
|
||||
#
|
||||
# CONFIG_MM_MULTIHEAP is not set
|
||||
# CONFIG_MM_SMALL is not set
|
||||
CONFIG_MM_REGIONS=1
|
||||
CONFIG_MM_REGIONS=2
|
||||
# CONFIG_GRAN is not set
|
||||
|
||||
#
|
||||
|
||||
Loading…
Reference in New Issue
Block a user