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s32k1xx: Added FlexCAN driver with SocketCAN support

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This commit is contained in:
Peter van der Perk 2020-06-15 10:24:23 +02:00 committed by patacongo
parent 55d9e5f7af
commit ff76ef0725
27 changed files with 3136 additions and 69 deletions
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164
arch/arm/src/s32k1xx/Kconfig
View File

@ -27,6 +27,7 @@ config ARCH_CHIP_S32K118
config ARCH_CHIP_S32K142
bool "S32K142"
select ARCH_CHIP_S32K14X
select S32K1XX_HAVE_FLEXCAN1
---help---
Cortex-M4F, 256Kb FLASH, 32Kb RAM incl. 4Kb FlexRAM
@ -34,6 +35,8 @@ config ARCH_CHIP_S32K144
bool "S32K144"
select ARCH_CHIP_S32K14X
select S32K1XX_HAVE_LPSPI2
select S32K1XX_HAVE_FLEXCAN1
select S32K1XX_HAVE_FLEXCAN2
---help---
Cortex-M4F, 512Kb FLASH, 64Kb RAM incl. 4Kb FlexRAM
@ -41,6 +44,8 @@ config ARCH_CHIP_S32K146
bool "S32K146"
select ARCH_CHIP_S32K14X
select S32K1XX_HAVE_LPSPI2
select S32K1XX_HAVE_FLEXCAN1
select S32K1XX_HAVE_FLEXCAN2
---help---
Cortex-M4F, 1Mb FLASH, 128Kb RAM incl. 4Kb FlexRAM
@ -51,6 +56,8 @@ config ARCH_CHIP_S32K148
select S32K1XX_HAVE_LPI2C1
select S32K1XX_HAVE_LPSPI2
select S32K1XX_HAVE_SAI
select S32K1XX_HAVE_FLEXCAN1
select S32K1XX_HAVE_FLEXCAN2
---help---
Cortex-M4F, 2Mb FLASH, 256Kb RAM incl. 4Kb FlexRAM
@ -110,6 +117,14 @@ config S32K1XX_HAVE_LPSPI1
config S32K1XX_HAVE_LPSPI2
bool
default n
config S32K1XX_HAVE_FLEXCAN1
bool
default n
config S32K1XX_HAVE_FLEXCAN2
bool
default n
config S32K1XX_HAVE_QSPI
bool
@ -137,6 +152,11 @@ config S32K1XX_LPSPI
bool
default n
config S32K1XX_FLEXCAN
bool
select NET_CAN_HAVE_CANFD
default n
# Peripheral Selection
menu "S32K1XX Peripheral Selection"
@ -150,6 +170,26 @@ config S32K1XX_ENET
default n
depends on S32K1XX_HAVE_ENET
config S32K1XX_FLEXCAN0
bool "FLEXCAN0"
select S32K1XX_FLEXCAN
select NET_CAN_HAVE_TX_DEADLINE
default n
config S32K1XX_FLEXCAN1
bool "FLEXCAN1"
select S32K1XX_FLEXCAN
select NET_CAN_HAVE_TX_DEADLINE
default n
depends on S32K1XX_HAVE_FLEXCAN1
config S32K1XX_FLEXCAN2
bool "FLEXCAN2"
select S32K1XX_FLEXCAN
select NET_CAN_HAVE_TX_DEADLINE
default n
depends on S32K1XX_HAVE_FLEXCAN2
menuconfig S32K1XX_LPI2C0
bool "LPI2C0"
default n
@ -205,6 +245,15 @@ config S32K1XX_LPUART2
config S32K1XX_RTC
bool "RTC"
default n
config S32K1XX_PROGMEM
bool PROGMEM
default n
select ARCH_HAVE_PROGMEM
depends on (ARCH_CHIP_S32K11X || (ARCH_CHIP_S32K14X && !ARCH_CHIP_S32K148) )
---help---
Use the FlexNVM 32/64 KB of d-flash memory as a
Memory-Technology-Device (MTD).
endmenu # S32K1XX Peripheral Selection
@ -453,4 +502,119 @@ config S32K1XX_ENET_PHYINIT
endmenu # S32K1XX_ENET
menu "FLEXCAN0 Configuration"
depends on S32K1XX_FLEXCAN0
config FLEXCAN0_BITRATE
int "CAN bitrate"
depends on !NET_CAN_CANFD
default 1000000
config FLEXCAN0_SAMPLEP
int "CAN sample point"
depends on !NET_CAN_CANFD
default 80
config FLEXCAN0_ARBI_BITRATE
int "CAN FD Arbitration phase bitrate"
depends on NET_CAN_CANFD
default 1000000
config FLEXCAN0_ARBI_SAMPLEP
int "CAN FD Arbitration phase sample point"
depends on NET_CAN_CANFD
default 80
config FLEXCAN0_DATA_BITRATE
int "CAN FD Arbitration phase bitrate"
depends on NET_CAN_CANFD
default 4000000
config FLEXCAN0_DATA_SAMPLEP
int "CAN FD Arbitration phase sample point"
depends on NET_CAN_CANFD
default 90
endmenu # S32K1XX_FLEXCAN0
menu "FLEXCAN1 Configuration"
depends on S32K1XX_FLEXCAN1
config FLEXCAN1_BITRATE
int "CAN bitrate"
depends on !NET_CAN_CANFD
default 1000000
config FLEXCAN1_SAMPLEP
int "CAN sample point"
depends on !NET_CAN_CANFD
default 80
config FLEXCAN1_ARBI_BITRATE
int "CAN FD Arbitration phase bitrate"
depends on NET_CAN_CANFD
default 1000000
config FLEXCAN1_ARBI_SAMPLEP
int "CAN FD Arbitration phase sample point"
depends on NET_CAN_CANFD
default 80
config FLEXCAN1_DATA_BITRATE
int "CAN FD Arbitration phase bitrate"
depends on NET_CAN_CANFD
default 4000000
config FLEXCAN1_DATA_SAMPLEP
int "CAN FD Arbitration phase sample point"
depends on NET_CAN_CANFD
default 90
endmenu # S32K1XX_FLEXCAN1
menu "FLEXCAN2 Configuration"
depends on S32K1XX_FLEXCAN2
config FLEXCAN2_BITRATE
int "CAN bitrate"
depends on !NET_CAN_CANFD
default 1000000
config FLEXCAN2_SAMPLEP
int "CAN sample point"
depends on !NET_CAN_CANFD
default 80
config FLEXCAN2_ARBI_BITRATE
int "CAN FD Arbitration phase bitrate"
depends on NET_CAN_CANFD
default 1000000
config FLEXCAN2_ARBI_SAMPLEP
int "CAN FD Arbitration phase sample point"
depends on NET_CAN_CANFD
default 80
config FLEXCAN2_DATA_BITRATE
int "CAN FD Arbitration phase bitrate"
depends on NET_CAN_CANFD
default 4000000
config FLEXCAN2_DATA_SAMPLEP
int "CAN FD Arbitration phase sample point"
depends on NET_CAN_CANFD
default 90
endmenu # S32K1XX_FLEXCAN0
menu "PROGMEM Configuration"
depends on S32K1XX_PROGMEM
config PROGMEM_SIZE
int "Progmem size (KB)"
default 64 if ARCH_CHIP_S32K14X
default 32 if ARCH_CHIP_S32K11X
endmenu
endif # ARCH_CHIP_S32K1XX

8
arch/arm/src/s32k1xx/Make.defs
View File

@ -87,10 +87,18 @@ ifeq ($(CONFIG_S32K1XX_ENET),y)
CHIP_CSRCS += s32k1xx_enet.c
endif
ifeq ($(CONFIG_S32K1XX_FLEXCAN),y)
CHIP_CSRCS += s32k1xx_flexcan.c
endif
ifeq ($(CONFIG_S32K1XX_RTC),y)
CHIP_CSRCS += s32k1xx_rtc.c
endif
ifeq ($(CONFIG_S32K1XX_PROGMEM),y)
CHIP_CSRCS += s32k1xx_progmem.c
endif
# Source files specific to the ARM CPU family and to the S32K1xx chip family
ifeq ($(CONFIG_ARCH_CHIP_S32K11X),y)

103
arch/arm/src/s32k1xx/hardware/s32k1xx_flexcan.h
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@ -66,8 +66,11 @@
#define S32K1XX_CAN_CRCR_OFFSET 0x0044 /* CRC Register */
#define S32K1XX_CAN_RXFGMASK_OFFSET 0x0048 /* Rx FIFO Global Mask Register */
#define S32K1XX_CAN_RXFIR_OFFSET 0x004c /* Rx FIFO Information Register */
#define S32K1XX_CAN_CBT_OFFSET 0x0050 /* CAN Bit Timing register */
#define S32K1XX_CAN_RXIMR_OFFSET(n) (0x0880 + ((n) << 2)) /* Rn Individual Mask Registers */
#define S32K1XX_CAN_MB_OFFSET 0x0080 /* CAN MB register */
#define S32K1XX_CAN_RXIMR_OFFSET(n) (0x0880 + ((n) << 2))
# define S32K1XX_CAN_RXIMR0_OFFSET 0x0880 /* R0 Individual Mask Registers */
# define S32K1XX_CAN_RXIMR1_OFFSET 0x0884 /* R1 Individual Mask Registers */
# define S32K1XX_CAN_RXIMR2_OFFSET 0x0888 /* R2 Individual Mask Registers */
@ -141,7 +144,7 @@
#define S32K1XX_CAN_FDCTRL_OFFSET 0x0c00 /* CAN FD Control register */
#define S32K1XX_CAN_FDCBT_OFFSET 0x0c04 /* CAN FD Bit Timing register */
#define S32K1XX_CAN_FDCRC_OFFSET 0x0c08 /* CAN FD CRC register */
#define S32K1XX_CAN_FDCRC_OFFSET 0x0c08 /* CAN FD CRC register */
/* Register Addresses ***************************************************************************************/
@ -162,6 +165,11 @@
#define S32K1XX_CAN0_CRCR (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_CRCR_OFFSET)
#define S32K1XX_CAN0_RXFGMASK (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_RXFGMASK_OFFSET)
#define S32K1XX_CAN0_RXFIR (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_RXFIR_OFFSET)
#define S32K1XX_CAN0_CBT (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_CBT_OFFSET)
#define S32K1XX_CAN0_MB (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_MB_OFFSET)
#define S32K1XX_CAN0_FDCTRL (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_FDCTRL_OFFSET)
#define S32K1XX_CAN0_FDCBT (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_FDCBT_OFFSET)
#define S32K1XX_CAN0_FDCRC (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_FDCRC_OFFSET)
#define S32K1XX_CAN0_RXIMR(n) (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_RXIMR_OFFSET(n))
# define S32K1XX_CAN0_RXIMR0 (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_RXIMR0_OFFSET)
@ -335,12 +343,15 @@
#define CAN_MCR_MAXMB_MASK (0x7f << CAN_MCR_MAXMB_SHIFT)
/* Bit 7: Reserved */
#define CAN_MCR_IDAM_SHIFT (8) /* Bits 8-9: ID Acceptance Mode */
#define CAN_MCR_IDAM_MASK (3 << CAN_MCR_IDAM_SHIFT)
# define CAN_MCR_IDAM_FMTA (0 << CAN_MCR_IDAM_SHIFT) /* Format A: One full ID */
# define CAN_MCR_IDAM_FMTB (1 << CAN_MCR_IDAM_SHIFT) /* Format B: Two full (or partial) IDs */
# define CAN_MCR_IDAM_FMTC (2 << CAN_MCR_IDAM_SHIFT) /* Format C: Four partial IDs */
# define CAN_MCR_IDAM_FMTD (3 << CAN_MCR_IDAM_SHIFT) /* Format D: All frames rejected */
/* Bits 10-11: Reserved */
/* Bit 10: Reserved */
#define CAN_MCR_FDEN (1 << 11) /* Bit 11: CAN FD operation enable */
#define CAN_MCR_AEN (1 << 12) /* Bit 12: Abort Enable */
#define CAN_MCR_LPRIOEN (1 << 13) /* Bit 13: Local Priority Enable */
/* Bits 14-15: Reserved */
@ -363,8 +374,7 @@
/* Control 1 Register */
#define CAN_CTRL1_ROPSEG_SHIFT (0) /* Bits 0-2: Propagation Segment */
#define CAN_CTRL1_ROPSEG_MASK (7 << CAN_CTRL1_ROPSEG_SHIFT)
#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0x7)
#define CAN_CTRL1_LOM (1 << 3) /* Bit 3: Listen-Only Mode */
#define CAN_CTRL1_LBUF (1 << 4) /* Bit 4: Lowest Buffer Transmitted First */
#define CAN_CTRL1_TSYN (1 << 5) /* Bit 5: Timer Sync */
@ -377,14 +387,10 @@
#define CAN_CTRL1_CLKSRC (1 << 13) /* Bit 13: CAN Engine Clock Source */
#define CAN_CTRL1_ERRMSK (1 << 14) /* Bit 14: Error Mask */
#define CAN_CTRL1_BOFFMSK (1 << 15) /* Bit 15: Bus Off Mask */
#define CAN_CTRL1_PSEG2_SHIFT (16) /* Bits 16-18: Phase Segment 2 */
#define CAN_CTRL1_PSEG2_MASK (7 << CAN_CTRL1_PSEG2_SHIFT)
#define CAN_CTRL1_PSEG1_SHIFT (19) /* Bits 19-21: Phase Segment 1 */
#define CAN_CTRL1_PSEG1_MASK (7 << CAN_CTRL1_PSEG1_SHIFT)
#define CAN_CTRL1_RJW_SHIFT (22) /* Bits 22-23: Resync Jump Width */
#define CAN_CTRL1_RJW_MASK (3 << CAN_CTRL1_RJW_SHIFT)
#define CAN_CTRL1_PRESDIV_SHIFT (24) /* Bits 24-31: Prescaler Division Factor */
#define CAN_CTRL1_PRESDIV_MASK (0xff << CAN_CTRL1_PRESDIV_SHIFT)
#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0x70000)
#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << 19)) & 0x380000)
#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << 22)) & 0xC00000)
#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << 24)) & 0xFF000000)
/* Free Running Timer */
@ -409,8 +415,8 @@
#define CAN_ECR_TXERRCNT_SHIFT (0) /* Bits 0-7: Transmit Error Counter */
#define CAN_ECR_TXERRCNT_MASK (0xff << CAN_ECR_TXERRCNT_SHIFT)
#define CAN_ECR_RXERRCNT_SHIFT (8) /* Bits 8-15: Receive Error Counter */
#define CAN_ECR_RXERRCNT_MASK (0xff << CAN_ECR_RXERRCNT_SHIFT)
/* Bits 16-31: Reserved */
#define CAN_ECR_RXERRCNT_MASK (0xff << CAN_ECR_RXERRCNT_SHIFT)
/* Bits 16-31: Reserved */
/* Error and Status 1 Register */
@ -419,13 +425,15 @@
#define CAN_ESR1_BOFFINT (1 << 2) /* Bit 2: 'Bus Off' Interrupt */
#define CAN_ESR1_RX (1 << 3) /* Bit 3: FlexCAN in Reception */
#define CAN_ESR1_FLTCONF_SHIFT (4) /* Bits 4-5: Fault Confinement State */
#define CAN_ESR1_FLTCONF_MASK (3 << CAN_ESR1_FLTCONF_SHIFT)
# define CAN_ESR1_FLTCONF_ACTV (0 << CAN_ESR1_FLTCONF_SHIFT) /* Error Active */
# define CAN_ESR1_FLTCONF_PASV (1 << CAN_ESR1_FLTCONF_SHIFT) /* Error Passive */
# define CAN_ESR1_FLTCONF_OFF (2 << CAN_ESR1_FLTCONF_SHIFT) /* Bus Off */
#define CAN_ESR1_TX (1 << 6) /* Bit 6: FlexCAN in Transmission */
#define CAN_ESR1_IDLE (1 << 7) /* Bit 7: CAN bus is in IDLE state */
#define CAN_ESR1_RXWRN (1 << 8) /* Bit 8: Rx Error Warning */
#define CAN_ESR1_RXWRN (1 << 8) /* Bit 8: Rx Error Warning */
#define CAN_ESR1_TXWRN (1 << 9) /* Bit 9: TX Error Warning */
#define CAN_ESR1_STFERR (1 << 10) /* Bit 10: Stuffing Error */
#define CAN_ESR1_FRMERR (1 << 11) /* Bit 11: Form Error */
@ -437,6 +445,7 @@
#define CAN_ESR1_TWRNINT (1 << 17) /* Bit 17: Tx Warning Interrupt Flag */
#define CAN_ESR1_SYNCH (1 << 18) /* Bit 18: CAN Synchronization Status */
/* Bits 19-31: Reserved */
/* Interrupt Masks 2 Register */
#define CAN_IMASK2(n) (1 << (n)) /* Bit n: Buffer MBn Mask */
@ -454,7 +463,13 @@
#define CAN_IFLAG1(n) (1 << (n)) /* Bit n: Buffer MBn Interrupt, n=0..4,8..31 */
/* Control 2 Register */
/* Bits 0-15: Reserved */
/* Bits 0-10: Reserved */
#define CAN_CTRL2_EDFLTDIS (1 << 11) /* Bit 11: Edge Filter Disable */
#define CAN_CTRL2_ISOCANFDEN (1 << 12) /* Bit 12: ISO CAN FD Enable */
/* Bit 13: Reserved */
#define CAN_CTRL2_PREXCEN (1 << 14) /* Bit 14: Protocol Exception Enable */
#define CAN_CTRL2_TIMER_SRC (1 << 15) /* Bit 15: Timer Source */
#define CAN_CTRL2_EACEN (1 << 16) /* Bit 16: Entire Frame Arbitration Field Comparison Enable (Rx) */
#define CAN_CTRL2_RRS (1 << 17) /* Bit 17: Remote Request Storing */
#define CAN_CTRL2_MRP (1 << 18) /* Bit 18: Mailboxes Reception Priority */
@ -482,6 +497,7 @@
/* Bits 29-31: Reserved */
/* Error and Status 2 Register */
/* Bits 0-12: Reserved */
#define CAN_ESR2_IMB (1 << 13) /* Bit 13: Inactive Mailbox */
#define CAN_ESR2_VPS (1 << 14) /* Bit 14: Valid Priority Status */
@ -502,15 +518,54 @@
/* Rx FIFO Global Mask Register (32 Rx FIFO Global Mask Bits) */
/* Rx FIFO Information Register */
/* Bits 9-31: Reserved */
#define CAN_RXFIR_IDHIT_SHIFT (0) /* Bits 0-8: Identifier Acceptance Filter Hit Indicator */
#define CAN_RXFIR_IDHIT_MASK (0x1ff << CAN_RXFIR_IDHIT_SHIFT)
/* CAN Bit Timing register (CBT) */
/* CBT Bit Fields */
#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0x1F)
#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << 5)) & 0x3E0)
#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << 10)) & 0xFC00)
#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0x1F0000)
#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << 21)) & 0x7FE00000)
#define CAN_CBT_BTF (1 << 31) /* Bit 31: Bit Timing Format Enable */
/* CAN MB TX codes */
#define CAN_TXMB_INACTIVE 0x8 /* MB is not active. */
#define CAN_TXMB_ABORT 0x9 /* MB is aborted. */
#define CAN_TXMB_DATAORREMOTE 0xC /* MB is a TX Data Frame(when MB RTR = 0) or */
/* MB is a TX Remote Request Frame (when MB RTR = 1). */
#define CAN_TXMB_TANSWER 0xE /* MB is a TX Response Request Frame from */
/* an incoming Remote Request Frame. */
#define CAN_TXMB_NOTUSED 0xF /* Not used.*/
/* CAN FD Control register (FDCTRL) */
#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0x3F)
#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << 8)) & 0x1F00)
#define CAN_FDCTRL_TDCF (1 << 14) /* Bit 14: TDC fail */
#define CAN_FDCTRL_TDCEN (1 << 15) /* Bit 15: TDC enable */
#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0x30000)
#define CAN_FDCTRL_FDRATE (1 << 31) /* Bit 31: FD rate */
/* FDCBT Bit Fields */
#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0x7)
#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << 5)) & 0xE0)
#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << 10)) & 0x7C00)
#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0x70000)
#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << 20)) & 0x3FF00000)
/* FDCRC Bit Fields */
#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0x1FFFFF)
#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << 24)) & 0x7F000000)
/* Rn Individual Mask Registers */
#define CAN_RXIMR(n) (1 << (n)) /* Bit n: Individual Mask Bits */
/* Pretended Networking Control 1 register */
/* Pretended Networking Control 1 register */
#define CAN_CTRL1_PN_
/* Pretended Networking Control 2 register */
@ -561,16 +616,4 @@
/* CAN FD CRC register */
#define CAN_FDCRC_
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FLEXCAN_H */

143
arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h Normal file
View File

@ -0,0 +1,143 @@
/*****************************************************************************************************
* arch/arm/src/s32k1xx/chip/s32k1xx_ftfc.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FTFC_H
#define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FTFC_H
/*****************************************************************************************************
* Included Files
*****************************************************************************************************/
#include <nuttx/config.h>
#include <hardware/s32k1xx_memorymap.h>
/*****************************************************************************************************
* Pre-processor Definitions
*****************************************************************************************************/
/* FTFC Register Offsets *****************************************************************************/
/* FTFC Register Offsets *****************************************************************************/
#define S32K1XX_FTFC_FSTAT_OFFSET 0x0000
#define S32K1XX_FTFC_FCNFG_OFFSET 0x0001
#define S32K1XX_FTFC_FSEC_OFFSET 0x0002
#define S32K1XX_FTFC_FOPT_OFFSET 0x0003
#define S32K1XX_FTFC_FCCOB3_OFFSET 0x0004
#define S32K1XX_FTFC_FCCOB2_OFFSET 0x0005
#define S32K1XX_FTFC_FCCOB1_OFFSET 0x0006
#define S32K1XX_FTFC_FCCOB0_OFFSET 0x0007
#define S32K1XX_FTFC_FCCOB7_OFFSET 0x0008
#define S32K1XX_FTFC_FCCOB6_OFFSET 0x0009
#define S32K1XX_FTFC_FCCOB5_OFFSET 0x000a
#define S32K1XX_FTFC_FCCOB4_OFFSET 0x000b
#define S32K1XX_FTFC_FCCOBB_OFFSET 0x000c
#define S32K1XX_FTFC_FCCOBA_OFFSET 0x000d
#define S32K1XX_FTFC_FCCOB9_OFFSET 0x000e
#define S32K1XX_FTFC_FCCOB8_OFFSET 0x000f
#define S32K1XX_FTFC_FPROT3_OFFSET 0x0010
#define S32K1XX_FTFC_FPROT2_OFFSET 0x0011
#define S32K1XX_FTFC_FPROT1_OFFSET 0x0012
#define S32K1XX_FTFC_FPROT0_OFFSET 0x0013
#define S32K1XX_FTFC_FEPROT_OFFSET 0x0016
#define S32K1XX_FTFC_FDPROT_OFFSET 0x0017
#define S32K1XX_FTFC_FCSESTAT_OFFSET 0x002c
#define S32K1XX_FTFC_FERSTAT_OFFSET 0x002e
#define S32K1XX_FTFC_FERCNFG_OFFSET 0x002f
/* FTFC Register Addresses ***************************************************************************/
#define S32K1XX_FTFC_FSTAT (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FSTAT_OFFSET)
#define S32K1XX_FTFC_FCNFG (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCNFG_OFFSET)
#define S32K1XX_FTFC_FSEC (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FSEC_OFFSET)
#define S32K1XX_FTFC_FOPT (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FOPT_OFFSET)
#define S32K1XX_FTFC_FCCOB3 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB3_OFFSET)
#define S32K1XX_FTFC_FCCOB2 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB2_OFFSET)
#define S32K1XX_FTFC_FCCOB1 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB1_OFFSET)
#define S32K1XX_FTFC_FCCOB0 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB0_OFFSET)
#define S32K1XX_FTFC_FCCOB7 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB7_OFFSET)
#define S32K1XX_FTFC_FCCOB6 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB6_OFFSET)
#define S32K1XX_FTFC_FCCOB5 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB5_OFFSET)
#define S32K1XX_FTFC_FCCOB4 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB4_OFFSET)
#define S32K1XX_FTFC_FCCOBB (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOBB_OFFSET)
#define S32K1XX_FTFC_FCCOBA (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOBA_OFFSET)
#define S32K1XX_FTFC_FCCOB9 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB9_OFFSET)
#define S32K1XX_FTFC_FCCOB8 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB8_OFFSET)
#define S32K1XX_FTFC_FPROT3 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FPROT3_OFFSET)
#define S32K1XX_FTFC_FPROT2 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FPROT2_OFFSET)
#define S32K1XX_FTFC_FPROT1 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FPROT1_OFFSET)
#define S32K1XX_FTFC_FPROT0 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FPROT0_OFFSET)
#define S32K1XX_FTFC_FEPROT (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FEPROT_OFFSET)
#define S32K1XX_FTFC_FDPROT (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FDPROT_OFFSET)
#define S32K1XX_FTFC_FCSESTAT (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCSESTAT_OFFSET)
#define S32K1XX_FTFC_FERSTAT (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FERSTAT_OFFSET)
#define S32K1XX_FTFC_FERCNFG (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FERCNFG_OFFSET)
/* FTFC Register Bitfield Definitions ****************************************************************/
#define FTTC_FSTAT_MGSTAT0 (1 << 0)
#define FTTC_FSTAT_FPVIOL (1 << 4)
#define FTTC_FSTAT_ACCERR (1 << 5)
#define FTTC_FSTAT_RDCOLERR (1 << 6)
#define FTTC_FSTAT_CCIF (1 << 7)
#define FTTC_FCNFG_EEERDY (1 << 0)
#define FTTC_FCNFG_RAMRDY (1 << 1)
/* Flash controller command numbers ******************************************************************/
#define S32K1XX_FTFC_VERIFY_BLOCK 0x00 /* RD1BLK*/
#define S32K1XX_FTFC_VERIFY_SECTION 0x01 /* RD1SEC*/
#define S32K1XX_FTFC_PROGRAM_CHECK 0x02 /* PGMCHK*/
#define S32K1XX_FTFC_READ_RESOURCE 0x03 /* RDRSRC*/
#define S32K1XX_FTFC_PROGRAM_LONGWORD 0x06 /* PGM4*/
#define S32K1XX_FTFC_PROGRAM_PHRASE 0x07 /* PGM8*/
#define S32K1XX_FTFC_ERASE_BLOCK 0x08 /* ERSBLK*/
#define S32K1XX_FTFC_ERASE_SECTOR 0x09 /* ERSSCR*/
#define S32K1XX_FTFC_PROGRAM_SECTION 0x0B /* PGMSEC*/
#define S32K1XX_FTFC_GENERATE_CRC 0x0C /* CRCGEN*/
#define S32K1XX_FTFC_VERIFY_ALL_BLOCK 0x40 /* RD1ALL*/
#define S32K1XX_FTFC_READ_ONCE 0x41 /* RDONCE or RDINDEX*/
#define S32K1XX_FTFC_PROGRAM_ONCE 0x43 /* PGMONCE or PGMINDEX*/
#define S32K1XX_FTFC_ERASE_ALL_BLOCK 0x44 /* ERSALL*/
#define S32K1XX_FTFC_SECURITY_BY_PASS 0x45 /* VFYKEY*/
#define S32K1XX_FTFC_SWAP_CONTROL 0x46 /* SWAP*/
#define S32K1XX_FTFC_ERASE_ALL_BLOCK_UNSECURE 0x49 /* ERSALLU*/
#define S32K1XX_FTFC_VERIFY_ALL_EXECUTE_ONLY_SEGMENT 0x4A /* RD1XA*/
#define S32K1XX_FTFC_ERASE_ALL_EXECUTE_ONLY_SEGMENT 0x4B /* ERSXA*/
#define S32K1XX_FTFC_PROGRAM_PARTITION 0x80 /* PGMPART */
#define S32K1XX_FTFC_SET_FLEXRAM_FUNCTION 0x81 /* SETRAM */
#endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FTFC_H */

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115
arch/arm/src/s32k1xx/s32k1xx_flexcan.h Normal file
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/************************************************************************************
* arch/arm/src/s32k1xx/s32k1xx_flexcan.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_FLEXCAN_H
#define __ARCH_ARM_SRC_S32K1XX_S32K1XX_FLEXCAN_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "hardware/s32k1xx_flexcan.h"
#ifdef CONFIG_S32K1XX_FLEXCAN
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Function: arm_netinitialize
*
* Description:
* Initialize the first network interface. If there are more than one
* interface in the chip, then board-specific logic will have to provide
* this function to determine which, if any, Ethernet controllers should
* be initialized. Also prototyped in up_internal.h.
*
* Input Parameters:
* None
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
* Called very early in the initialization sequence.
*
************************************************************************************/
void arm_netinitialize(void);
/************************************************************************************
* Function: s32k1xx_phy_boardinitialize
*
* Description:
* Some boards require specialized initialization of the PHY before it can be
* used. This may include such things as configuring GPIOs, resetting the PHY,
* etc. If CONFIG_S32K1XX_FLEXCAN_PHYINIT is defined in the configuration then the
* board specific logic must provide s32k1xx_phyinitialize(); The i.MX RT Ethernet
* driver will call this function one time before it first uses the PHY.
*
* Input Parameters:
* intf - Always zero for now.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_S32K1XX_FLEXCAN */
#endif /* __ARCH_ARM_SRC_S32K1XX_S32K1XX_FLEXCAN_H */

424
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/******************************************************************************
* arch/arm/src/s32k1xx/s32k1xx_progmem.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
/******************************************************************************
* Included Files
******************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <errno.h>
#include "arm_arch.h"
#include "hardware/s32k1xx_ftfc.h"
#include "s32k1xx_config.h"
#include "s32k1xx_progmem.h"
#include "arm_internal.h"
#include <arch/board/board.h> /* Include last: has dependencies */
/******************************************************************************
* Pre-processor Definitions
******************************************************************************/
#ifdef CONFIG_MTD_SMART
# warning FlexNVM does not support back-to-back programming \
thus SmartFS willt not work
#endif
/******************************************************************************
* Private Data
******************************************************************************/
union fccob_flash_addr
{
uint32_t addr;
struct
{
uint8_t fccob3;
uint8_t fccob2;
uint8_t fccob1;
uint8_t pad;
} fccobs;
};
/******************************************************************************
* Private Functions
******************************************************************************/
static inline void wait_ftfc_ready()
{
while ((getreg8(S32K1XX_FTFC_FSTAT) & FTTC_FSTAT_CCIF) == 0)
{
/* Busy */
}
}
static uint32_t execute_ftfc_command()
{
uint8_t regval;
uint32_t retval;
/* Clear CCIF to launch command */
regval = getreg8(S32K1XX_FTFC_FSTAT);
regval |= FTTC_FSTAT_CCIF;
putreg8(regval, S32K1XX_FTFC_FSTAT);
wait_ftfc_ready();
retval = getreg8(S32K1XX_FTFC_FSTAT);
if (retval & (FTTC_FSTAT_MGSTAT0 | FTTC_FSTAT_FPVIOL |
FTTC_FSTAT_ACCERR | FTTC_FSTAT_RDCOLERR))
{
return retval; /* Error has occured */
}
else
{
return 0; /* success */
}
}
/******************************************************************************
* Public Functions
******************************************************************************/
/******************************************************************************
* Name: up_progmem_neraseblocks
*
* Description:
* Return number of erase blocks
*
******************************************************************************/
size_t up_progmem_neraseblocks(void)
{
return S32K1XX_PROGMEM_SECTOR_COUNT;
}
/******************************************************************************
* Name: up_progmem_isuniform
*
* Description:
* Is program memory uniform or page size differs?
*
******************************************************************************/
bool up_progmem_isuniform(void)
{
return true;
}
/******************************************************************************
* Name: up_progmem_pagesize
*
* Description:
* Return read/write page size
*
******************************************************************************/
size_t up_progmem_pagesize(size_t page)
{
return (size_t)S32K1XX_PROGMEM_PAGE_SIZE;
}
/******************************************************************************
* Name: up_progmem_erasesize
*
* Description:
* Return erase block size
*
******************************************************************************/
size_t up_progmem_erasesize(size_t block)
{
return (size_t)S32K1XX_PROGMEM_BLOCK_SECTOR_SIZE;
}
/******************************************************************************
* Name: up_progmem_getpage
*
* Description:
* Address to read/write page conversion
*
* Input Parameters:
* addr - Address with or without flash offset (absolute or aligned to page0)
*
* Returned Value:
* Page or negative value on error. The following errors are reported
* (errno is not set!):
*
* -EFAULT: On invalid address
*
******************************************************************************/
ssize_t up_progmem_getpage(size_t addr)
{
if (addr >= S32K1XX_PROGMEM_START_ADDR)
{
addr -= S32K1XX_PROGMEM_START_ADDR;
}
return (size_t)(addr / S32K1XX_PROGMEM_PAGE_SIZE);
}
/******************************************************************************
* Name: up_progmem_getaddress
*
* Description:
* Read/write page to address conversion
*
* Input Parameters:
* page - page index
*
* Returned Value:
* Base address of given page, SIZE_MAX if page index is not valid.
*
******************************************************************************/
size_t up_progmem_getaddress(size_t page)
{
return (size_t)(S32K1XX_PROGMEM_START_ADDR
+ (page * S32K1XX_PROGMEM_PAGE_SIZE));
}
/******************************************************************************
* Name: up_progmem_eraseblock
*
* Description:
* Erase selected block.
*
* Input Parameters:
* block - The erase block index to be erased.
*
* Returned Value:
* block size or negative value on error. The following errors are reported
* (errno is not set!):
*
* -EFAULT: On invalid page
* -EIO: On unsuccessful erase
* -EROFS: On access to write protected area
* -EACCES: Insufficient permissions (read/write protected)
* -EPERM: If operation is not permitted due to some other constraints
* (i.e. some internal block is not running etc.)
*
******************************************************************************/
ssize_t up_progmem_eraseblock(size_t block)
{
union fccob_flash_addr dest;
dest.addr = (block * S32K1XX_PROGMEM_BLOCK_SECTOR_SIZE) + 0x800000;
wait_ftfc_ready();
/* Clear FSTAT error bits */
putreg8(FTTC_FSTAT_FPVIOL | FTTC_FSTAT_ACCERR | FTTC_FSTAT_RDCOLERR,
S32K1XX_FTFC_FSTAT);
/* Set FTFC command */
putreg8(S32K1XX_FTFC_ERASE_SECTOR, S32K1XX_FTFC_FCCOB0);
/* Destination address of sector to erase */
putreg8(dest.fccobs.fccob1, S32K1XX_FTFC_FCCOB1);
putreg8(dest.fccobs.fccob2, S32K1XX_FTFC_FCCOB2);
putreg8(dest.fccobs.fccob3, S32K1XX_FTFC_FCCOB3);
if (execute_ftfc_command() & (FTTC_FSTAT_MGSTAT0 | FTTC_FSTAT_FPVIOL |
FTTC_FSTAT_ACCERR | FTTC_FSTAT_RDCOLERR))
{
return -EIO; /* Error has occured */
}
return (ssize_t)S32K1XX_PROGMEM_BLOCK_SECTOR_SIZE;
}
/******************************************************************************
* Name: up_progmem_ispageerased
*
* Description:
* Checks whether page is erased
*
* Input Parameters:
* page - The erase page index to be checked.
*
* Returned Value:
* Returns number of bytes NOT erased or negative value on error. If it
* returns zero then complete page is erased.
*
* The following errors are reported:
* -EFAULT: On invalid page
*
******************************************************************************/
ssize_t up_progmem_ispageerased(size_t page)
{
const uint8_t *p;
int i;
if (page >= S32K1XX_PROGMEM_PAGE_COUNT)
{
return -EFAULT;
}
p = (const uint8_t *)up_progmem_getaddress(page);
for (i = 0; i < S32K1XX_PROGMEM_PAGE_SIZE; i++)
{
if (p[i] != 0xff)
{
break;
}
}
return (ssize_t)(S32K1XX_PROGMEM_PAGE_SIZE - i);
}
/******************************************************************************
* Name: up_progmem_write
*
* Description:
* Program data at given address
*
* Note: this function is not limited to single page and nor it requires
* the address be aligned inside the page boundaries.
*
* Input Parameters:
* addr - Address with or without flash offset
* buf - Pointer to buffer
* count - Number of bytes to write
*
* Returned Value:
* Bytes written or negative value on error. The following errors are
* reported (errno is not set!)
*
* EINVAL: If count is not aligned with the flash boundaries (i.e.
* some MCU's require per half-word or even word access)
* EFAULT: On invalid address
* EIO: On unsuccessful write, do note when this occurs the complete
* flash sector is deemed to be unreadable and a read will most
* likely result in a hard fault.
* EROFS: On access to write protected area
* EACCES: Insufficient permissions (read/write protected)
* EPERM: If operation is not permitted due to some other constraints
* (i.e. some internal block is not running etc.)
*
******************************************************************************/
ssize_t up_progmem_write(size_t addr, FAR const void *buf, size_t count)
{
union fccob_flash_addr dest;
uint32_t i;
uint32_t j;
uint8_t *src;
if (addr >= S32K1XX_PROGMEM_START_ADDR)
{
addr -= S32K1XX_PROGMEM_START_ADDR;
}
if (count % S32K1XX_PROGMEM_DFLASH_WRITE_UNIT_SIZE != 0)
{
return -EINVAL;
}
src = (uint8_t *)buf;
dest.addr = addr + 0x800000;
for (i = 0; i < count / S32K1XX_PROGMEM_DFLASH_WRITE_UNIT_SIZE ; i++)
{
wait_ftfc_ready();
/* Clear FSTAT error bits */
putreg8(FTTC_FSTAT_FPVIOL | FTTC_FSTAT_ACCERR | FTTC_FSTAT_RDCOLERR,
S32K1XX_FTFC_FSTAT);
/* Set FTFC command */
putreg8(S32K1XX_FTFC_PROGRAM_PHRASE, S32K1XX_FTFC_FCCOB0);
/* Destination address */
putreg8(dest.fccobs.fccob1, S32K1XX_FTFC_FCCOB1);
putreg8(dest.fccobs.fccob2, S32K1XX_FTFC_FCCOB2);
putreg8(dest.fccobs.fccob3, S32K1XX_FTFC_FCCOB3);
/* Write data */
for (j = 0; j < S32K1XX_PROGMEM_DFLASH_WRITE_UNIT_SIZE; j++)
{
putreg8(src[j], S32K1XX_FTFC_BASE + j + 0x8);
}
if (execute_ftfc_command() & (FTTC_FSTAT_MGSTAT0 | FTTC_FSTAT_FPVIOL |
FTTC_FSTAT_ACCERR | FTTC_FSTAT_RDCOLERR))
{
return -EIO; /* Error has occured */
}
dest.addr = dest.addr + S32K1XX_PROGMEM_DFLASH_WRITE_UNIT_SIZE;
src = src + S32K1XX_PROGMEM_DFLASH_WRITE_UNIT_SIZE;
}
return count;
}
void s32k1xx_progmem_init()
{
/* Disable D-Flash Cache */
putreg32(0xc706b030, S32K1XX_MSCM_BASE + 0x404);
/* Setup D-flash partitioning */
putreg8(S32K1XX_FTFC_PROGRAM_PARTITION, S32K1XX_FTFC_FCCOB0); /* Command */
putreg8(0x0, S32K1XX_FTFC_FCCOB1); /* CSEc key size */
putreg8(0x0, S32K1XX_FTFC_FCCOB2); /* uSFE */
putreg8(0x0, S32K1XX_FTFC_FCCOB3); /* Disable FlexRAM EEE */
putreg8(0xf, S32K1XX_FTFC_FCCOB4); /* EEE Partition code */
putreg8(0x0, S32K1XX_FTFC_FCCOB5); /* DE Partition code */
execute_ftfc_command();
}

95
arch/arm/src/s32k1xx/s32k1xx_progmem.h Normal file
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@ -0,0 +1,95 @@
/******************************************************************************
* arch/arm/src/s32k1xx/s32k1xx_progmem.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ARCH_ARM_SRC_S32K1XX_PROGMEM_H
#define __ARCH_ARM_SRC_S32K1XX_PROGMEM_H
/******************************************************************************
* Included Files
******************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "up_internal.h"
#include "s32k1xx_config.h"
/******************************************************************************
* Pre-processor Definitions
******************************************************************************/
#define DFLASH_SIZE CONFIG_PROGMEM_SIZE
#if (DFLASH_SIZE % 2) == 1
# error "Progmem size has to be a multiple of 2"
#endif
#if defined(CONFIG_ARCH_CHIP_S32K14X) && (DFLASH_SIZE > 64)
# error "Progmem size is bigger than FlexNVM size"
#endif
#if defined(CONFIG_ARCH_CHIP_S32K11X) && (DFLASH_SIZE > 32)
# error "Progmem size is bigger than FlexNVM size"
#endif
/* Base address of the flash segment used for progmem. */
#define S32K1XX_PROGMEM_START_ADDR 0x10000000
#define S32K1XX_PROGMEM_BLOCK_COUNT 1
#define S32K1XX_PROGMEM_BLOCK_SIZE DFLASH_SIZE * 1024
#define S32K1XX_PROGMEM_BLOCK_SECTOR_SIZE 2048
#define S32K1XX_PROGMEM_PAGE_SIZE 8
#define S32K1XX_PROGMEM_SECTOR_COUNT S32K1XX_PROGMEM_BLOCK_SIZE / S32K1XX_PROGMEM_BLOCK_SECTOR_SIZE
#define S32K1XX_PROGMEM_PAGE_COUNT (S32K1XX_PROGMEM_BLOCK_SIZE / S32K1XX_PROGMEM_PAGE_SIZE)
#define S32K1XX_PROGMEM_DFLASH_WRITE_UNIT_SIZE 8
/******************************************************************************
* Public Function Prototypes
******************************************************************************/
void s32k1xx_progmem_init();
#endif /* __ARCH_ARM_SRC_S32K1XX_PROGMEM_H */

85
arch/arm/src/s32k1xx/s32k1xx_rtc.c
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@ -157,11 +157,11 @@ int up_rtc_initialize(void)
putreg32(regval, S32K1XX_RTC_CR);
/* Set LPO_1KHZ clock source */
/* Increment on 32.768Khz clock */
regval = getreg32(S32K1XX_RTC_CR);
regval |= RTC_CR_LPOS;
regval &= ~RTC_CR_LPOS;
putreg32(regval, S32K1XX_RTC_CR);
@ -181,6 +181,18 @@ int up_rtc_initialize(void)
putreg32(regval, S32K1XX_RTC_CR);
regval = getreg32(S32K1XX_RTC_SR);
if (regval & RTC_SR_TIF)
{
regval &= ~RTC_SR_TCE;
putreg32(regval, S32K1XX_RTC_SR);
/* Write TSR register to clear invalid */
putreg32(0x0, S32K1XX_RTC_TSR);
}
/* Enable the rtc */
s32k1xx_rtc_enable();
@ -207,7 +219,7 @@ int up_rtc_initialize(void)
* The current time in seconds
*
****************************************************************************/
#ifndef CONFIG_RTC_HIRES
time_t up_rtc_time(void)
{
uint32_t regval;
@ -217,6 +229,55 @@ time_t up_rtc_time(void)
return (uint32_t) (regval);
}
#endif
/****************************************************************************
* Name: up_rtc_gettime
*
* Description:
* Get the current time from the high resolution RTC clock/counter. This
* interface is only supported by the high-resolution RTC/counter hardware
* implementation. It is used to replace the system timer.
*
* Input Parameters:
* tp - The location to return the high resolution time value.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_RTC_HIRES
int up_rtc_gettime(FAR struct timespec *tp)
{
irqstate_t flags;
uint32_t seconds;
uint32_t prescaler;
uint32_t prescaler2;
/* Get prescaler and seconds register. this is in a loop which ensures that
* registers will be re-read if during the reads the prescaler has
* wrapped-around.
*/
flags = enter_critical_section();
do
{
prescaler = getreg32(S32K1XX_RTC_TPR);
seconds = getreg32(S32K1XX_RTC_TSR);
prescaler2 = getreg32(S32K1XX_RTC_TPR);
}
while (prescaler > prescaler2);
leave_critical_section(flags);
/* Build seconds + nanoseconds from seconds and prescaler register */
tp->tv_sec = seconds;
tp->tv_nsec = prescaler * (1000000000 / CONFIG_RTC_FREQUENCY);
return OK;
}
#endif
/****************************************************************************
* Name: up_rtc_settime
@ -237,12 +298,28 @@ int up_rtc_settime(FAR const struct timespec *ts)
{
DEBUGASSERT(ts != NULL);
irqstate_t flags;
uint32_t seconds;
uint32_t prescaler;
seconds = ts->tv_sec;
#ifdef CONFIG_RTC_HIRES
prescaler = ts->tv_nsec * (CONFIG_RTC_FREQUENCY / 1000000000);
#else
prescaler = 0;
#endif
flags = enter_critical_section();
s32k1xx_rtc_disable();
putreg32((uint32_t)ts->tv_sec, S32K1XX_RTC_TSR);
putreg32(prescaler, S32K1XX_RTC_TPR); /* Always write prescaler first */
putreg32(seconds, S32K1XX_RTC_TSR);
s32k1xx_rtc_enable();
leave_critical_section(flags);
return OK;
}

8
arch/arm/src/s32k1xx/s32k1xx_rtc.h
View File

@ -58,14 +58,6 @@
# error CONFIG_RTC_PERIODIC should not be selected with this driver
# endif
/* REVISIT: This is probably supportable. The 47 bit timer does have
* accuracy greater than 1 second.
*/
# ifdef CONFIG_RTC_HIRES
# error CONFIG_RTC_PERIODIC should not be selected with this driver
# endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/

8
arch/arm/src/s32k1xx/s32k1xx_start.c
View File

@ -65,6 +65,10 @@
#include "hardware/s32k1xx_mpu.h"
#endif
#ifdef CONFIG_S32K1XX_PROGMEM
#include "s32k1xx_progmem.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@ -353,6 +357,10 @@ void __start(void)
#endif
showprogress('E');
#ifdef CONFIG_S32K1XX_PROGMEM
s32k1xx_progmem_init();
#endif
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss

11
boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_bringup.c
View File

@ -143,5 +143,16 @@ int s32k1xx_bringup(void)
#endif
#endif
#ifdef CONFIG_S32K1XX_PROGMEM
FAR struct mtd_dev_s *mtd;
int minor = 0;
mtd = progmem_initialize();
if (!mtd)
{
syslog(LOG_ERR, "ERROR: progmem_initialize failed\n");
}
#endif
return ret;
}

2
boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_clockconfig.c
View File

@ -165,7 +165,7 @@ const struct clock_configuration_s g_initial_clkconfig =
},
.lpoclk = /* Low Power Clock configuration. */
{
.rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
.rtc_source = SIM_RTCCLK_SEL_LPO_32K, /* RTCCLKSEL */
.lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
.initialize = true, /* Initialize */
.lpo32k = true, /* LPO32KCLKEN */

29
boards/arm/s32k1xx/rddrone-uavcan146/configs/nsh/defconfig
View File

@ -69,3 +69,32 @@ CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
CONFIG_SYSTEM_SPITOOL=y
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_S32K1XX_FLEXCAN0=y
CONFIG_S32K1XX_FLEXCAN1=y
CONFIG_NET=y
CONFIG_NET_ETHERNET=n
CONFIG_NET_IPv4=n
CONFIG_ARCH_HAVE_NET=y
CONFIG_NET_READAHEAD=y
CONFIG_NSOCKET_DESCRIPTORS=8
CONFIG_NET_NACTIVESOCKETS=16
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_CANPROTO_OPTIONS=y
CONFIG_NET_CAN=y
CONFIG_NET_CAN_HAVE_TX_DEADLINE=y
CONFIG_CAN_CONNS=4
CONFIG_NET_CAN_SOCK_OPTS=y
CONFIG_NET_CAN_RAW_FILTER_MAX=32
CONFIG_NET_TIMESTAMP=y
CONFIG_NET_CMSG=y
CONFIG_NETDEV_IFINDEX=y
CONFIG_NSH_NETINIT=y
CONFIG_SCHED_LPWORK=y
CONFIG_SCHED_LPNTHREADS=1
CONFIG_SCHED_LPWORKPRIORITY=100
CONFIG_SCHED_LPWORKSTACKSIZE=2048
CONFIG_S32K1XX_RTC=y
CONFIG_RTC=y
CONFIG_RTC_HIRES=y
CONFIG_RTC_FREQUENCY=32768
CONFIG_SIG_DEFAULT=y

10
boards/arm/s32k1xx/rddrone-uavcan146/include/board.h
View File

@ -150,4 +150,14 @@
#define PIN_LPI2C0_SCL PIN_LPI2C0_SCL_2 /* PTA3 */
#define PIN_LPI2C0_SDA PIN_LPI2C0_SDA_2 /* PTA2 */
/* CAN selections ***********************************************************/
#define PIN_CAN0_TX PIN_CAN0_TX_4 /* PTE5 */
#define PIN_CAN0_RX PIN_CAN0_RX_4 /* PTE4 */
#define PIN_CAN0_ENABLE (GPIO_OUTPUT | PIN_PORTE | PIN11 )
#define CAN0_ENABLE_OUT 0
#define PIN_CAN1_TX PIN_CAN1_TX_1 /* PTA13 */
#define PIN_CAN1_RX PIN_CAN1_RX_1 /* PTA12 */
#define PIN_CAN1_ENABLE (GPIO_OUTPUT | PIN_PORTE | PIN10 )
#define CAN1_ENABLE_OUT 0
#endif /* __BOARDS_ARM_RDDRONE_UAVCAN146_INCLUDE_BOARD_H */

10
boards/arm/s32k1xx/rddrone-uavcan146/src/rddrone-uavcan146.h
View File

@ -69,14 +69,12 @@
#define GPIO_LED_G (PIN_PTD16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
#define GPIO_LED_B (PIN_PTD0 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
/* Buttons. The RDDRONE-UAVCAN146 supports two buttons:
/* Buttons. The RDDRONE-UAVCAN146 supports one button:
*
* SW2 PTC12
* SW3 PTC13
* SW3 PTC14
*/
#define GPIO_SW2 (PIN_PTC12 | PIN_INT_BOTH)
#define GPIO_SW3 (PIN_PTC13 | PIN_INT_BOTH)
#define GPIO_SW3 (PIN_PTC14 | PIN_INT_BOTH)
/* SPI chip selects */
@ -86,7 +84,7 @@
/* Count of peripheral clock user configurations */
#define NUM_OF_PERIPHERAL_CLOCKS_0 11
#define NUM_OF_PERIPHERAL_CLOCKS_0 12
/****************************************************************************
* Public Types

11
boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c
View File

@ -140,5 +140,16 @@ int s32k1xx_bringup(void)
#endif
#endif
#ifdef CONFIG_S32K1XX_PROGMEM
FAR struct mtd_dev_s *mtd;
int minor = 0;
mtd = progmem_initialize();
if (!mtd)
{
syslog(LOG_ERR, "ERROR: progmem_initialize failed\n");
}
#endif
return ret;
}

17
boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_buttons.c
View File

@ -33,10 +33,9 @@
*
****************************************************************************/
/* The RDDRONE-UAVCAN146 supports two buttons:
/* The RDDRONE-UAVCAN146 supports one button:
*
* SW2 PTC12
* SW3 PTC13
* SW3 PTC14
*/
/****************************************************************************
@ -77,7 +76,6 @@ uint32_t board_button_initialize(void)
{
/* Configure the GPIO pins as interrupting inputs. */
s32k1xx_pinconfig(GPIO_SW2);
s32k1xx_pinconfig(GPIO_SW3);
return NUM_BUTTONS;
}
@ -90,11 +88,6 @@ uint32_t board_buttons(void)
{
uint32_t ret = 0;
if (s32k1xx_gpioread(GPIO_SW2))
{
ret |= BUTTON_SW2_BIT;
}
if (s32k1xx_gpioread(GPIO_SW3))
{
ret |= BUTTON_SW3_BIT;
@ -133,11 +126,7 @@ int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
/* Map the button id to the GPIO bit set. */
if (id == BUTTON_SW2)
{
pinset = GPIO_SW2;
}
else if (id == BUTTON_SW3)
if (id == BUTTON_SW3)
{
pinset = GPIO_SW3;
}

2
boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_clockconfig.c
View File

@ -165,7 +165,7 @@ const struct clock_configuration_s g_initial_clkconfig =
},
.lpoclk = /* Low Power Clock configuration. */
{
.rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
.rtc_source = SIM_RTCCLK_SEL_LPO_32K, /* RTCCLKSEL */
.lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
.initialize = true, /* Initialize */
.lpo32k = true, /* LPO32KCLKEN */

12
boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_periphclocks.c
View File

@ -73,7 +73,7 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
{
{
.clkname = FLEXCAN0_CLK,
#ifdef CONFIG_S32K1XX_FLEXCAN
#ifdef CONFIG_S32K1XX_FLEXCAN0
.clkgate = true,
#else
.clkgate = false,
@ -81,7 +81,7 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
},
{
.clkname = FLEXCAN1_CLK,
#ifdef CONFIG_S32K1XX_FLEXCAN
#ifdef CONFIG_S32K1XX_FLEXCAN1
.clkgate = true,
#else
.clkgate = false,
@ -143,6 +143,14 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
.clkname = PORTE_CLK,
.clkgate = true,
},
{
.clkname = RTC0_CLK,
#ifdef CONFIG_S32K1XX_RTC
.clkgate = true,
#else
.clkgate = false,
#endif
},
};
/****************************************************************************

11
boards/arm/s32k1xx/s32k118evb/src/s32k1xx_bringup.c
View File

@ -105,5 +105,16 @@ int s32k1xx_bringup(void)
}
#endif
#ifdef CONFIG_S32K1XX_PROGMEM
FAR struct mtd_dev_s *mtd;
int minor = 0;
mtd = progmem_initialize();
if (!mtd)
{
syslog(LOG_ERR, "ERROR: progmem_initialize failed\n");
}
#endif
return ret;
}

11
boards/arm/s32k1xx/s32k144evb/src/s32k1xx_bringup.c
View File

@ -137,5 +137,16 @@ int s32k1xx_bringup(void)
}
#endif
#ifdef CONFIG_S32K1XX_PROGMEM
FAR struct mtd_dev_s *mtd;
int minor = 0;
mtd = progmem_initialize();
if (!mtd)
{
syslog(LOG_ERR, "ERROR: progmem_initialize failed\n");
}
#endif
return ret;
}

2
boards/arm/s32k1xx/s32k144evb/src/s32k1xx_clockconfig.c
View File

@ -165,7 +165,7 @@ const struct clock_configuration_s g_initial_clkconfig =
},
.lpoclk = /* Low Power Clock configuration. */
{
.rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
.rtc_source = SIM_RTCCLK_SEL_LPO_32K, /* RTCCLKSEL */
.lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
.initialize = true, /* Initialize */
.lpo32k = true, /* LPO32KCLKEN */

11
boards/arm/s32k1xx/s32k146evb/src/s32k1xx_bringup.c
View File

@ -137,5 +137,16 @@ int s32k1xx_bringup(void)
}
#endif
#ifdef CONFIG_S32K1XX_PROGMEM
FAR struct mtd_dev_s *mtd;
int minor = 0;
mtd = progmem_initialize();
if (!mtd)
{
syslog(LOG_ERR, "ERROR: progmem_initialize failed\n");
}
#endif
return ret;
}

2
boards/arm/s32k1xx/s32k146evb/src/s32k1xx_clockconfig.c
View File

@ -165,7 +165,7 @@ const struct clock_configuration_s g_initial_clkconfig =
},
.lpoclk = /* Low Power Clock configuration. */
{
.rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
.rtc_source = SIM_RTCCLK_SEL_LPO_32K, /* RTCCLKSEL */
.lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
.initialize = true, /* Initialize */
.lpo32k = true, /* LPO32KCLKEN */

8
boards/arm/s32k1xx/s32k148evb/include/board.h
View File

@ -133,4 +133,12 @@
#define PIN_LPUART1_RX PIN_LPUART1_RX_1 /* PTC6 */
#define PIN_LPUART1_TX PIN_LPUART1_TX_1 /* PTC7 */
/* CAN selections ***********************************************************/
#define PIN_CAN0_TX PIN_CAN0_TX_1
#define PIN_CAN0_RX PIN_CAN0_RX_1
#define PIN_CAN1_TX PIN_CAN1_TX_1
#define PIN_CAN1_RX PIN_CAN1_RX_1
#define PIN_CAN2_TX PIN_CAN2_TX_1
#define PIN_CAN2_RX PIN_CAN2_RX_1
#endif /* __BOARDS_ARM_S32K148EVB_INCLUDE_BOARD_H */

2
boards/arm/s32k1xx/s32k148evb/src/s32k1xx_clockconfig.c
View File

@ -165,7 +165,7 @@ const struct clock_configuration_s g_initial_clkconfig =
},
.lpoclk = /* Low Power Clock configuration. */
{
.rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
.rtc_source = SIM_RTCCLK_SEL_LPO_32K, /* RTCCLKSEL */
.lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
.initialize = true, /* Initialize */
.lpo32k = true, /* LPO32KCLKEN */