From ff76ef0725fad91338831329a06fa4ff612ec856 Mon Sep 17 00:00:00 2001 From: Peter van der Perk Date: Mon, 15 Jun 2020 10:24:23 +0200 Subject: [PATCH] s32k1xx: Added FlexCAN driver with SocketCAN support --- arch/arm/src/s32k1xx/Kconfig | 164 ++ arch/arm/src/s32k1xx/Make.defs | 8 + .../src/s32k1xx/hardware/s32k1xx_flexcan.h | 103 +- arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h | 143 ++ arch/arm/src/s32k1xx/s32k1xx_flexcan.c | 1901 +++++++++++++++++ arch/arm/src/s32k1xx/s32k1xx_flexcan.h | 115 + arch/arm/src/s32k1xx/s32k1xx_progmem.c | 424 ++++ arch/arm/src/s32k1xx/s32k1xx_progmem.h | 95 + arch/arm/src/s32k1xx/s32k1xx_rtc.c | 85 +- arch/arm/src/s32k1xx/s32k1xx_rtc.h | 8 - arch/arm/src/s32k1xx/s32k1xx_start.c | 8 + .../rddrone-uavcan144/src/s32k1xx_bringup.c | 11 + .../src/s32k1xx_clockconfig.c | 2 +- .../rddrone-uavcan146/configs/nsh/defconfig | 29 + .../s32k1xx/rddrone-uavcan146/include/board.h | 10 + .../rddrone-uavcan146/src/rddrone-uavcan146.h | 10 +- .../rddrone-uavcan146/src/s32k1xx_bringup.c | 11 + .../rddrone-uavcan146/src/s32k1xx_buttons.c | 17 +- .../src/s32k1xx_clockconfig.c | 2 +- .../src/s32k1xx_periphclocks.c | 12 +- .../s32k1xx/s32k118evb/src/s32k1xx_bringup.c | 11 + .../s32k1xx/s32k144evb/src/s32k1xx_bringup.c | 11 + .../s32k144evb/src/s32k1xx_clockconfig.c | 2 +- .../s32k1xx/s32k146evb/src/s32k1xx_bringup.c | 11 + .../s32k146evb/src/s32k1xx_clockconfig.c | 2 +- boards/arm/s32k1xx/s32k148evb/include/board.h | 8 + .../s32k148evb/src/s32k1xx_clockconfig.c | 2 +- 27 files changed, 3136 insertions(+), 69 deletions(-) create mode 100644 arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h create mode 100644 arch/arm/src/s32k1xx/s32k1xx_flexcan.c create mode 100644 arch/arm/src/s32k1xx/s32k1xx_flexcan.h create mode 100644 arch/arm/src/s32k1xx/s32k1xx_progmem.c create mode 100644 arch/arm/src/s32k1xx/s32k1xx_progmem.h diff --git a/arch/arm/src/s32k1xx/Kconfig b/arch/arm/src/s32k1xx/Kconfig index 63e0cd9581..e3ef9bd084 100644 --- a/arch/arm/src/s32k1xx/Kconfig +++ b/arch/arm/src/s32k1xx/Kconfig @@ -27,6 +27,7 @@ config ARCH_CHIP_S32K118 config ARCH_CHIP_S32K142 bool "S32K142" select ARCH_CHIP_S32K14X + select S32K1XX_HAVE_FLEXCAN1 ---help--- Cortex-M4F, 256Kb FLASH, 32Kb RAM incl. 4Kb FlexRAM @@ -34,6 +35,8 @@ config ARCH_CHIP_S32K144 bool "S32K144" select ARCH_CHIP_S32K14X select S32K1XX_HAVE_LPSPI2 + select S32K1XX_HAVE_FLEXCAN1 + select S32K1XX_HAVE_FLEXCAN2 ---help--- Cortex-M4F, 512Kb FLASH, 64Kb RAM incl. 4Kb FlexRAM @@ -41,6 +44,8 @@ config ARCH_CHIP_S32K146 bool "S32K146" select ARCH_CHIP_S32K14X select S32K1XX_HAVE_LPSPI2 + select S32K1XX_HAVE_FLEXCAN1 + select S32K1XX_HAVE_FLEXCAN2 ---help--- Cortex-M4F, 1Mb FLASH, 128Kb RAM incl. 4Kb FlexRAM @@ -51,6 +56,8 @@ config ARCH_CHIP_S32K148 select S32K1XX_HAVE_LPI2C1 select S32K1XX_HAVE_LPSPI2 select S32K1XX_HAVE_SAI + select S32K1XX_HAVE_FLEXCAN1 + select S32K1XX_HAVE_FLEXCAN2 ---help--- Cortex-M4F, 2Mb FLASH, 256Kb RAM incl. 4Kb FlexRAM @@ -110,6 +117,14 @@ config S32K1XX_HAVE_LPSPI1 config S32K1XX_HAVE_LPSPI2 bool default n + +config S32K1XX_HAVE_FLEXCAN1 + bool + default n + +config S32K1XX_HAVE_FLEXCAN2 + bool + default n config S32K1XX_HAVE_QSPI bool @@ -137,6 +152,11 @@ config S32K1XX_LPSPI bool default n +config S32K1XX_FLEXCAN + bool + select NET_CAN_HAVE_CANFD + default n + # Peripheral Selection menu "S32K1XX Peripheral Selection" @@ -150,6 +170,26 @@ config S32K1XX_ENET default n depends on S32K1XX_HAVE_ENET +config S32K1XX_FLEXCAN0 + bool "FLEXCAN0" + select S32K1XX_FLEXCAN + select NET_CAN_HAVE_TX_DEADLINE + default n + +config S32K1XX_FLEXCAN1 + bool "FLEXCAN1" + select S32K1XX_FLEXCAN + select NET_CAN_HAVE_TX_DEADLINE + default n + depends on S32K1XX_HAVE_FLEXCAN1 + +config S32K1XX_FLEXCAN2 + bool "FLEXCAN2" + select S32K1XX_FLEXCAN + select NET_CAN_HAVE_TX_DEADLINE + default n + depends on S32K1XX_HAVE_FLEXCAN2 + menuconfig S32K1XX_LPI2C0 bool "LPI2C0" default n @@ -205,6 +245,15 @@ config S32K1XX_LPUART2 config S32K1XX_RTC bool "RTC" default n + +config S32K1XX_PROGMEM + bool PROGMEM + default n + select ARCH_HAVE_PROGMEM + depends on (ARCH_CHIP_S32K11X || (ARCH_CHIP_S32K14X && !ARCH_CHIP_S32K148) ) + ---help--- + Use the FlexNVM 32/64 KB of d-flash memory as a + Memory-Technology-Device (MTD). endmenu # S32K1XX Peripheral Selection @@ -453,4 +502,119 @@ config S32K1XX_ENET_PHYINIT endmenu # S32K1XX_ENET +menu "FLEXCAN0 Configuration" + depends on S32K1XX_FLEXCAN0 + +config FLEXCAN0_BITRATE + int "CAN bitrate" + depends on !NET_CAN_CANFD + default 1000000 + +config FLEXCAN0_SAMPLEP + int "CAN sample point" + depends on !NET_CAN_CANFD + default 80 + +config FLEXCAN0_ARBI_BITRATE + int "CAN FD Arbitration phase bitrate" + depends on NET_CAN_CANFD + default 1000000 + +config FLEXCAN0_ARBI_SAMPLEP + int "CAN FD Arbitration phase sample point" + depends on NET_CAN_CANFD + default 80 + +config FLEXCAN0_DATA_BITRATE + int "CAN FD Arbitration phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +config FLEXCAN0_DATA_SAMPLEP + int "CAN FD Arbitration phase sample point" + depends on NET_CAN_CANFD + default 90 + +endmenu # S32K1XX_FLEXCAN0 + +menu "FLEXCAN1 Configuration" + depends on S32K1XX_FLEXCAN1 + +config FLEXCAN1_BITRATE + int "CAN bitrate" + depends on !NET_CAN_CANFD + default 1000000 + +config FLEXCAN1_SAMPLEP + int "CAN sample point" + depends on !NET_CAN_CANFD + default 80 + +config FLEXCAN1_ARBI_BITRATE + int "CAN FD Arbitration phase bitrate" + depends on NET_CAN_CANFD + default 1000000 + +config FLEXCAN1_ARBI_SAMPLEP + int "CAN FD Arbitration phase sample point" + depends on NET_CAN_CANFD + default 80 + +config FLEXCAN1_DATA_BITRATE + int "CAN FD Arbitration phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +config FLEXCAN1_DATA_SAMPLEP + int "CAN FD Arbitration phase sample point" + depends on NET_CAN_CANFD + default 90 + +endmenu # S32K1XX_FLEXCAN1 + +menu "FLEXCAN2 Configuration" + depends on S32K1XX_FLEXCAN2 + +config FLEXCAN2_BITRATE + int "CAN bitrate" + depends on !NET_CAN_CANFD + default 1000000 + +config FLEXCAN2_SAMPLEP + int "CAN sample point" + depends on !NET_CAN_CANFD + default 80 + +config FLEXCAN2_ARBI_BITRATE + int "CAN FD Arbitration phase bitrate" + depends on NET_CAN_CANFD + default 1000000 + +config FLEXCAN2_ARBI_SAMPLEP + int "CAN FD Arbitration phase sample point" + depends on NET_CAN_CANFD + default 80 + +config FLEXCAN2_DATA_BITRATE + int "CAN FD Arbitration phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +config FLEXCAN2_DATA_SAMPLEP + int "CAN FD Arbitration phase sample point" + depends on NET_CAN_CANFD + default 90 + +endmenu # S32K1XX_FLEXCAN0 + +menu "PROGMEM Configuration" + depends on S32K1XX_PROGMEM + +config PROGMEM_SIZE + int "Progmem size (KB)" + default 64 if ARCH_CHIP_S32K14X + default 32 if ARCH_CHIP_S32K11X + +endmenu + endif # ARCH_CHIP_S32K1XX diff --git a/arch/arm/src/s32k1xx/Make.defs b/arch/arm/src/s32k1xx/Make.defs index a06fa86992..05ac9dd187 100644 --- a/arch/arm/src/s32k1xx/Make.defs +++ b/arch/arm/src/s32k1xx/Make.defs @@ -87,10 +87,18 @@ ifeq ($(CONFIG_S32K1XX_ENET),y) CHIP_CSRCS += s32k1xx_enet.c endif +ifeq ($(CONFIG_S32K1XX_FLEXCAN),y) +CHIP_CSRCS += s32k1xx_flexcan.c +endif + ifeq ($(CONFIG_S32K1XX_RTC),y) CHIP_CSRCS += s32k1xx_rtc.c endif +ifeq ($(CONFIG_S32K1XX_PROGMEM),y) +CHIP_CSRCS += s32k1xx_progmem.c +endif + # Source files specific to the ARM CPU family and to the S32K1xx chip family ifeq ($(CONFIG_ARCH_CHIP_S32K11X),y) diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_flexcan.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_flexcan.h index fa9c36fe41..aba9b7f331 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_flexcan.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_flexcan.h @@ -66,8 +66,11 @@ #define S32K1XX_CAN_CRCR_OFFSET 0x0044 /* CRC Register */ #define S32K1XX_CAN_RXFGMASK_OFFSET 0x0048 /* Rx FIFO Global Mask Register */ #define S32K1XX_CAN_RXFIR_OFFSET 0x004c /* Rx FIFO Information Register */ +#define S32K1XX_CAN_CBT_OFFSET 0x0050 /* CAN Bit Timing register */ -#define S32K1XX_CAN_RXIMR_OFFSET(n) (0x0880 + ((n) << 2)) /* Rn Individual Mask Registers */ +#define S32K1XX_CAN_MB_OFFSET 0x0080 /* CAN MB register */ + +#define S32K1XX_CAN_RXIMR_OFFSET(n) (0x0880 + ((n) << 2)) # define S32K1XX_CAN_RXIMR0_OFFSET 0x0880 /* R0 Individual Mask Registers */ # define S32K1XX_CAN_RXIMR1_OFFSET 0x0884 /* R1 Individual Mask Registers */ # define S32K1XX_CAN_RXIMR2_OFFSET 0x0888 /* R2 Individual Mask Registers */ @@ -141,7 +144,7 @@ #define S32K1XX_CAN_FDCTRL_OFFSET 0x0c00 /* CAN FD Control register */ #define S32K1XX_CAN_FDCBT_OFFSET 0x0c04 /* CAN FD Bit Timing register */ -#define S32K1XX_CAN_FDCRC_OFFSET 0x0c08 /* CAN FD CRC register */ +#define S32K1XX_CAN_FDCRC_OFFSET 0x0c08 /* CAN FD CRC register */ /* Register Addresses ***************************************************************************************/ @@ -162,6 +165,11 @@ #define S32K1XX_CAN0_CRCR (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_CRCR_OFFSET) #define S32K1XX_CAN0_RXFGMASK (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_RXFGMASK_OFFSET) #define S32K1XX_CAN0_RXFIR (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_RXFIR_OFFSET) +#define S32K1XX_CAN0_CBT (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_CBT_OFFSET) +#define S32K1XX_CAN0_MB (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_MB_OFFSET) +#define S32K1XX_CAN0_FDCTRL (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_FDCTRL_OFFSET) +#define S32K1XX_CAN0_FDCBT (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_FDCBT_OFFSET) +#define S32K1XX_CAN0_FDCRC (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_FDCRC_OFFSET) #define S32K1XX_CAN0_RXIMR(n) (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_RXIMR_OFFSET(n)) # define S32K1XX_CAN0_RXIMR0 (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_RXIMR0_OFFSET) @@ -335,12 +343,15 @@ #define CAN_MCR_MAXMB_MASK (0x7f << CAN_MCR_MAXMB_SHIFT) /* Bit 7: Reserved */ #define CAN_MCR_IDAM_SHIFT (8) /* Bits 8-9: ID Acceptance Mode */ + #define CAN_MCR_IDAM_MASK (3 << CAN_MCR_IDAM_SHIFT) # define CAN_MCR_IDAM_FMTA (0 << CAN_MCR_IDAM_SHIFT) /* Format A: One full ID */ # define CAN_MCR_IDAM_FMTB (1 << CAN_MCR_IDAM_SHIFT) /* Format B: Two full (or partial) IDs */ # define CAN_MCR_IDAM_FMTC (2 << CAN_MCR_IDAM_SHIFT) /* Format C: Four partial IDs */ # define CAN_MCR_IDAM_FMTD (3 << CAN_MCR_IDAM_SHIFT) /* Format D: All frames rejected */ - /* Bits 10-11: Reserved */ + + /* Bit 10: Reserved */ +#define CAN_MCR_FDEN (1 << 11) /* Bit 11: CAN FD operation enable */ #define CAN_MCR_AEN (1 << 12) /* Bit 12: Abort Enable */ #define CAN_MCR_LPRIOEN (1 << 13) /* Bit 13: Local Priority Enable */ /* Bits 14-15: Reserved */ @@ -363,8 +374,7 @@ /* Control 1 Register */ -#define CAN_CTRL1_ROPSEG_SHIFT (0) /* Bits 0-2: Propagation Segment */ -#define CAN_CTRL1_ROPSEG_MASK (7 << CAN_CTRL1_ROPSEG_SHIFT) +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0x7) #define CAN_CTRL1_LOM (1 << 3) /* Bit 3: Listen-Only Mode */ #define CAN_CTRL1_LBUF (1 << 4) /* Bit 4: Lowest Buffer Transmitted First */ #define CAN_CTRL1_TSYN (1 << 5) /* Bit 5: Timer Sync */ @@ -377,14 +387,10 @@ #define CAN_CTRL1_CLKSRC (1 << 13) /* Bit 13: CAN Engine Clock Source */ #define CAN_CTRL1_ERRMSK (1 << 14) /* Bit 14: Error Mask */ #define CAN_CTRL1_BOFFMSK (1 << 15) /* Bit 15: Bus Off Mask */ -#define CAN_CTRL1_PSEG2_SHIFT (16) /* Bits 16-18: Phase Segment 2 */ -#define CAN_CTRL1_PSEG2_MASK (7 << CAN_CTRL1_PSEG2_SHIFT) -#define CAN_CTRL1_PSEG1_SHIFT (19) /* Bits 19-21: Phase Segment 1 */ -#define CAN_CTRL1_PSEG1_MASK (7 << CAN_CTRL1_PSEG1_SHIFT) -#define CAN_CTRL1_RJW_SHIFT (22) /* Bits 22-23: Resync Jump Width */ -#define CAN_CTRL1_RJW_MASK (3 << CAN_CTRL1_RJW_SHIFT) -#define CAN_CTRL1_PRESDIV_SHIFT (24) /* Bits 24-31: Prescaler Division Factor */ -#define CAN_CTRL1_PRESDIV_MASK (0xff << CAN_CTRL1_PRESDIV_SHIFT) +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0x70000) +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << 19)) & 0x380000) +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << 22)) & 0xC00000) +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << 24)) & 0xFF000000) /* Free Running Timer */ @@ -409,8 +415,8 @@ #define CAN_ECR_TXERRCNT_SHIFT (0) /* Bits 0-7: Transmit Error Counter */ #define CAN_ECR_TXERRCNT_MASK (0xff << CAN_ECR_TXERRCNT_SHIFT) #define CAN_ECR_RXERRCNT_SHIFT (8) /* Bits 8-15: Receive Error Counter */ -#define CAN_ECR_RXERRCNT_MASK (0xff << CAN_ECR_RXERRCNT_SHIFT) - /* Bits 16-31: Reserved */ +#define CAN_ECR_RXERRCNT_MASK (0xff << CAN_ECR_RXERRCNT_SHIFT) + /* Bits 16-31: Reserved */ /* Error and Status 1 Register */ @@ -419,13 +425,15 @@ #define CAN_ESR1_BOFFINT (1 << 2) /* Bit 2: 'Bus Off' Interrupt */ #define CAN_ESR1_RX (1 << 3) /* Bit 3: FlexCAN in Reception */ #define CAN_ESR1_FLTCONF_SHIFT (4) /* Bits 4-5: Fault Confinement State */ + #define CAN_ESR1_FLTCONF_MASK (3 << CAN_ESR1_FLTCONF_SHIFT) # define CAN_ESR1_FLTCONF_ACTV (0 << CAN_ESR1_FLTCONF_SHIFT) /* Error Active */ # define CAN_ESR1_FLTCONF_PASV (1 << CAN_ESR1_FLTCONF_SHIFT) /* Error Passive */ # define CAN_ESR1_FLTCONF_OFF (2 << CAN_ESR1_FLTCONF_SHIFT) /* Bus Off */ + #define CAN_ESR1_TX (1 << 6) /* Bit 6: FlexCAN in Transmission */ #define CAN_ESR1_IDLE (1 << 7) /* Bit 7: CAN bus is in IDLE state */ -#define CAN_ESR1_RXWRN (1 << 8) /* Bit 8: Rx Error Warning */ +#define CAN_ESR1_RXWRN (1 << 8) /* Bit 8: Rx Error Warning */ #define CAN_ESR1_TXWRN (1 << 9) /* Bit 9: TX Error Warning */ #define CAN_ESR1_STFERR (1 << 10) /* Bit 10: Stuffing Error */ #define CAN_ESR1_FRMERR (1 << 11) /* Bit 11: Form Error */ @@ -437,6 +445,7 @@ #define CAN_ESR1_TWRNINT (1 << 17) /* Bit 17: Tx Warning Interrupt Flag */ #define CAN_ESR1_SYNCH (1 << 18) /* Bit 18: CAN Synchronization Status */ /* Bits 19-31: Reserved */ + /* Interrupt Masks 2 Register */ #define CAN_IMASK2(n) (1 << (n)) /* Bit n: Buffer MBn Mask */ @@ -454,7 +463,13 @@ #define CAN_IFLAG1(n) (1 << (n)) /* Bit n: Buffer MBn Interrupt, n=0..4,8..31 */ /* Control 2 Register */ - /* Bits 0-15: Reserved */ + + /* Bits 0-10: Reserved */ +#define CAN_CTRL2_EDFLTDIS (1 << 11) /* Bit 11: Edge Filter Disable */ +#define CAN_CTRL2_ISOCANFDEN (1 << 12) /* Bit 12: ISO CAN FD Enable */ + /* Bit 13: Reserved */ +#define CAN_CTRL2_PREXCEN (1 << 14) /* Bit 14: Protocol Exception Enable */ +#define CAN_CTRL2_TIMER_SRC (1 << 15) /* Bit 15: Timer Source */ #define CAN_CTRL2_EACEN (1 << 16) /* Bit 16: Entire Frame Arbitration Field Comparison Enable (Rx) */ #define CAN_CTRL2_RRS (1 << 17) /* Bit 17: Remote Request Storing */ #define CAN_CTRL2_MRP (1 << 18) /* Bit 18: Mailboxes Reception Priority */ @@ -482,6 +497,7 @@ /* Bits 29-31: Reserved */ /* Error and Status 2 Register */ + /* Bits 0-12: Reserved */ #define CAN_ESR2_IMB (1 << 13) /* Bit 13: Inactive Mailbox */ #define CAN_ESR2_VPS (1 << 14) /* Bit 14: Valid Priority Status */ @@ -502,15 +518,54 @@ /* Rx FIFO Global Mask Register (32 Rx FIFO Global Mask Bits) */ /* Rx FIFO Information Register */ + /* Bits 9-31: Reserved */ #define CAN_RXFIR_IDHIT_SHIFT (0) /* Bits 0-8: Identifier Acceptance Filter Hit Indicator */ #define CAN_RXFIR_IDHIT_MASK (0x1ff << CAN_RXFIR_IDHIT_SHIFT) +/* CAN Bit Timing register (CBT) */ + +/* CBT Bit Fields */ +#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0x1F) +#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << 5)) & 0x3E0) +#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << 10)) & 0xFC00) +#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0x1F0000) +#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << 21)) & 0x7FE00000) +#define CAN_CBT_BTF (1 << 31) /* Bit 31: Bit Timing Format Enable */ + +/* CAN MB TX codes */ +#define CAN_TXMB_INACTIVE 0x8 /* MB is not active. */ +#define CAN_TXMB_ABORT 0x9 /* MB is aborted. */ +#define CAN_TXMB_DATAORREMOTE 0xC /* MB is a TX Data Frame(when MB RTR = 0) or */ + /* MB is a TX Remote Request Frame (when MB RTR = 1). */ +#define CAN_TXMB_TANSWER 0xE /* MB is a TX Response Request Frame from */ + /* an incoming Remote Request Frame. */ +#define CAN_TXMB_NOTUSED 0xF /* Not used.*/ + +/* CAN FD Control register (FDCTRL) */ +#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0x3F) +#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << 8)) & 0x1F00) +#define CAN_FDCTRL_TDCF (1 << 14) /* Bit 14: TDC fail */ +#define CAN_FDCTRL_TDCEN (1 << 15) /* Bit 15: TDC enable */ +#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0x30000) +#define CAN_FDCTRL_FDRATE (1 << 31) /* Bit 31: FD rate */ + +/* FDCBT Bit Fields */ +#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0x7) +#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << 5)) & 0xE0) +#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << 10)) & 0x7C00) +#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0x70000) +#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << 20)) & 0x3FF00000) + +/* FDCRC Bit Fields */ +#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0x1FFFFF) +#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << 24)) & 0x7F000000) + /* Rn Individual Mask Registers */ #define CAN_RXIMR(n) (1 << (n)) /* Bit n: Individual Mask Bits */ - /* Pretended Networking Control 1 register */ +/* Pretended Networking Control 1 register */ #define CAN_CTRL1_PN_ /* Pretended Networking Control 2 register */ @@ -561,16 +616,4 @@ /* CAN FD CRC register */ #define CAN_FDCRC_ -/**************************************************************************************************** - * Public Types - ****************************************************************************************************/ - -/**************************************************************************************************** - * Public Data - ****************************************************************************************************/ - -/**************************************************************************************************** - * Public Functions - ****************************************************************************************************/ - #endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FLEXCAN_H */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h new file mode 100644 index 0000000000..59f576a6b5 --- /dev/null +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h @@ -0,0 +1,143 @@ +/***************************************************************************************************** + * arch/arm/src/s32k1xx/chip/s32k1xx_ftfc.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FTFC_H +#define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FTFC_H + +/***************************************************************************************************** + * Included Files + *****************************************************************************************************/ + +#include +#include + +/***************************************************************************************************** + * Pre-processor Definitions + *****************************************************************************************************/ + +/* FTFC Register Offsets *****************************************************************************/ + +/* FTFC Register Offsets *****************************************************************************/ + +#define S32K1XX_FTFC_FSTAT_OFFSET 0x0000 +#define S32K1XX_FTFC_FCNFG_OFFSET 0x0001 +#define S32K1XX_FTFC_FSEC_OFFSET 0x0002 +#define S32K1XX_FTFC_FOPT_OFFSET 0x0003 +#define S32K1XX_FTFC_FCCOB3_OFFSET 0x0004 +#define S32K1XX_FTFC_FCCOB2_OFFSET 0x0005 +#define S32K1XX_FTFC_FCCOB1_OFFSET 0x0006 +#define S32K1XX_FTFC_FCCOB0_OFFSET 0x0007 +#define S32K1XX_FTFC_FCCOB7_OFFSET 0x0008 +#define S32K1XX_FTFC_FCCOB6_OFFSET 0x0009 +#define S32K1XX_FTFC_FCCOB5_OFFSET 0x000a +#define S32K1XX_FTFC_FCCOB4_OFFSET 0x000b +#define S32K1XX_FTFC_FCCOBB_OFFSET 0x000c +#define S32K1XX_FTFC_FCCOBA_OFFSET 0x000d +#define S32K1XX_FTFC_FCCOB9_OFFSET 0x000e +#define S32K1XX_FTFC_FCCOB8_OFFSET 0x000f +#define S32K1XX_FTFC_FPROT3_OFFSET 0x0010 +#define S32K1XX_FTFC_FPROT2_OFFSET 0x0011 +#define S32K1XX_FTFC_FPROT1_OFFSET 0x0012 +#define S32K1XX_FTFC_FPROT0_OFFSET 0x0013 +#define S32K1XX_FTFC_FEPROT_OFFSET 0x0016 +#define S32K1XX_FTFC_FDPROT_OFFSET 0x0017 +#define S32K1XX_FTFC_FCSESTAT_OFFSET 0x002c +#define S32K1XX_FTFC_FERSTAT_OFFSET 0x002e +#define S32K1XX_FTFC_FERCNFG_OFFSET 0x002f + +/* FTFC Register Addresses ***************************************************************************/ + +#define S32K1XX_FTFC_FSTAT (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FSTAT_OFFSET) +#define S32K1XX_FTFC_FCNFG (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCNFG_OFFSET) +#define S32K1XX_FTFC_FSEC (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FSEC_OFFSET) +#define S32K1XX_FTFC_FOPT (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FOPT_OFFSET) +#define S32K1XX_FTFC_FCCOB3 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB3_OFFSET) +#define S32K1XX_FTFC_FCCOB2 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB2_OFFSET) +#define S32K1XX_FTFC_FCCOB1 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB1_OFFSET) +#define S32K1XX_FTFC_FCCOB0 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB0_OFFSET) +#define S32K1XX_FTFC_FCCOB7 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB7_OFFSET) +#define S32K1XX_FTFC_FCCOB6 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB6_OFFSET) +#define S32K1XX_FTFC_FCCOB5 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB5_OFFSET) +#define S32K1XX_FTFC_FCCOB4 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB4_OFFSET) +#define S32K1XX_FTFC_FCCOBB (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOBB_OFFSET) +#define S32K1XX_FTFC_FCCOBA (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOBA_OFFSET) +#define S32K1XX_FTFC_FCCOB9 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB9_OFFSET) +#define S32K1XX_FTFC_FCCOB8 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCCOB8_OFFSET) +#define S32K1XX_FTFC_FPROT3 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FPROT3_OFFSET) +#define S32K1XX_FTFC_FPROT2 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FPROT2_OFFSET) +#define S32K1XX_FTFC_FPROT1 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FPROT1_OFFSET) +#define S32K1XX_FTFC_FPROT0 (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FPROT0_OFFSET) +#define S32K1XX_FTFC_FEPROT (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FEPROT_OFFSET) +#define S32K1XX_FTFC_FDPROT (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FDPROT_OFFSET) +#define S32K1XX_FTFC_FCSESTAT (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCSESTAT_OFFSET) +#define S32K1XX_FTFC_FERSTAT (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FERSTAT_OFFSET) +#define S32K1XX_FTFC_FERCNFG (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FERCNFG_OFFSET) + +/* FTFC Register Bitfield Definitions ****************************************************************/ + +#define FTTC_FSTAT_MGSTAT0 (1 << 0) +#define FTTC_FSTAT_FPVIOL (1 << 4) +#define FTTC_FSTAT_ACCERR (1 << 5) +#define FTTC_FSTAT_RDCOLERR (1 << 6) +#define FTTC_FSTAT_CCIF (1 << 7) + +#define FTTC_FCNFG_EEERDY (1 << 0) +#define FTTC_FCNFG_RAMRDY (1 << 1) + +/* Flash controller command numbers ******************************************************************/ + +#define S32K1XX_FTFC_VERIFY_BLOCK 0x00 /* RD1BLK*/ +#define S32K1XX_FTFC_VERIFY_SECTION 0x01 /* RD1SEC*/ +#define S32K1XX_FTFC_PROGRAM_CHECK 0x02 /* PGMCHK*/ +#define S32K1XX_FTFC_READ_RESOURCE 0x03 /* RDRSRC*/ +#define S32K1XX_FTFC_PROGRAM_LONGWORD 0x06 /* PGM4*/ +#define S32K1XX_FTFC_PROGRAM_PHRASE 0x07 /* PGM8*/ +#define S32K1XX_FTFC_ERASE_BLOCK 0x08 /* ERSBLK*/ +#define S32K1XX_FTFC_ERASE_SECTOR 0x09 /* ERSSCR*/ +#define S32K1XX_FTFC_PROGRAM_SECTION 0x0B /* PGMSEC*/ +#define S32K1XX_FTFC_GENERATE_CRC 0x0C /* CRCGEN*/ +#define S32K1XX_FTFC_VERIFY_ALL_BLOCK 0x40 /* RD1ALL*/ +#define S32K1XX_FTFC_READ_ONCE 0x41 /* RDONCE or RDINDEX*/ +#define S32K1XX_FTFC_PROGRAM_ONCE 0x43 /* PGMONCE or PGMINDEX*/ +#define S32K1XX_FTFC_ERASE_ALL_BLOCK 0x44 /* ERSALL*/ +#define S32K1XX_FTFC_SECURITY_BY_PASS 0x45 /* VFYKEY*/ +#define S32K1XX_FTFC_SWAP_CONTROL 0x46 /* SWAP*/ +#define S32K1XX_FTFC_ERASE_ALL_BLOCK_UNSECURE 0x49 /* ERSALLU*/ +#define S32K1XX_FTFC_VERIFY_ALL_EXECUTE_ONLY_SEGMENT 0x4A /* RD1XA*/ +#define S32K1XX_FTFC_ERASE_ALL_EXECUTE_ONLY_SEGMENT 0x4B /* ERSXA*/ +#define S32K1XX_FTFC_PROGRAM_PARTITION 0x80 /* PGMPART */ +#define S32K1XX_FTFC_SET_FLEXRAM_FUNCTION 0x81 /* SETRAM */ + +#endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FTFC_H */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_flexcan.c b/arch/arm/src/s32k1xx/s32k1xx_flexcan.c new file mode 100644 index 0000000000..d09dceb115 --- /dev/null +++ b/arch/arm/src/s32k1xx/s32k1xx_flexcan.c @@ -0,0 +1,1901 @@ +/**************************************************************************** + * arch/arm/src/s32k1xx/s32k1xx_flexcan.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "arm_arch.h" +#include "chip.h" +#include "s32k1xx_config.h" +#include "hardware/s32k1xx_flexcan.h" +#include "hardware/s32k1xx_pinmux.h" +#include "s32k1xx_periphclocks.h" +#include "s32k1xx_pin.h" +#include "s32k1xx_flexcan.h" + +#include + +#ifdef CONFIG_NET_CMSG +#include +#endif + +#ifdef CONFIG_S32K1XX_FLEXCAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If processing is not done at the interrupt level, then work queue support + * is required. + */ + +#define CANWORK LPWORK + +/* CONFIG_S32K1XX_FLEXCAN_NETHIFS determines the number of physical + * interfaces that will be supported. + */ + +#define MASKSTDID 0x000007ff +#define MASKEXTID 0x1fffffff +#define FLAGEFF (1 << 31) /* Extended frame format */ +#define FLAGRTR (1 << 30) /* Remote transmission request */ + +#define RXMBCOUNT 5 +#define TXMBCOUNT 2 +#define TOTALMBCOUNT RXMBCOUNT + TXMBCOUNT + +#define IFLAG1_RX ((1 << RXMBCOUNT)-1) +#define IFLAG1_TX (((1 << TXMBCOUNT)-1) << RXMBCOUNT) + +#define CAN_FIFO_NE (1 << 5) +#define CAN_FIFO_OV (1 << 6) +#define CAN_FIFO_WARN (1 << 7) +#define CAN_EFF_FLAG 0x80000000 /* EFF/SFF is set in the MSB */ + +#define POOL_SIZE 1 + +#ifdef CONFIG_NET_CMSG +#define MSG_DATA sizeof(struct timeval) +#else +#define MSG_DATA 0 +#endif + +/* CAN bit timing values */ +#define CLK_FREQ 80000000 +#define PRESDIV_MAX 256 + +#define SEG_MAX 8 +#define SEG_MIN 1 +#define TSEG_MIN 2 +#define TSEG1_MAX 17 +#define TSEG2_MAX 9 +#define NUMTQ_MAX 26 + +#define SEG_FD_MAX 32 +#define SEG_FD_MIN 1 +#define TSEG_FD_MIN 2 +#define TSEG1_FD_MAX 39 +#define TSEG2_FD_MAX 9 +#define NUMTQ_FD_MAX 49 + +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE + +# if !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +# endif + +#define TX_TIMEOUT_WQ +#endif + +/* Interrupt flags for RX fifo */ +#define IFLAG1_RXFIFO (CAN_FIFO_NE | CAN_FIFO_WARN | CAN_FIFO_OV) + +static int peak_tx_mailbox_index_ = 0; + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +union cs_e +{ + volatile uint32_t cs; + struct + { + volatile uint32_t time_stamp : 16; + volatile uint32_t dlc : 4; + volatile uint32_t rtr : 1; + volatile uint32_t ide : 1; + volatile uint32_t srr : 1; + volatile uint32_t res : 1; + volatile uint32_t code : 4; + volatile uint32_t res2 : 1; + volatile uint32_t esi : 1; + volatile uint32_t brs : 1; + volatile uint32_t edl : 1; + }; +}; + +union id_e +{ + volatile uint32_t w; + struct + { + volatile uint32_t ext : 29; + volatile uint32_t resex : 3; + }; + struct + { + volatile uint32_t res : 18; + volatile uint32_t std : 11; + volatile uint32_t resstd : 3; + }; +}; + +union data_e +{ + volatile uint32_t w00; + struct + { + volatile uint32_t b03 : 8; + volatile uint32_t b02 : 8; + volatile uint32_t b01 : 8; + volatile uint32_t b00 : 8; + }; +}; + +struct mb_s +{ + union cs_e cs; + union id_e id; +#ifdef CONFIG_NET_CAN_CANFD + union data_e data[16]; +#else + union data_e data[2]; +#endif +}; + +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE +#define TX_ABORT -1 +#define TX_FREE 0 +#define TX_BUSY 1 + +struct txmbstats +{ + struct timeval deadline; + uint32_t pending; /* -1 = abort, 0 = free, 1 = busy */ +}; +#endif + +/* FlexCAN Device hardware configuration */ + +struct flexcan_config_s +{ + uint32_t tx_pin; /* GPIO configuration for TX */ + uint32_t rx_pin; /* GPIO configuration for RX */ + uint32_t enable_pin; /* Optional enable pin */ + uint32_t enable_high; /* Optional enable high/low */ + uint32_t bus_irq; /* BUS IRQ */ + uint32_t error_irq; /* ERROR IRQ */ + uint32_t lprx_irq; /* LPRX IRQ */ + uint32_t mb_irq; /* MB 0-15 IRQ */ +}; + +struct flexcan_timeseg +{ + uint32_t bitrate; + int32_t samplep; + uint8_t propseg; + uint8_t pseg1; + uint8_t pseg2; + uint8_t presdiv; +}; + +/* FlexCAN device structures */ + +#ifdef CONFIG_S32K1XX_FLEXCAN0 +static const struct flexcan_config_s s32k1xx_flexcan0_config = +{ + .tx_pin = PIN_CAN0_TX, + .rx_pin = PIN_CAN0_RX, +#ifdef PIN_CAN0_ENABLE + .enable_pin = PIN_CAN0_ENABLE, + .enable_high = CAN0_ENABLE_OUT, +#else + .enable_pin = 0, + .enable_high = 0, +#endif + .bus_irq = S32K1XX_IRQ_CAN0_BUS, + .error_irq = S32K1XX_IRQ_CAN0_ERROR, + .lprx_irq = S32K1XX_IRQ_CAN0_LPRX, + .mb_irq = S32K1XX_IRQ_CAN0_0_15, +}; +#endif + +#ifdef CONFIG_S32K1XX_FLEXCAN1 +static const struct flexcan_config_s s32k1xx_flexcan1_config = +{ + .tx_pin = PIN_CAN1_TX, + .rx_pin = PIN_CAN1_RX, +#ifdef PIN_CAN1_ENABLE + .enable_pin = PIN_CAN1_ENABLE, + .enable_high = CAN1_ENABLE_OUT, +#else + .enable_pin = 0, + .enable_high = 0, +#endif + .bus_irq = S32K1XX_IRQ_CAN1_BUS, + .error_irq = S32K1XX_IRQ_CAN1_ERROR, + .lprx_irq = 0, + .mb_irq = S32K1XX_IRQ_CAN1_0_15, +}; +#endif + +#ifdef CONFIG_S32K1XX_FLEXCAN2 +static const struct flexcan_config_s s32k1xx_flexcan2_config = +{ + .tx_pin = PIN_CAN2_TX, + .rx_pin = PIN_CAN2_RX, +#ifdef PIN_CAN2_ENABLE + .enable_pin = PIN_CAN2_ENABLE, + .rx_pin = CAN2_ENABLE_HIGH, +#else + .enable_pin = 0, + .rx_pin = 0, +#endif + .bus_irq = S32K1XX_IRQ_CAN2_BUS, + .error_irq = S32K1XX_IRQ_CAN2_ERROR, + .lprx_irq = 0, + .mb_irq = S32K1XX_IRQ_CAN2_0_15, +}; +#endif + +/* The s32k1xx_driver_s encapsulates all state information for a single + * hardware interface + */ + +struct s32k1xx_driver_s +{ + uint32_t base; /* FLEXCAN base address */ + bool bifup; /* true:ifup false:ifdown */ +#ifdef TX_TIMEOUT_WQ + WDOG_ID txtimeout[TXMBCOUNT]; /* TX timeout timer */ +#endif + struct work_s irqwork; /* For deferring interrupt work to the wq */ + struct work_s pollwork; /* For deferring poll work to the work wq */ +#ifdef CONFIG_NET_CAN_CANFD + struct canfd_frame *txdesc; /* A pointer to the list of TX descriptor */ + struct canfd_frame *rxdesc; /* A pointer to the list of RX descriptors */ +#else + struct can_frame *txdesc; /* A pointer to the list of TX descriptor */ + struct can_frame *rxdesc; /* A pointer to the list of RX descriptors */ +#endif + + /* This holds the information visible to the NuttX network */ + + struct net_driver_s dev; /* Interface understood by the network */ + + struct mb_s *rx; + struct mb_s *tx; + + struct flexcan_timeseg arbi_timing; /* Timing for arbitration phase */ +#ifdef CONFIG_NET_CAN_CANFD + struct flexcan_timeseg data_timing; /* Timing for data phase */ +#endif + + const struct flexcan_config_s *config; + +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE + struct txmbstats txmb[TXMBCOUNT]; +#endif +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_S32K1XX_FLEXCAN0 +static struct s32k1xx_driver_s g_flexcan0; +#endif + +#ifdef CONFIG_S32K1XX_FLEXCAN1 +static struct s32k1xx_driver_s g_flexcan1; +#endif + +#ifdef CONFIG_S32K1XX_FLEXCAN2 +static struct s32k1xx_driver_s g_flexcan2; +#endif + +#ifdef CONFIG_NET_CAN_CANFD +static uint8_t g_tx_pool[(sizeof(struct canfd_frame)+MSG_DATA)*POOL_SIZE]; +static uint8_t g_rx_pool[(sizeof(struct canfd_frame)+MSG_DATA)*POOL_SIZE]; +#else +static uint8_t g_tx_pool[sizeof(struct can_frame)*POOL_SIZE]; +static uint8_t g_rx_pool[sizeof(struct can_frame)*POOL_SIZE]; +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_lsb + * + * Description: + * Calculate position of lsb that's equal to 1 + * + * Input Parameters: + * value - The value to perform the operation on + * + * Returned Value: + * location of lsb which is equal to 1, returns 32 when value is 0 + * + ****************************************************************************/ + +static inline uint32_t arm_lsb(unsigned int value) +{ + uint32_t ret; + volatile uint32_t rvalue = value; + __asm__ __volatile__ ("rbit %1,%0" : "=r" (rvalue) : "r" (rvalue)); + __asm__ __volatile__ ("clz %0, %1" : "=r"(ret) : "r"(rvalue)); + return ret; +} + +/**************************************************************************** + * Name: s32k1xx_bitratetotimeseg + * + * Description: + * Convert bitrate to timeseg + * + * Input Parameters: + * timeseg - structure to store bit timing + * sp_tolerance - allowed difference in sample point from calculated + * bit timings (recommended value: 1) + * can_fd - if set to calculate CAN FD bit timings, otherwise calculate + * classical can timings + * + * Returned Value: + * return 1 on succes, return 0 on failure + * + ****************************************************************************/ + +uint32_t s32k1xx_bitratetotimeseg(struct flexcan_timeseg *timeseg, + int32_t sp_tolerance, + uint32_t can_fd) +{ + int32_t tmppresdiv; + int32_t numtq; + int32_t tmpsample; + int32_t tseg1; + int32_t tseg2; + int32_t tmppseg1; + int32_t tmppseg2; + int32_t tmppropseg; + + const int32_t TSEG1MAX = (can_fd ? TSEG1_FD_MAX : TSEG1_MAX); + const int32_t TSEG2MAX = (can_fd ? TSEG2_FD_MAX : TSEG2_MAX); + const int32_t SEGMAX = (can_fd ? SEG_FD_MAX : SEG_MAX); + const int32_t NUMTQMAX = (can_fd ? NUMTQ_FD_MAX : NUMTQ_MAX); + + for (tmppresdiv = 0; tmppresdiv < PRESDIV_MAX; tmppresdiv++) + { + numtq = (CLK_FREQ / ((tmppresdiv + 1) * timeseg->bitrate)); + + if (numtq == 0) + { + continue; + } + + /* The number of time quanta in 1 bit time must be + * lower than the one supported + */ + + if ((CLK_FREQ / ((tmppresdiv + 1) * numtq) == timeseg->bitrate) + && (numtq >= 8) && (numtq < NUMTQMAX)) + { + /* Compute time segments based on the value of the sampling point */ + + tseg1 = (numtq * timeseg->samplep / 100) - 1; + tseg2 = numtq - 1 - tseg1; + + /* Adjust time segment 1 and time segment 2 */ + + while (tseg1 >= TSEG1MAX || tseg2 < TSEG_MIN) + { + tseg2++; + tseg1--; + } + + tmppseg2 = tseg2 - 1; + + /* Start from pseg1 = pseg2 and adjust until propseg is valid */ + + tmppseg1 = tmppseg2; + tmppropseg = tseg1 - tmppseg1 - 2; + + while (tmppropseg <= 0) + { + tmppropseg++; + tmppseg1--; + } + + while (tmppropseg >= SEGMAX) + { + tmppropseg--; + tmppseg1++; + } + + if (((tseg1 >= TSEG1MAX) || (tseg2 >= TSEG2MAX) || + (tseg2 < TSEG_MIN) || (tseg1 < TSEG_MIN)) || + ((tmppropseg >= SEGMAX) || (tmppseg1 >= SEGMAX) || + (tmppseg2 < SEG_MIN) || (tmppseg2 >= SEGMAX))) + { + continue; + } + + tmpsample = ((tseg1 + 1) * 100) / numtq; + + if ((tmpsample - timeseg->samplep) <= sp_tolerance && + (timeseg->samplep - tmpsample) <= sp_tolerance) + { + if (can_fd == 1) + { + timeseg->propseg = tmppropseg + 1; + } + else + { + timeseg->propseg = tmppropseg; + } + timeseg->pseg1 = tmppseg1; + timeseg->pseg2 = tmppseg2; + timeseg->presdiv = tmppresdiv; + timeseg->samplep = tmpsample; + return 1; + } + } + } + + return 0; +} + +/* Common TX logic */ + +static bool s32k1xx_txringfull(FAR struct s32k1xx_driver_s *priv); +static int s32k1xx_transmit(FAR struct s32k1xx_driver_s *priv); +static int s32k1xx_txpoll(struct net_driver_s *dev); + +/* Helper functions */ + +static void s32k1xx_setenable(uint32_t base, uint32_t enable); +static void s32k1xx_setfreeze(uint32_t base, uint32_t freeze); +static uint32_t s32k1xx_waitmcr_change(uint32_t base, + uint32_t mask, + uint32_t target_state); + +/* Interrupt handling */ + +static void s32k1xx_receive(FAR struct s32k1xx_driver_s *priv, + uint32_t flags); +static void s32k1xx_txdone(FAR void *arg); + +static int s32k1xx_flexcan_interrupt(int irq, FAR void *context, + FAR void *arg); + +/* Watchdog timer expirations */ +#ifdef TX_TIMEOUT_WQ +static void s32k1xx_txtimeout_work(FAR void *arg); +static void s32k1xx_txtimeout_expiry(int argc, uint32_t arg, ...); +#endif + +/* NuttX callback functions */ + +static int s32k1xx_ifup(struct net_driver_s *dev); +static int s32k1xx_ifdown(struct net_driver_s *dev); + +static void s32k1xx_txavail_work(FAR void *arg); +static int s32k1xx_txavail(struct net_driver_s *dev); + +#ifdef CONFIG_NETDEV_IOCTL +static int s32k1xx_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg); +#endif + +/* Initialization */ + +static int s32k1xx_initialize(struct s32k1xx_driver_s *priv); +static void s32k1xx_reset(struct s32k1xx_driver_s *priv); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: s32k1xx_txringfull + * + * Description: + * Check if all of the TX descriptors are in use. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * true is the TX ring is full; false if there are free slots at the + * head index. + * + ****************************************************************************/ + +static bool s32k1xx_txringfull(FAR struct s32k1xx_driver_s *priv) +{ + uint32_t mbi = 0; + + while (mbi < TXMBCOUNT) + { + if (priv->tx[mbi].cs.code != CAN_TXMB_DATAORREMOTE) + { + return 0; + } + + mbi++; + } + + return 1; +} + +/**************************************************************************** + * Function: s32k1xx_transmit + * + * Description: + * Start hardware transmission. Called either from the txdone interrupt + * handling or from watchdog based polling. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int s32k1xx_transmit(FAR struct s32k1xx_driver_s *priv) +{ + /* Attempt to write frame */ + + uint32_t mbi = 0; + if ((getreg32(priv->base + S32K1XX_CAN_ESR2_OFFSET) & + (CAN_ESR2_IMB | CAN_ESR2_VPS)) == + (CAN_ESR2_IMB | CAN_ESR2_VPS)) + { + mbi = ((getreg32(priv->base + S32K1XX_CAN_ESR2_OFFSET) & + CAN_ESR2_LPTM_MASK) >> CAN_ESR2_LPTM_SHIFT); + mbi -= RXMBCOUNT; + } + + uint32_t mb_bit = 1 << (RXMBCOUNT + mbi); + + while (mbi < TXMBCOUNT) + { + if (priv->tx[mbi].cs.code != CAN_TXMB_DATAORREMOTE) + { + putreg32(mb_bit, priv->base + S32K1XX_CAN_IFLAG1_OFFSET); + break; + } + + mb_bit <<= 1; + mbi++; + } + + if (mbi == TXMBCOUNT) + { + nwarn("No TX MB available mbi %i\r\n", mbi); + return 0; /* No transmission for you! */ + } + +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE + int32_t timeout = 0; + struct timespec ts; + clock_systimespec(&ts); + + if (priv->dev.d_sndlen > priv->dev.d_len) + { + struct timeval *tv = + (struct timeval *)(priv->dev.d_buf + priv->dev.d_len); + priv->txmb[mbi].deadline = *tv; + timeout = (tv->tv_sec - ts.tv_sec)*CLK_TCK + + ((tv->tv_usec - ts.tv_nsec / 1000)*CLK_TCK) / 1000000; + if (timeout < 0) + { + return 0; /* No transmission for you! */ + } + } + else + { + /* Default TX deadline defined in NET_CAN_RAW_DEFAULT_TX_DEADLINE */ + + if (CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE > 0) + { + timeout = ((CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE / 1000000) + *CLK_TCK); + priv->txmb[mbi].deadline.tv_sec = ts.tv_sec + + CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE / 1000000; + priv->txmb[mbi].deadline.tv_usec = (ts.tv_nsec / 1000) + + CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE % 1000000; + } + else + { + priv->txmb[mbi].deadline.tv_sec = 0; + priv->txmb[mbi].deadline.tv_usec = 0; + } + } +#endif + + peak_tx_mailbox_index_ = + (peak_tx_mailbox_index_ > mbi ? peak_tx_mailbox_index_ : mbi); + + union cs_e cs; + cs.code = CAN_TXMB_DATAORREMOTE; + struct mb_s *mb = &priv->tx[mbi]; + mb->cs.code = CAN_TXMB_INACTIVE; + + if (priv->dev.d_len <= sizeof(struct can_frame)) + { + struct can_frame *frame = (struct can_frame *)priv->dev.d_buf; + + if (frame->can_id & CAN_EFF_FLAG) + { + cs.ide = 1; + mb->id.ext = frame->can_id & MASKEXTID; + } + else + { + mb->id.std = frame->can_id & MASKSTDID; + } + + cs.rtr = frame->can_id & FLAGRTR ? 1 : 0; + cs.dlc = frame->can_dlc; + + mb->data[0].w00 = __builtin_bswap32(*(uint32_t *)&frame->data[0]); + mb->data[1].w00 = __builtin_bswap32(*(uint32_t *)&frame->data[4]); + } +#ifdef CONFIG_NET_CAN_CANFD + else /* CAN FD frame */ + { + struct canfd_frame *frame = (struct canfd_frame *)priv->dev.d_buf; + + cs.edl = 1; /* CAN FD Frame */ + + if (frame->can_id & CAN_EFF_FLAG) + { + cs.ide = 1; + mb->id.ext = frame->can_id & MASKEXTID; + } + else + { + mb->id.std = frame->can_id & MASKSTDID; + } + + cs.rtr = frame->can_id & FLAGRTR ? 1 : 0; + + cs.dlc = len_to_can_dlc[frame->len]; + + uint32_t *frame_data_word = (uint32_t *)&frame->data[0]; + + for (int i = 0; i < (frame->len + 4 - 1) / 4; i++) + { + mb->data[i].w00 = __builtin_bswap32(frame_data_word[i]); + } + } +#endif + + mb->cs = cs; /* Go. */ + + uint32_t regval; + regval = getreg32(priv->base + S32K1XX_CAN_IMASK1_OFFSET); + regval |= mb_bit; + putreg32(regval, priv->base + S32K1XX_CAN_IMASK1_OFFSET); + + /* Increment statistics */ + + NETDEV_TXPACKETS(&priv->dev); + +#ifdef TX_TIMEOUT_WQ + /* Setup the TX timeout watchdog (perhaps restarting the timer) */ + + if (timeout >= 0) + { + wd_start(priv->txtimeout[mbi], timeout + 1, s32k1xx_txtimeout_expiry, + 1, (wdparm_t)priv); + } +#endif + + return OK; +} + +/**************************************************************************** + * Function: s32k1xx_txpoll + * + * Description: + * The transmitter is available, check if the network has any outgoing + * packets ready to send. This is a callback from devif_poll(). + * devif_poll() may be called: + * + * 1. When the preceding TX packet send is complete, + * 2. When the preceding TX packet send timesout and the interface is reset + * 3. During normal TX polling + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int s32k1xx_txpoll(struct net_driver_s *dev) +{ + FAR struct s32k1xx_driver_s *priv = + (FAR struct s32k1xx_driver_s *)dev->d_private; + + /* If the polling resulted in data that should be sent out on the network, + * the field d_len is set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + if (!devif_loopback(&priv->dev)) + { + /* Send the packet */ + + s32k1xx_transmit(priv); + + /* Check if there is room in the device to hold another packet. If + * not, return a non-zero value to terminate the poll. + */ + + if (s32k1xx_txringfull(priv)) + { + return -EBUSY; + } + } + } + + /* If zero is returned, the polling will continue until all connections + * have been examined. + */ + + return 0; +} + +/**************************************************************************** + * Function: s32k1xx_receive + * + * Description: + * An interrupt was received indicating the availability of a new RX packet + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static void s32k1xx_receive(FAR struct s32k1xx_driver_s *priv, + uint32_t flags) +{ + uint32_t mb_index; + struct mb_s *rf; + + while ((mb_index = arm_lsb(flags)) != 32) + { + rf = &priv->rx[mb_index]; + + /* Read the frame contents */ + +#ifdef CONFIG_NET_CAN_CANFD + if (rf->cs.edl) /* CAN FD frame */ + { + struct canfd_frame *frame = (struct canfd_frame *)priv->rxdesc; + + if (rf->cs.ide) + { + frame->can_id = MASKEXTID & rf->id.ext; + frame->can_id |= FLAGEFF; + } + else + { + frame->can_id = MASKSTDID & rf->id.std; + } + + if (rf->cs.rtr) + { + frame->can_id |= FLAGRTR; + } + + frame->len = can_dlc_to_len[rf->cs.dlc]; + + uint32_t *frame_data_word = (uint32_t *)&frame->data[0]; + + for (int i = 0; i < (frame->len + 4 - 1) / 4; i++) + { + frame_data_word[i] = __builtin_bswap32(rf->data[i].w00); + } + + /* Clear MB interrupt flag */ + + putreg32(1 << mb_index, + priv->base + S32K1XX_CAN_IFLAG1_OFFSET); + + /* Copy the buffer pointer to priv->dev.. Set amount of data + * in priv->dev.d_len + */ + + priv->dev.d_len = sizeof(struct canfd_frame); + priv->dev.d_buf = (uint8_t *)frame; + } + else /* CAN 2.0 Frame */ +#endif + { + struct can_frame *frame = (struct can_frame *)priv->rxdesc; + + if (rf->cs.ide) + { + frame->can_id = MASKEXTID & rf->id.ext; + frame->can_id |= FLAGEFF; + } + else + { + frame->can_id = MASKSTDID & rf->id.std; + } + + if (rf->cs.rtr) + { + frame->can_id |= FLAGRTR; + } + + frame->can_dlc = rf->cs.dlc; + + *(uint32_t *)&frame->data[0] = __builtin_bswap32(rf->data[0].w00); + *(uint32_t *)&frame->data[4] = __builtin_bswap32(rf->data[1].w00); + + /* Clear MB interrupt flag */ + + putreg32(1 << mb_index, + priv->base + S32K1XX_CAN_IFLAG1_OFFSET); + + /* Copy the buffer pointer to priv->dev.. Set amount of data + * in priv->dev.d_len + */ + + priv->dev.d_len = sizeof(struct can_frame); + priv->dev.d_buf = (uint8_t *)frame; + } + + /* Send to socket interface */ + + NETDEV_RXPACKETS(&priv->dev); + + can_input(&priv->dev); + + /* Point the packet buffer back to the next Tx buffer that will be + * used during the next write. If the write queue is full, then + * this will point at an active buffer, which must not be written + * to. This is OK because devif_poll won't be called unless the + * queue is not full. + */ + + priv->dev.d_buf = (uint8_t *)priv->txdesc; + + flags &= ~(1 << mb_index); + + /* Reread interrupt flags and process them in this loop */ + + if (flags == 0) + { + flags = getreg32(priv->base + S32K1XX_CAN_IFLAG1_OFFSET); + flags &= IFLAG1_RX; + } + } +} + +/**************************************************************************** + * Function: s32k1xx_txdone + * + * Description: + * An interrupt was received indicating that the last TX packet(s) is done + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * We are not in an interrupt context so that we can lock the network. + * + ****************************************************************************/ + +static void s32k1xx_txdone(FAR void *arg) +{ + FAR struct s32k1xx_driver_s *priv = (FAR struct s32k1xx_driver_s *)arg; + uint32_t flags; + + flags = getreg32(priv->base + S32K1XX_CAN_IFLAG1_OFFSET); + flags &= IFLAG1_TX; + + #warning Missing logic + + /* FIXME First Process Error aborts */ + + /* Process TX completions */ + + uint32_t mb_bit = 1 << RXMBCOUNT; + for (uint32_t mbi = 0; flags && mbi < TXMBCOUNT; mbi++) + { + if (flags & mb_bit) + { + putreg32(mb_bit, priv->base + S32K1XX_CAN_IFLAG1_OFFSET); + flags &= ~mb_bit; + NETDEV_TXDONE(&priv->dev); +#ifdef TX_TIMEOUT_WQ + /* We are here because a transmission completed, so the + * corresponding watchdog can be canceled. + */ + + wd_cancel(priv->txtimeout[mbi]); +#endif + } + + mb_bit <<= 1; + } + + /* There should be space for a new TX in any event. Poll the network for + * new XMIT data + */ + + net_lock(); + devif_poll(&priv->dev, s32k1xx_txpoll); + net_unlock(); + up_enable_irq(priv->config->mb_irq); +} + +/**************************************************************************** + * Function: s32k1xx_flexcan_interrupt + * + * Description: + * Three interrupt sources will vector this this function: + * 1. CAN MB transmit interrupt handler + * 2. CAN MB receive interrupt handler + * 3. + * + * Input Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static int s32k1xx_flexcan_interrupt(int irq, FAR void *context, + FAR void *arg) +{ + FAR struct s32k1xx_driver_s *priv = (struct s32k1xx_driver_s *)arg; + + if (irq == priv->config->mb_irq) + { + uint32_t flags; + flags = getreg32(priv->base + S32K1XX_CAN_IFLAG1_OFFSET); + flags &= IFLAG1_RX; + + if (flags) + { + /* Process immediately since scheduling a workqueue is too slow + * which causes us to drop CAN frames + */ + + s32k1xx_receive(priv, flags); + } + + flags = getreg32(priv->base + S32K1XX_CAN_IFLAG1_OFFSET); + flags &= IFLAG1_TX; + + if (flags) + { + /* Disable further CAN interrupts. here can be no race + * condition here. + */ + + up_disable_irq(priv->config->mb_irq); + work_queue(CANWORK, &priv->irqwork, s32k1xx_txdone, priv, 0); + } + } + + return OK; +} + +/**************************************************************************** + * Function: s32k1xx_txtimeout_work + * + * Description: + * Perform TX timeout related work from the worker thread + * + * Input Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ +#ifdef TX_TIMEOUT_WQ + +static void s32k1xx_txtimeout_work(FAR void *arg) +{ + FAR struct s32k1xx_driver_s *priv = (FAR struct s32k1xx_driver_s *)arg; + + struct timespec ts; + struct timeval *now = (struct timeval *)&ts; + clock_systimespec(&ts); + now->tv_usec = ts.tv_nsec / 1000; /* timespec to timeval conversion */ + + /* The watchdog timed out, yet we still check mailboxes in case the + * transmit function transmitted a new frame + */ + + for (int mbi = 0; mbi < TXMBCOUNT; mbi++) + { + if (priv->txmb[mbi].deadline.tv_sec != 0 + && (now->tv_sec > priv->txmb[mbi].deadline.tv_sec + || now->tv_usec > priv->txmb[mbi].deadline.tv_usec)) + { + NETDEV_TXTIMEOUTS(&priv->dev); + struct mb_s *mb = &priv->tx[mbi]; + mb->cs.code = CAN_TXMB_ABORT; + priv->txmb[mbi].pending = TX_ABORT; + } + } +} + +/**************************************************************************** + * Function: s32k1xx_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. + * + * Input Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void s32k1xx_txtimeout_expiry(int argc, uint32_t arg, ...) +{ + FAR struct s32k1xx_driver_s *priv = (FAR struct s32k1xx_driver_s *)arg; + + /* Schedule to perform the TX timeout processing on the worker thread + */ + + work_queue(CANWORK, &priv->irqwork, s32k1xx_txtimeout_work, priv, 0); +} + +#endif + +static void s32k1xx_setenable(uint32_t base, uint32_t enable) +{ + uint32_t regval; + + if (enable) + { + regval = getreg32(base + S32K1XX_CAN_MCR_OFFSET); + regval &= ~(CAN_MCR_MDIS); + putreg32(regval, base + S32K1XX_CAN_MCR_OFFSET); + } + else + { + regval = getreg32(base + S32K1XX_CAN_MCR_OFFSET); + regval |= CAN_MCR_MDIS; + putreg32(regval, base + S32K1XX_CAN_MCR_OFFSET); + } + + s32k1xx_waitmcr_change(base, CAN_MCR_LPMACK, 1); +} + +static void s32k1xx_setfreeze(uint32_t base, uint32_t freeze) +{ + uint32_t regval; + if (freeze) + { + /* Enter freeze mode */ + + regval = getreg32(base + S32K1XX_CAN_MCR_OFFSET); + regval |= (CAN_MCR_HALT | CAN_MCR_FRZ); + putreg32(regval, base + S32K1XX_CAN_MCR_OFFSET); + } + else + { + /* Exit freeze mode */ + + regval = getreg32(base + S32K1XX_CAN_MCR_OFFSET); + regval &= ~(CAN_MCR_HALT | CAN_MCR_FRZ); + putreg32(regval, base + S32K1XX_CAN_MCR_OFFSET); + } +} + +static uint32_t s32k1xx_waitmcr_change(uint32_t base, uint32_t mask, + uint32_t target_state) +{ + const unsigned timeout = 1000; + for (unsigned wait_ack = 0; wait_ack < timeout; wait_ack++) + { + const bool state = (getreg32(base + S32K1XX_CAN_MCR_OFFSET) & mask) + != 0; + if (state == target_state) + { + return true; + } + + up_udelay(10); + } + + return false; +} + +static uint32_t s32k1xx_waitfreezeack_change(uint32_t base, + uint32_t target_state) +{ + return s32k1xx_waitmcr_change(base, CAN_MCR_FRZACK, target_state); +} + +/**************************************************************************** + * Function: s32k1xx_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int s32k1xx_ifup(struct net_driver_s *dev) +{ + FAR struct s32k1xx_driver_s *priv = + (FAR struct s32k1xx_driver_s *)dev->d_private; + + if (!s32k1xx_initialize(priv)) + { + nerr("initialize failed"); + return -1; + } + + priv->bifup = true; + +#ifdef CONFIG_NET_CAN_CANFD + priv->txdesc = (struct canfd_frame *)&g_tx_pool; + priv->rxdesc = (struct canfd_frame *)&g_rx_pool; +#else + priv->txdesc = (struct can_frame *)&g_tx_pool; + priv->rxdesc = (struct can_frame *)&g_rx_pool; +#endif + + priv->dev.d_buf = (uint8_t *)priv->txdesc; + + /* Set interrupts */ + + up_enable_irq(priv->config->bus_irq); + up_enable_irq(priv->config->error_irq); + if (priv->config->lprx_irq > 0) + { + up_enable_irq(priv->config->lprx_irq); + } + + up_enable_irq(priv->config->mb_irq); + + return OK; +} + +/**************************************************************************** + * Function: s32k1xx_ifdown + * + * Description: + * NuttX Callback: Stop the interface. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int s32k1xx_ifdown(struct net_driver_s *dev) +{ + FAR struct s32k1xx_driver_s *priv = + (FAR struct s32k1xx_driver_s *)dev->d_private; + + s32k1xx_reset(priv); + + priv->bifup = false; + return OK; +} + +/**************************************************************************** + * Function: s32k1xx_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Input Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +static void s32k1xx_txavail_work(FAR void *arg) +{ + FAR struct s32k1xx_driver_s *priv = (FAR struct s32k1xx_driver_s *)arg; + + /* Ignore the notification if the interface is not yet up */ + + net_lock(); + if (priv->bifup) + { + /* Check if there is room in the hardware to hold another outgoing + * packet. + */ + + if (!s32k1xx_txringfull(priv)) + { + /* No, there is space for another transfer. Poll the network for + * new XMIT data. + */ + + devif_poll(&priv->dev, s32k1xx_txpoll); + } + } + + net_unlock(); +} + +/**************************************************************************** + * Function: s32k1xx_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int s32k1xx_txavail(struct net_driver_s *dev) +{ + FAR struct s32k1xx_driver_s *priv = + (FAR struct s32k1xx_driver_s *)dev->d_private; + + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->pollwork)) + { + /* Schedule to serialize the poll on the worker thread. */ + + s32k1xx_txavail_work(priv); + } + + return OK; +} + +/**************************************************************************** + * Function: s32k1xx_ioctl + * + * Description: + * PHY ioctl command handler + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * cmd - ioctl command + * arg - Argument accompanying the command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NETDEV_CAN_BITRATE_IOCTL +static int s32k1xx_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg) +{ + FAR struct s32k1xx_driver_s *priv = + (FAR struct s32k1xx_driver_s *)dev->d_private; + + int ret; + + switch (cmd) + { + case SIOCGCANBITRATE: /* Get bitrate from a CAN controller */ + { + struct can_ioctl_data_s *req = + (struct can_ioctl_data_s *)((uintptr_t)arg); + req->arbi_bitrate = priv->arbi_timing.bitrate / 1000; /* kbit/s */ + req->arbi_samplep = priv->arbi_timing.samplep; +#ifdef CONFIG_NET_CAN_CANFD + req->data_bitrate = priv->data_timing.bitrate / 1000; /* kbit/s */ + req->data_samplep = priv->data_timing.samplep; +#else + req->data_bitrate = 0; + req->data_samplep = 0; +#endif + ret = OK; + } + break; + + case SIOCSCANBITRATE: /* Set bitrate of a CAN controller */ + { + struct can_ioctl_data_s *req = + (struct can_ioctl_data_s *)((uintptr_t)arg); + + struct flexcan_timeseg arbi_timing; + arbi_timing.bitrate = req->arbi_bitrate * 1000; + arbi_timing.samplep = req->arbi_samplep; + + if (s32k1xx_bitratetotimeseg(&arbi_timing, 10, 0)) + { + ret = OK; + } + else + { + ret = -EINVAL; + } + +#ifdef CONFIG_NET_CAN_CANFD + struct flexcan_timeseg data_timing; + data_timing.bitrate = req->data_bitrate * 1000; + data_timing.samplep = req->data_samplep; + + if (ret == OK && s32k1xx_bitratetotimeseg(&data_timing, 10, 1)) + { + ret = OK; + } + else + { + ret = -EINVAL; + } +#endif + + if (ret == OK) + { + /* Reset CAN controller and start with new timings */ + + priv->arbi_timing = arbi_timing; +#ifdef CONFIG_NET_CAN_CANFD + priv->data_timing = data_timing; +#endif + s32k1xx_ifup(dev); + } + } + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; +} +#endif /* CONFIG_NETDEV_IOCTL */ + +/**************************************************************************** + * Function: s32k1xx_initalize + * + * Description: + * Initialize FLEXCAN device + * + * Input Parameters: + * priv - Reference to the private FLEXCAN driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int s32k1xx_initialize(struct s32k1xx_driver_s *priv) +{ + uint32_t regval; + uint32_t i; + + /* initialize CAN device */ + + s32k1xx_setenable(priv->base, 0); + + /* Set SYS_CLOCK src */ + + regval = getreg32(priv->base + S32K1XX_CAN_CTRL1_OFFSET); + regval |= CAN_CTRL1_CLKSRC; + putreg32(regval, priv->base + S32K1XX_CAN_CTRL1_OFFSET); + + s32k1xx_setenable(priv->base, 1); + + s32k1xx_reset(priv); + + /* Enter freeze mode */ + + s32k1xx_setfreeze(priv->base, 1); + if (!s32k1xx_waitfreezeack_change(priv->base, 1)) + { + ninfo("FLEXCAN: freeze fail\r\n"); + return -1; + } + +#ifndef CONFIG_NET_CAN_CANFD + regval = getreg32(priv->base + S32K1XX_CAN_CTRL1_OFFSET); + regval |= CAN_CTRL1_PRESDIV(priv->arbi_timing.presdiv) | /* Prescaler divisor factor */ + CAN_CTRL1_PROPSEG(priv->arbi_timing.propseg) | /* Propagation segment */ + CAN_CTRL1_PSEG1(priv->arbi_timing.pseg1) | /* Phase buffer segment 1 */ + CAN_CTRL1_PSEG2(priv->arbi_timing.pseg2) | /* Phase buffer segment 2 */ + CAN_CTRL1_RJW(1); /* Resynchronization jump width */ + putreg32(regval, priv->base + S32K1XX_CAN_CTRL1_OFFSET); + +#else + regval = getreg32(priv->base + S32K1XX_CAN_CBT_OFFSET); + regval |= CAN_CBT_BTF | /* Enable extended bit timing + * configurations for CAN-FD for setting up + * separately nominal and data phase */ + CAN_CBT_EPRESDIV(priv->arbi_timing.presdiv) | /* Prescaler divisor factor */ + CAN_CBT_EPROPSEG(priv->arbi_timing.propseg) | /* Propagation segment */ + CAN_CBT_EPSEG1(priv->arbi_timing.pseg1) | /* Phase buffer segment 1 */ + CAN_CBT_EPSEG2(priv->arbi_timing.pseg2) | /* Phase buffer segment 2 */ + CAN_CBT_ERJW(1); /* Resynchronization jump width */ + putreg32(regval, priv->base + S32K1XX_CAN_CBT_OFFSET); + + /* Enable CAN FD feature */ + + regval = getreg32(priv->base + S32K1XX_CAN_MCR_OFFSET); + regval |= CAN_MCR_FDEN; + putreg32(regval, priv->base + S32K1XX_CAN_MCR_OFFSET); + + regval = getreg32(priv->base + S32K1XX_CAN_FDCBT_OFFSET); + regval |= CAN_FDCBT_FPRESDIV(priv->data_timing.presdiv) | /* Prescaler divisor factor of 1 */ + CAN_FDCBT_FPROPSEG(priv->data_timing.propseg) | /* Propagation + * segment (only register that doesn't add 1) */ + CAN_FDCBT_FPSEG1(priv->data_timing.pseg1) | /* Phase buffer segment 1 */ + CAN_FDCBT_FPSEG2(priv->data_timing.pseg2) | /* Phase buffer segment 2 */ + CAN_FDCBT_FRJW(priv->data_timing.pseg2); /* Resynchorinzation jump width same as PSEG2 */ + putreg32(regval, priv->base + S32K1XX_CAN_FDCBT_OFFSET); + + /* Additional CAN-FD configurations */ + + regval = getreg32(priv->base + S32K1XX_CAN_FDCTRL_OFFSET); + + regval |= CAN_FDCTRL_FDRATE | /* Enable bit rate switch in data phase of frame */ + CAN_FDCTRL_TDCEN | /* Enable transceiver delay compensation */ + CAN_FDCTRL_TDCOFF(5) | /* Setup 5 cycles for data phase sampling delay */ + CAN_FDCTRL_MBDSR0(3); /* Setup 64 bytes per message buffer (7 MB's) */ + putreg32(regval, priv->base + S32K1XX_CAN_FDCTRL_OFFSET); + + regval = getreg32(priv->base + S32K1XX_CAN_CTRL2_OFFSET); + regval |= CAN_CTRL2_ISOCANFDEN; + putreg32(regval, priv->base + S32K1XX_CAN_CTRL2_OFFSET); +#endif + + for (i = TXMBCOUNT; i < TOTALMBCOUNT; i++) + { + priv->rx[i].id.w = 0x0; + + /* FIXME sometimes we get a hard fault here */ + } + + putreg32(0x0, priv->base + S32K1XX_CAN_RXFGMASK_OFFSET); + + for (i = 0; i < TOTALMBCOUNT; i++) + { + putreg32(0, priv->base + S32K1XX_CAN_RXIMR_OFFSET(i)); + } + + for (i = 0; i < RXMBCOUNT; i++) + { + ninfo("Set MB%i to receive %p\r\n", i, &priv->rx[i]); + priv->rx[i].cs.edl = 0x1; + priv->rx[i].cs.brs = 0x1; + priv->rx[i].cs.esi = 0x0; + priv->rx[i].cs.code = 4; + priv->rx[i].cs.srr = 0x0; + priv->rx[i].cs.ide = 0x1; + priv->rx[i].cs.rtr = 0x0; + } + + putreg32(IFLAG1_RX, priv->base + S32K1XX_CAN_IFLAG1_OFFSET); + putreg32(IFLAG1_RX, priv->base + S32K1XX_CAN_IMASK1_OFFSET); + + /* Exit freeze mode */ + + s32k1xx_setfreeze(priv->base, 0); + if (!s32k1xx_waitfreezeack_change(priv->base, 0)) + { + ninfo("FLEXCAN: unfreeze fail\r\n"); + return -1; + } + + return 1; +} + +/**************************************************************************** + * Function: s32k1xx_reset + * + * Description: + * Put the EMAC in the non-operational, reset state + * + * Input Parameters: + * priv - Reference to the private FLEXCAN driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void s32k1xx_reset(struct s32k1xx_driver_s *priv) +{ + uint32_t regval; + uint32_t i; + + regval = getreg32(priv->base + S32K1XX_CAN_MCR_OFFSET); + regval |= CAN_MCR_SOFTRST; + putreg32(regval, priv->base + S32K1XX_CAN_MCR_OFFSET); + + if (!s32k1xx_waitmcr_change(priv->base, CAN_MCR_SOFTRST, 0)) + { + nerr("Reset failed"); + return; + } + + regval = getreg32(priv->base + S32K1XX_CAN_MCR_OFFSET); + regval &= ~(CAN_MCR_SUPV); + putreg32(regval, priv->base + S32K1XX_CAN_MCR_OFFSET); + + /* Initialize all MB rx and tx */ + + for (i = 0; i < TOTALMBCOUNT; i++) + { + ninfo("MB %i %p\r\n", i, &priv->rx[i]); + ninfo("MB %i %p\r\n", i, &priv->rx[i].id.w); + priv->rx[i].cs.cs = 0x0; + priv->rx[i].id.w = 0x0; + priv->rx[i].data[0].w00 = 0x0; + priv->rx[i].data[1].w00 = 0x0; + } + + regval = getreg32(priv->base + S32K1XX_CAN_MCR_OFFSET); + regval |= CAN_MCR_SLFWAK | CAN_MCR_WRNEN | CAN_MCR_SRXDIS | + CAN_MCR_IRMQ | CAN_MCR_AEN | + (((TOTALMBCOUNT - 1) << CAN_MCR_MAXMB_SHIFT) & + CAN_MCR_MAXMB_MASK); + putreg32(regval, priv->base + S32K1XX_CAN_MCR_OFFSET); + + regval = CAN_CTRL2_RRS | CAN_CTRL2_EACEN; + putreg32(regval, priv->base + S32K1XX_CAN_CTRL2_OFFSET); + + for (i = 0; i < TOTALMBCOUNT; i++) + { + putreg32(0, priv->base + S32K1XX_CAN_RXIMR_OFFSET(i)); + } + + /* Filtering catchall */ + + putreg32(0x3fffffff, priv->base + S32K1XX_CAN_RX14MASK_OFFSET); + putreg32(0x3fffffff, priv->base + S32K1XX_CAN_RX15MASK_OFFSET); + putreg32(0x3fffffff, priv->base + S32K1XX_CAN_RXMGMASK_OFFSET); + putreg32(0x0, priv->base + S32K1XX_CAN_RXFGMASK_OFFSET); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: s32k1xx_netinitialize + * + * Description: + * Initialize the Ethernet controller and driver + * + * Input Parameters: + * intf - In the case where there are multiple EMACs, this value + * identifies which EMAC is to be initialized. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +int s32k1xx_netinitialize(int intf) +{ + struct s32k1xx_driver_s *priv; + int ret; + + switch (intf) + { +#ifdef CONFIG_S32K1XX_FLEXCAN0 + case 0: + priv = &g_flexcan0; + memset(priv, 0, sizeof(struct s32k1xx_driver_s)); + priv->base = S32K1XX_FLEXCAN0_BASE; + priv->config = &s32k1xx_flexcan0_config; + + /* Default bitrate configuration */ + +# ifdef CONFIG_NET_CAN_CANFD + priv->arbi_timing.bitrate = CONFIG_FLEXCAN0_ARBI_BITRATE; + priv->arbi_timing.samplep = CONFIG_FLEXCAN0_ARBI_SAMPLEP; + priv->data_timing.bitrate = CONFIG_FLEXCAN0_DATA_BITRATE; + priv->data_timing.samplep = CONFIG_FLEXCAN0_DATA_SAMPLEP; +# else + priv->arbi_timing.bitrate = CONFIG_FLEXCAN0_BITRATE; + priv->arbi_timing.samplep = CONFIG_FLEXCAN0_SAMPLEP; +# endif + break; +#endif + +#ifdef CONFIG_S32K1XX_FLEXCAN1 + case 1: + priv = &g_flexcan1; + memset(priv, 0, sizeof(struct s32k1xx_driver_s)); + priv->base = S32K1XX_FLEXCAN1_BASE; + priv->config = &s32k1xx_flexcan1_config; + + /* Default bitrate configuration */ + +# ifdef CONFIG_NET_CAN_CANFD + priv->arbi_timing.bitrate = CONFIG_FLEXCAN1_ARBI_BITRATE; + priv->arbi_timing.samplep = CONFIG_FLEXCAN1_ARBI_SAMPLEP; + priv->data_timing.bitrate = CONFIG_FLEXCAN1_DATA_BITRATE; + priv->data_timing.samplep = CONFIG_FLEXCAN1_DATA_SAMPLEP; +# else + priv->arbi_timing.bitrate = CONFIG_FLEXCAN1_BITRATE; + priv->arbi_timing.samplep = CONFIG_FLEXCAN1_SAMPLEP; +# endif + break; +#endif + +#ifdef CONFIG_S32K1XX_FLEXCAN2 + case 2: + priv = &g_flexcan2; + memset(priv, 0, sizeof(struct s32k1xx_driver_s)); + priv->base = S32K1XX_FLEXCAN2_BASE; + priv->config = &s32k1xx_flexcan2_config; + + /* Default bitrate configuration */ + +# ifdef CONFIG_NET_CAN_CANFD + priv->arbi_timing.bitrate = CONFIG_FLEXCAN2_ARBI_BITRATE; + priv->arbi_timing.samplep = CONFIG_FLEXCAN2_ARBI_SAMPLEP; + priv->data_timing.bitrate = CONFIG_FLEXCAN2_DATA_BITRATE; + priv->data_timing.samplep = CONFIG_FLEXCAN2_DATA_SAMPLEP; +# else + priv->arbi_timing.bitrate = CONFIG_FLEXCAN2_BITRATE; + priv->arbi_timing.samplep = CONFIG_FLEXCAN2_SAMPLEP; +# endif + break; +#endif + + default: + return -ENODEV; + } + + if (!s32k1xx_bitratetotimeseg(&priv->arbi_timing, 1, 0)) + { + nerr("ERROR: Invalid CAN timings please try another sample point " + "or refer to the reference manual\n"); + return -1; + } + +#ifdef CONFIG_NET_CAN_CANFD + if (!s32k1xx_bitratetotimeseg(&priv->data_timing, 1, 1)) + { + nerr("ERROR: Invalid CAN data phase timings please try another " + "sample point or refer to the reference manual\n"); + return -1; + } +#endif + + s32k1xx_pinconfig(priv->config->tx_pin); + s32k1xx_pinconfig(priv->config->rx_pin); + if (priv->config->enable_pin > 0) + { + s32k1xx_pinconfig(priv->config->enable_pin); + s32k1xx_gpiowrite(priv->config->enable_pin, priv->config->enable_high); + } + + /* Attach the flexcan interrupt handler */ + + if (irq_attach(priv->config->bus_irq, s32k1xx_flexcan_interrupt, priv)) + { + /* We could not attach the ISR to the interrupt */ + + nerr("ERROR: Failed to attach CAN bus IRQ\n"); + return -EAGAIN; + } + + if (irq_attach(priv->config->error_irq, s32k1xx_flexcan_interrupt, priv)) + { + /* We could not attach the ISR to the interrupt */ + + nerr("ERROR: Failed to attach CAN error IRQ\n"); + return -EAGAIN; + } + + if (priv->config->lprx_irq > 0) + { + if (irq_attach(priv->config->lprx_irq, + s32k1xx_flexcan_interrupt, priv)) + { + /* We could not attach the ISR to the interrupt */ + + nerr("ERROR: Failed to attach CAN LPRX IRQ\n"); + return -EAGAIN; + } + } + + if (irq_attach(priv->config->mb_irq, s32k1xx_flexcan_interrupt, priv)) + { + /* We could not attach the ISR to the interrupt */ + + nerr("ERROR: Failed to attach CAN OR'ed Message buffer (0-15) IRQ\n"); + return -EAGAIN; + } + + /* Initialize the driver structure */ + + priv->dev.d_ifup = s32k1xx_ifup; /* I/F up (new IP address) callback */ + priv->dev.d_ifdown = s32k1xx_ifdown; /* I/F down callback */ + priv->dev.d_txavail = s32k1xx_txavail; /* New TX data callback */ +#ifdef CONFIG_NETDEV_IOCTL + priv->dev.d_ioctl = s32k1xx_ioctl; /* Support CAN ioctl() calls */ +#endif + priv->dev.d_private = (void *)priv; /* Used to recover private state from dev */ + +#ifdef TX_TIMEOUT_WQ + for (int i = 0; i < TXMBCOUNT; i++) + { + priv->txtimeout[i] = wd_create(); /* Create TX timeout timer */ + } + +#endif + priv->rx = (struct mb_s *)(priv->base + S32K1XX_CAN_MB_OFFSET); + priv->tx = (struct mb_s *)(priv->base + S32K1XX_CAN_MB_OFFSET + + (sizeof(struct mb_s) * RXMBCOUNT)); + + /* Put the interface in the down state. This usually amounts to resetting + * the device and/or calling s32k1xx_ifdown(). + */ + + ninfo("callbacks done\r\n"); + + s32k1xx_ifdown(&priv->dev); + + /* Register the device with the OS so that socket IOCTLs can be performed */ + + netdev_register(&priv->dev, NET_LL_CAN); + + UNUSED(ret); + return OK; +} + +/**************************************************************************** + * Name: arm_netinitialize + * + * Description: + * Initialize the first network interface. If there are more than one + * interface in the chip, then board-specific logic will have to provide + * this function to determine which, if any, Ethernet controllers should + * be initialized. + * + ****************************************************************************/ + +#if !defined(CONFIG_NETDEV_LATEINIT) +void arm_netinitialize(void) +{ +#ifdef CONFIG_S32K1XX_FLEXCAN0 + s32k1xx_netinitialize(0); +#endif + +#ifdef CONFIG_S32K1XX_FLEXCAN1 + s32k1xx_netinitialize(1); +#endif + +#ifdef CONFIG_S32K1XX_FLEXCAN2 + s32k1xx_netinitialize(2); +#endif +} +#endif + +#endif /* CONFIG_S32K1XX_FLEXCAN */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_flexcan.h b/arch/arm/src/s32k1xx/s32k1xx_flexcan.h new file mode 100644 index 0000000000..3b193321ac --- /dev/null +++ b/arch/arm/src/s32k1xx/s32k1xx_flexcan.h @@ -0,0 +1,115 @@ +/************************************************************************************ + * arch/arm/src/s32k1xx/s32k1xx_flexcan.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_FLEXCAN_H +#define __ARCH_ARM_SRC_S32K1XX_S32K1XX_FLEXCAN_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "hardware/s32k1xx_flexcan.h" + +#ifdef CONFIG_S32K1XX_FLEXCAN + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Function: arm_netinitialize + * + * Description: + * Initialize the first network interface. If there are more than one + * interface in the chip, then board-specific logic will have to provide + * this function to determine which, if any, Ethernet controllers should + * be initialized. Also prototyped in up_internal.h. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * Called very early in the initialization sequence. + * + ************************************************************************************/ + +void arm_netinitialize(void); + +/************************************************************************************ + * Function: s32k1xx_phy_boardinitialize + * + * Description: + * Some boards require specialized initialization of the PHY before it can be + * used. This may include such things as configuring GPIOs, resetting the PHY, + * etc. If CONFIG_S32K1XX_FLEXCAN_PHYINIT is defined in the configuration then the + * board specific logic must provide s32k1xx_phyinitialize(); The i.MX RT Ethernet + * driver will call this function one time before it first uses the PHY. + * + * Input Parameters: + * intf - Always zero for now. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_S32K1XX_FLEXCAN */ +#endif /* __ARCH_ARM_SRC_S32K1XX_S32K1XX_FLEXCAN_H */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_progmem.c b/arch/arm/src/s32k1xx/s32k1xx_progmem.c new file mode 100644 index 0000000000..78d6ad9bd0 --- /dev/null +++ b/arch/arm/src/s32k1xx/s32k1xx_progmem.c @@ -0,0 +1,424 @@ +/****************************************************************************** + * arch/arm/src/s32k1xx/s32k1xx_progmem.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +/****************************************************************************** + * Included Files + ******************************************************************************/ + +#include + +#include +#include +#include + +#include "arm_arch.h" + +#include "hardware/s32k1xx_ftfc.h" + +#include "s32k1xx_config.h" +#include "s32k1xx_progmem.h" + +#include "arm_internal.h" + +#include /* Include last: has dependencies */ + +/****************************************************************************** + * Pre-processor Definitions + ******************************************************************************/ +#ifdef CONFIG_MTD_SMART +# warning FlexNVM does not support back-to-back programming \ + thus SmartFS willt not work +#endif + +/****************************************************************************** + * Private Data + ******************************************************************************/ + +union fccob_flash_addr +{ + uint32_t addr; + struct + { + uint8_t fccob3; + uint8_t fccob2; + uint8_t fccob1; + uint8_t pad; + } fccobs; +}; + +/****************************************************************************** + * Private Functions + ******************************************************************************/ + +static inline void wait_ftfc_ready() +{ + while ((getreg8(S32K1XX_FTFC_FSTAT) & FTTC_FSTAT_CCIF) == 0) + { + /* Busy */ + } +} + +static uint32_t execute_ftfc_command() +{ + uint8_t regval; + uint32_t retval; + + /* Clear CCIF to launch command */ + + regval = getreg8(S32K1XX_FTFC_FSTAT); + regval |= FTTC_FSTAT_CCIF; + putreg8(regval, S32K1XX_FTFC_FSTAT); + + wait_ftfc_ready(); + + retval = getreg8(S32K1XX_FTFC_FSTAT); + + if (retval & (FTTC_FSTAT_MGSTAT0 | FTTC_FSTAT_FPVIOL | + FTTC_FSTAT_ACCERR | FTTC_FSTAT_RDCOLERR)) + { + return retval; /* Error has occured */ + } + else + { + return 0; /* success */ + } +} + +/****************************************************************************** + * Public Functions + ******************************************************************************/ + +/****************************************************************************** + * Name: up_progmem_neraseblocks + * + * Description: + * Return number of erase blocks + * + ******************************************************************************/ + +size_t up_progmem_neraseblocks(void) +{ + return S32K1XX_PROGMEM_SECTOR_COUNT; +} + +/****************************************************************************** + * Name: up_progmem_isuniform + * + * Description: + * Is program memory uniform or page size differs? + * + ******************************************************************************/ + +bool up_progmem_isuniform(void) +{ + return true; +} + +/****************************************************************************** + * Name: up_progmem_pagesize + * + * Description: + * Return read/write page size + * + ******************************************************************************/ + +size_t up_progmem_pagesize(size_t page) +{ + return (size_t)S32K1XX_PROGMEM_PAGE_SIZE; +} + +/****************************************************************************** + * Name: up_progmem_erasesize + * + * Description: + * Return erase block size + * + ******************************************************************************/ + +size_t up_progmem_erasesize(size_t block) +{ + return (size_t)S32K1XX_PROGMEM_BLOCK_SECTOR_SIZE; +} + +/****************************************************************************** + * Name: up_progmem_getpage + * + * Description: + * Address to read/write page conversion + * + * Input Parameters: + * addr - Address with or without flash offset (absolute or aligned to page0) + * + * Returned Value: + * Page or negative value on error. The following errors are reported + * (errno is not set!): + * + * -EFAULT: On invalid address + * + ******************************************************************************/ + +ssize_t up_progmem_getpage(size_t addr) +{ + if (addr >= S32K1XX_PROGMEM_START_ADDR) + { + addr -= S32K1XX_PROGMEM_START_ADDR; + } + + return (size_t)(addr / S32K1XX_PROGMEM_PAGE_SIZE); +} + +/****************************************************************************** + * Name: up_progmem_getaddress + * + * Description: + * Read/write page to address conversion + * + * Input Parameters: + * page - page index + * + * Returned Value: + * Base address of given page, SIZE_MAX if page index is not valid. + * + ******************************************************************************/ + +size_t up_progmem_getaddress(size_t page) +{ + return (size_t)(S32K1XX_PROGMEM_START_ADDR + + (page * S32K1XX_PROGMEM_PAGE_SIZE)); +} + +/****************************************************************************** + * Name: up_progmem_eraseblock + * + * Description: + * Erase selected block. + * + * Input Parameters: + * block - The erase block index to be erased. + * + * Returned Value: + * block size or negative value on error. The following errors are reported + * (errno is not set!): + * + * -EFAULT: On invalid page + * -EIO: On unsuccessful erase + * -EROFS: On access to write protected area + * -EACCES: Insufficient permissions (read/write protected) + * -EPERM: If operation is not permitted due to some other constraints + * (i.e. some internal block is not running etc.) + * + ******************************************************************************/ + +ssize_t up_progmem_eraseblock(size_t block) +{ + union fccob_flash_addr dest; + + dest.addr = (block * S32K1XX_PROGMEM_BLOCK_SECTOR_SIZE) + 0x800000; + + wait_ftfc_ready(); + + /* Clear FSTAT error bits */ + + putreg8(FTTC_FSTAT_FPVIOL | FTTC_FSTAT_ACCERR | FTTC_FSTAT_RDCOLERR, + S32K1XX_FTFC_FSTAT); + + /* Set FTFC command */ + + putreg8(S32K1XX_FTFC_ERASE_SECTOR, S32K1XX_FTFC_FCCOB0); + + /* Destination address of sector to erase */ + + putreg8(dest.fccobs.fccob1, S32K1XX_FTFC_FCCOB1); + putreg8(dest.fccobs.fccob2, S32K1XX_FTFC_FCCOB2); + putreg8(dest.fccobs.fccob3, S32K1XX_FTFC_FCCOB3); + + if (execute_ftfc_command() & (FTTC_FSTAT_MGSTAT0 | FTTC_FSTAT_FPVIOL | + FTTC_FSTAT_ACCERR | FTTC_FSTAT_RDCOLERR)) + { + return -EIO; /* Error has occured */ + } + + return (ssize_t)S32K1XX_PROGMEM_BLOCK_SECTOR_SIZE; +} + +/****************************************************************************** + * Name: up_progmem_ispageerased + * + * Description: + * Checks whether page is erased + * + * Input Parameters: + * page - The erase page index to be checked. + * + * Returned Value: + * Returns number of bytes NOT erased or negative value on error. If it + * returns zero then complete page is erased. + * + * The following errors are reported: + * -EFAULT: On invalid page + * + ******************************************************************************/ + +ssize_t up_progmem_ispageerased(size_t page) +{ + const uint8_t *p; + int i; + + if (page >= S32K1XX_PROGMEM_PAGE_COUNT) + { + return -EFAULT; + } + + p = (const uint8_t *)up_progmem_getaddress(page); + + for (i = 0; i < S32K1XX_PROGMEM_PAGE_SIZE; i++) + { + if (p[i] != 0xff) + { + break; + } + } + + return (ssize_t)(S32K1XX_PROGMEM_PAGE_SIZE - i); +} + +/****************************************************************************** + * Name: up_progmem_write + * + * Description: + * Program data at given address + * + * Note: this function is not limited to single page and nor it requires + * the address be aligned inside the page boundaries. + * + * Input Parameters: + * addr - Address with or without flash offset + * buf - Pointer to buffer + * count - Number of bytes to write + * + * Returned Value: + * Bytes written or negative value on error. The following errors are + * reported (errno is not set!) + * + * EINVAL: If count is not aligned with the flash boundaries (i.e. + * some MCU's require per half-word or even word access) + * EFAULT: On invalid address + * EIO: On unsuccessful write, do note when this occurs the complete + * flash sector is deemed to be unreadable and a read will most + * likely result in a hard fault. + * EROFS: On access to write protected area + * EACCES: Insufficient permissions (read/write protected) + * EPERM: If operation is not permitted due to some other constraints + * (i.e. some internal block is not running etc.) + * + ******************************************************************************/ + +ssize_t up_progmem_write(size_t addr, FAR const void *buf, size_t count) +{ + union fccob_flash_addr dest; + uint32_t i; + uint32_t j; + uint8_t *src; + + if (addr >= S32K1XX_PROGMEM_START_ADDR) + { + addr -= S32K1XX_PROGMEM_START_ADDR; + } + + if (count % S32K1XX_PROGMEM_DFLASH_WRITE_UNIT_SIZE != 0) + { + return -EINVAL; + } + + src = (uint8_t *)buf; + dest.addr = addr + 0x800000; + + for (i = 0; i < count / S32K1XX_PROGMEM_DFLASH_WRITE_UNIT_SIZE ; i++) + { + wait_ftfc_ready(); + + /* Clear FSTAT error bits */ + + putreg8(FTTC_FSTAT_FPVIOL | FTTC_FSTAT_ACCERR | FTTC_FSTAT_RDCOLERR, + S32K1XX_FTFC_FSTAT); + + /* Set FTFC command */ + + putreg8(S32K1XX_FTFC_PROGRAM_PHRASE, S32K1XX_FTFC_FCCOB0); + + /* Destination address */ + + putreg8(dest.fccobs.fccob1, S32K1XX_FTFC_FCCOB1); + putreg8(dest.fccobs.fccob2, S32K1XX_FTFC_FCCOB2); + putreg8(dest.fccobs.fccob3, S32K1XX_FTFC_FCCOB3); + + /* Write data */ + + for (j = 0; j < S32K1XX_PROGMEM_DFLASH_WRITE_UNIT_SIZE; j++) + { + putreg8(src[j], S32K1XX_FTFC_BASE + j + 0x8); + } + + if (execute_ftfc_command() & (FTTC_FSTAT_MGSTAT0 | FTTC_FSTAT_FPVIOL | + FTTC_FSTAT_ACCERR | FTTC_FSTAT_RDCOLERR)) + { + return -EIO; /* Error has occured */ + } + + dest.addr = dest.addr + S32K1XX_PROGMEM_DFLASH_WRITE_UNIT_SIZE; + src = src + S32K1XX_PROGMEM_DFLASH_WRITE_UNIT_SIZE; + } + + return count; +} + +void s32k1xx_progmem_init() +{ + /* Disable D-Flash Cache */ + + putreg32(0xc706b030, S32K1XX_MSCM_BASE + 0x404); + + /* Setup D-flash partitioning */ + + putreg8(S32K1XX_FTFC_PROGRAM_PARTITION, S32K1XX_FTFC_FCCOB0); /* Command */ + + putreg8(0x0, S32K1XX_FTFC_FCCOB1); /* CSEc key size */ + putreg8(0x0, S32K1XX_FTFC_FCCOB2); /* uSFE */ + putreg8(0x0, S32K1XX_FTFC_FCCOB3); /* Disable FlexRAM EEE */ + putreg8(0xf, S32K1XX_FTFC_FCCOB4); /* EEE Partition code */ + putreg8(0x0, S32K1XX_FTFC_FCCOB5); /* DE Partition code */ + + execute_ftfc_command(); +} diff --git a/arch/arm/src/s32k1xx/s32k1xx_progmem.h b/arch/arm/src/s32k1xx/s32k1xx_progmem.h new file mode 100644 index 0000000000..9b97d7798e --- /dev/null +++ b/arch/arm/src/s32k1xx/s32k1xx_progmem.h @@ -0,0 +1,95 @@ +/****************************************************************************** + * arch/arm/src/s32k1xx/s32k1xx_progmem.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __ARCH_ARM_SRC_S32K1XX_PROGMEM_H +#define __ARCH_ARM_SRC_S32K1XX_PROGMEM_H + +/****************************************************************************** + * Included Files + ******************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "up_internal.h" +#include "s32k1xx_config.h" + +/****************************************************************************** + * Pre-processor Definitions + ******************************************************************************/ + +#define DFLASH_SIZE CONFIG_PROGMEM_SIZE + +#if (DFLASH_SIZE % 2) == 1 +# error "Progmem size has to be a multiple of 2" +#endif + +#if defined(CONFIG_ARCH_CHIP_S32K14X) && (DFLASH_SIZE > 64) +# error "Progmem size is bigger than FlexNVM size" +#endif + +#if defined(CONFIG_ARCH_CHIP_S32K11X) && (DFLASH_SIZE > 32) +# error "Progmem size is bigger than FlexNVM size" +#endif + +/* Base address of the flash segment used for progmem. */ + +#define S32K1XX_PROGMEM_START_ADDR 0x10000000 + +#define S32K1XX_PROGMEM_BLOCK_COUNT 1 + +#define S32K1XX_PROGMEM_BLOCK_SIZE DFLASH_SIZE * 1024 + +#define S32K1XX_PROGMEM_BLOCK_SECTOR_SIZE 2048 + +#define S32K1XX_PROGMEM_PAGE_SIZE 8 + +#define S32K1XX_PROGMEM_SECTOR_COUNT S32K1XX_PROGMEM_BLOCK_SIZE / S32K1XX_PROGMEM_BLOCK_SECTOR_SIZE + +#define S32K1XX_PROGMEM_PAGE_COUNT (S32K1XX_PROGMEM_BLOCK_SIZE / S32K1XX_PROGMEM_PAGE_SIZE) + +#define S32K1XX_PROGMEM_DFLASH_WRITE_UNIT_SIZE 8 + +/****************************************************************************** + * Public Function Prototypes + ******************************************************************************/ + +void s32k1xx_progmem_init(); + +#endif /* __ARCH_ARM_SRC_S32K1XX_PROGMEM_H */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_rtc.c b/arch/arm/src/s32k1xx/s32k1xx_rtc.c index 7c70b76da5..85e7ad2064 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_rtc.c +++ b/arch/arm/src/s32k1xx/s32k1xx_rtc.c @@ -157,11 +157,11 @@ int up_rtc_initialize(void) putreg32(regval, S32K1XX_RTC_CR); - /* Set LPO_1KHZ clock source */ + /* Increment on 32.768Khz clock */ regval = getreg32(S32K1XX_RTC_CR); - regval |= RTC_CR_LPOS; + regval &= ~RTC_CR_LPOS; putreg32(regval, S32K1XX_RTC_CR); @@ -181,6 +181,18 @@ int up_rtc_initialize(void) putreg32(regval, S32K1XX_RTC_CR); + regval = getreg32(S32K1XX_RTC_SR); + + if (regval & RTC_SR_TIF) + { + regval &= ~RTC_SR_TCE; + putreg32(regval, S32K1XX_RTC_SR); + + /* Write TSR register to clear invalid */ + + putreg32(0x0, S32K1XX_RTC_TSR); + } + /* Enable the rtc */ s32k1xx_rtc_enable(); @@ -207,7 +219,7 @@ int up_rtc_initialize(void) * The current time in seconds * ****************************************************************************/ - +#ifndef CONFIG_RTC_HIRES time_t up_rtc_time(void) { uint32_t regval; @@ -217,6 +229,55 @@ time_t up_rtc_time(void) return (uint32_t) (regval); } +#endif + +/**************************************************************************** + * Name: up_rtc_gettime + * + * Description: + * Get the current time from the high resolution RTC clock/counter. This + * interface is only supported by the high-resolution RTC/counter hardware + * implementation. It is used to replace the system timer. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_HIRES +int up_rtc_gettime(FAR struct timespec *tp) +{ + irqstate_t flags; + uint32_t seconds; + uint32_t prescaler; + uint32_t prescaler2; + + /* Get prescaler and seconds register. this is in a loop which ensures that + * registers will be re-read if during the reads the prescaler has + * wrapped-around. + */ + + flags = enter_critical_section(); + do + { + prescaler = getreg32(S32K1XX_RTC_TPR); + seconds = getreg32(S32K1XX_RTC_TSR); + prescaler2 = getreg32(S32K1XX_RTC_TPR); + } + while (prescaler > prescaler2); + + leave_critical_section(flags); + + /* Build seconds + nanoseconds from seconds and prescaler register */ + + tp->tv_sec = seconds; + tp->tv_nsec = prescaler * (1000000000 / CONFIG_RTC_FREQUENCY); + return OK; +} +#endif /**************************************************************************** * Name: up_rtc_settime @@ -237,12 +298,28 @@ int up_rtc_settime(FAR const struct timespec *ts) { DEBUGASSERT(ts != NULL); + irqstate_t flags; + uint32_t seconds; + uint32_t prescaler; + + seconds = ts->tv_sec; +#ifdef CONFIG_RTC_HIRES + prescaler = ts->tv_nsec * (CONFIG_RTC_FREQUENCY / 1000000000); +#else + prescaler = 0; +#endif + + flags = enter_critical_section(); + s32k1xx_rtc_disable(); - putreg32((uint32_t)ts->tv_sec, S32K1XX_RTC_TSR); + putreg32(prescaler, S32K1XX_RTC_TPR); /* Always write prescaler first */ + putreg32(seconds, S32K1XX_RTC_TSR); s32k1xx_rtc_enable(); + leave_critical_section(flags); + return OK; } diff --git a/arch/arm/src/s32k1xx/s32k1xx_rtc.h b/arch/arm/src/s32k1xx/s32k1xx_rtc.h index b00c3d38b9..35ce10d265 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_rtc.h +++ b/arch/arm/src/s32k1xx/s32k1xx_rtc.h @@ -58,14 +58,6 @@ # error CONFIG_RTC_PERIODIC should not be selected with this driver # endif -/* REVISIT: This is probably supportable. The 47 bit timer does have - * accuracy greater than 1 second. - */ - -# ifdef CONFIG_RTC_HIRES -# error CONFIG_RTC_PERIODIC should not be selected with this driver -# endif - /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/arch/arm/src/s32k1xx/s32k1xx_start.c b/arch/arm/src/s32k1xx/s32k1xx_start.c index 542e152547..430d52d863 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_start.c +++ b/arch/arm/src/s32k1xx/s32k1xx_start.c @@ -65,6 +65,10 @@ #include "hardware/s32k1xx_mpu.h" #endif +#ifdef CONFIG_S32K1XX_PROGMEM +#include "s32k1xx_progmem.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -353,6 +357,10 @@ void __start(void) #endif showprogress('E'); +#ifdef CONFIG_S32K1XX_PROGMEM + s32k1xx_progmem_init(); +#endif + /* For the case of the separate user-/kernel-space build, perform whatever * platform specific initialization of the user memory is required. * Normally this just means initializing the user space .data and .bss diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_bringup.c b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_bringup.c index bc0abbf10a..0adea7e4e9 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_bringup.c +++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_bringup.c @@ -143,5 +143,16 @@ int s32k1xx_bringup(void) #endif #endif +#ifdef CONFIG_S32K1XX_PROGMEM + FAR struct mtd_dev_s *mtd; + int minor = 0; + + mtd = progmem_initialize(); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: progmem_initialize failed\n"); + } +#endif + return ret; } diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_clockconfig.c b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_clockconfig.c index 3cf1656fed..126904f479 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_clockconfig.c +++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_clockconfig.c @@ -165,7 +165,7 @@ const struct clock_configuration_s g_initial_clkconfig = }, .lpoclk = /* Low Power Clock configuration. */ { - .rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */ + .rtc_source = SIM_RTCCLK_SEL_LPO_32K, /* RTCCLKSEL */ .lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */ .initialize = true, /* Initialize */ .lpo32k = true, /* LPO32KCLKEN */ diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/configs/nsh/defconfig b/boards/arm/s32k1xx/rddrone-uavcan146/configs/nsh/defconfig index 5b68d474ea..ef179824de 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan146/configs/nsh/defconfig +++ b/boards/arm/s32k1xx/rddrone-uavcan146/configs/nsh/defconfig @@ -69,3 +69,32 @@ CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_CXXINITIALIZE=y CONFIG_SYSTEM_SPITOOL=y CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_S32K1XX_FLEXCAN0=y +CONFIG_S32K1XX_FLEXCAN1=y +CONFIG_NET=y +CONFIG_NET_ETHERNET=n +CONFIG_NET_IPv4=n +CONFIG_ARCH_HAVE_NET=y +CONFIG_NET_READAHEAD=y +CONFIG_NSOCKET_DESCRIPTORS=8 +CONFIG_NET_NACTIVESOCKETS=16 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_CANPROTO_OPTIONS=y +CONFIG_NET_CAN=y +CONFIG_NET_CAN_HAVE_TX_DEADLINE=y +CONFIG_CAN_CONNS=4 +CONFIG_NET_CAN_SOCK_OPTS=y +CONFIG_NET_CAN_RAW_FILTER_MAX=32 +CONFIG_NET_TIMESTAMP=y +CONFIG_NET_CMSG=y +CONFIG_NETDEV_IFINDEX=y +CONFIG_NSH_NETINIT=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPNTHREADS=1 +CONFIG_SCHED_LPWORKPRIORITY=100 +CONFIG_SCHED_LPWORKSTACKSIZE=2048 +CONFIG_S32K1XX_RTC=y +CONFIG_RTC=y +CONFIG_RTC_HIRES=y +CONFIG_RTC_FREQUENCY=32768 +CONFIG_SIG_DEFAULT=y diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/include/board.h b/boards/arm/s32k1xx/rddrone-uavcan146/include/board.h index c0ab9d1d96..fbe1f799f9 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan146/include/board.h +++ b/boards/arm/s32k1xx/rddrone-uavcan146/include/board.h @@ -150,4 +150,14 @@ #define PIN_LPI2C0_SCL PIN_LPI2C0_SCL_2 /* PTA3 */ #define PIN_LPI2C0_SDA PIN_LPI2C0_SDA_2 /* PTA2 */ +/* CAN selections ***********************************************************/ +#define PIN_CAN0_TX PIN_CAN0_TX_4 /* PTE5 */ +#define PIN_CAN0_RX PIN_CAN0_RX_4 /* PTE4 */ +#define PIN_CAN0_ENABLE (GPIO_OUTPUT | PIN_PORTE | PIN11 ) +#define CAN0_ENABLE_OUT 0 +#define PIN_CAN1_TX PIN_CAN1_TX_1 /* PTA13 */ +#define PIN_CAN1_RX PIN_CAN1_RX_1 /* PTA12 */ +#define PIN_CAN1_ENABLE (GPIO_OUTPUT | PIN_PORTE | PIN10 ) +#define CAN1_ENABLE_OUT 0 + #endif /* __BOARDS_ARM_RDDRONE_UAVCAN146_INCLUDE_BOARD_H */ diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/rddrone-uavcan146.h b/boards/arm/s32k1xx/rddrone-uavcan146/src/rddrone-uavcan146.h index 2ab91bdfe2..e5532a210e 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan146/src/rddrone-uavcan146.h +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/rddrone-uavcan146.h @@ -69,14 +69,12 @@ #define GPIO_LED_G (PIN_PTD16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) #define GPIO_LED_B (PIN_PTD0 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) -/* Buttons. The RDDRONE-UAVCAN146 supports two buttons: +/* Buttons. The RDDRONE-UAVCAN146 supports one button: * - * SW2 PTC12 - * SW3 PTC13 + * SW3 PTC14 */ -#define GPIO_SW2 (PIN_PTC12 | PIN_INT_BOTH) -#define GPIO_SW3 (PIN_PTC13 | PIN_INT_BOTH) +#define GPIO_SW3 (PIN_PTC14 | PIN_INT_BOTH) /* SPI chip selects */ @@ -86,7 +84,7 @@ /* Count of peripheral clock user configurations */ -#define NUM_OF_PERIPHERAL_CLOCKS_0 11 +#define NUM_OF_PERIPHERAL_CLOCKS_0 12 /**************************************************************************** * Public Types diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c index 300f08e9a4..c792546af1 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c @@ -140,5 +140,16 @@ int s32k1xx_bringup(void) #endif #endif +#ifdef CONFIG_S32K1XX_PROGMEM + FAR struct mtd_dev_s *mtd; + int minor = 0; + + mtd = progmem_initialize(); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: progmem_initialize failed\n"); + } +#endif + return ret; } diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_buttons.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_buttons.c index ff48587baf..b51aceea2d 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_buttons.c +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_buttons.c @@ -33,10 +33,9 @@ * ****************************************************************************/ -/* The RDDRONE-UAVCAN146 supports two buttons: +/* The RDDRONE-UAVCAN146 supports one button: * - * SW2 PTC12 - * SW3 PTC13 + * SW3 PTC14 */ /**************************************************************************** @@ -77,7 +76,6 @@ uint32_t board_button_initialize(void) { /* Configure the GPIO pins as interrupting inputs. */ - s32k1xx_pinconfig(GPIO_SW2); s32k1xx_pinconfig(GPIO_SW3); return NUM_BUTTONS; } @@ -90,11 +88,6 @@ uint32_t board_buttons(void) { uint32_t ret = 0; - if (s32k1xx_gpioread(GPIO_SW2)) - { - ret |= BUTTON_SW2_BIT; - } - if (s32k1xx_gpioread(GPIO_SW3)) { ret |= BUTTON_SW3_BIT; @@ -133,11 +126,7 @@ int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) /* Map the button id to the GPIO bit set. */ - if (id == BUTTON_SW2) - { - pinset = GPIO_SW2; - } - else if (id == BUTTON_SW3) + if (id == BUTTON_SW3) { pinset = GPIO_SW3; } diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_clockconfig.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_clockconfig.c index 6ec3679393..badf9be072 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_clockconfig.c +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_clockconfig.c @@ -165,7 +165,7 @@ const struct clock_configuration_s g_initial_clkconfig = }, .lpoclk = /* Low Power Clock configuration. */ { - .rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */ + .rtc_source = SIM_RTCCLK_SEL_LPO_32K, /* RTCCLKSEL */ .lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */ .initialize = true, /* Initialize */ .lpo32k = true, /* LPO32KCLKEN */ diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_periphclocks.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_periphclocks.c index e6f84c9fb8..9fd3f7284d 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_periphclocks.c +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_periphclocks.c @@ -73,7 +73,7 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = { { .clkname = FLEXCAN0_CLK, -#ifdef CONFIG_S32K1XX_FLEXCAN +#ifdef CONFIG_S32K1XX_FLEXCAN0 .clkgate = true, #else .clkgate = false, @@ -81,7 +81,7 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = }, { .clkname = FLEXCAN1_CLK, -#ifdef CONFIG_S32K1XX_FLEXCAN +#ifdef CONFIG_S32K1XX_FLEXCAN1 .clkgate = true, #else .clkgate = false, @@ -143,6 +143,14 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = .clkname = PORTE_CLK, .clkgate = true, }, + { + .clkname = RTC0_CLK, +#ifdef CONFIG_S32K1XX_RTC + .clkgate = true, +#else + .clkgate = false, +#endif + }, }; /**************************************************************************** diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_bringup.c b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_bringup.c index 495468a784..81615fce25 100644 --- a/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_bringup.c +++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_bringup.c @@ -105,5 +105,16 @@ int s32k1xx_bringup(void) } #endif +#ifdef CONFIG_S32K1XX_PROGMEM + FAR struct mtd_dev_s *mtd; + int minor = 0; + + mtd = progmem_initialize(); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: progmem_initialize failed\n"); + } +#endif + return ret; } diff --git a/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_bringup.c b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_bringup.c index 607b3d41d4..ec88b7b293 100644 --- a/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_bringup.c +++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_bringup.c @@ -137,5 +137,16 @@ int s32k1xx_bringup(void) } #endif +#ifdef CONFIG_S32K1XX_PROGMEM + FAR struct mtd_dev_s *mtd; + int minor = 0; + + mtd = progmem_initialize(); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: progmem_initialize failed\n"); + } +#endif + return ret; } diff --git a/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_clockconfig.c b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_clockconfig.c index e9078823d5..fe3e26363f 100644 --- a/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_clockconfig.c +++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_clockconfig.c @@ -165,7 +165,7 @@ const struct clock_configuration_s g_initial_clkconfig = }, .lpoclk = /* Low Power Clock configuration. */ { - .rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */ + .rtc_source = SIM_RTCCLK_SEL_LPO_32K, /* RTCCLKSEL */ .lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */ .initialize = true, /* Initialize */ .lpo32k = true, /* LPO32KCLKEN */ diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_bringup.c b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_bringup.c index 830d574fab..c04617a4ed 100644 --- a/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_bringup.c +++ b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_bringup.c @@ -137,5 +137,16 @@ int s32k1xx_bringup(void) } #endif +#ifdef CONFIG_S32K1XX_PROGMEM + FAR struct mtd_dev_s *mtd; + int minor = 0; + + mtd = progmem_initialize(); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: progmem_initialize failed\n"); + } +#endif + return ret; } diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_clockconfig.c b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_clockconfig.c index 37596e606a..3481093108 100644 --- a/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_clockconfig.c +++ b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_clockconfig.c @@ -165,7 +165,7 @@ const struct clock_configuration_s g_initial_clkconfig = }, .lpoclk = /* Low Power Clock configuration. */ { - .rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */ + .rtc_source = SIM_RTCCLK_SEL_LPO_32K, /* RTCCLKSEL */ .lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */ .initialize = true, /* Initialize */ .lpo32k = true, /* LPO32KCLKEN */ diff --git a/boards/arm/s32k1xx/s32k148evb/include/board.h b/boards/arm/s32k1xx/s32k148evb/include/board.h index be8ccdf64d..06f3c3ca8d 100644 --- a/boards/arm/s32k1xx/s32k148evb/include/board.h +++ b/boards/arm/s32k1xx/s32k148evb/include/board.h @@ -133,4 +133,12 @@ #define PIN_LPUART1_RX PIN_LPUART1_RX_1 /* PTC6 */ #define PIN_LPUART1_TX PIN_LPUART1_TX_1 /* PTC7 */ +/* CAN selections ***********************************************************/ +#define PIN_CAN0_TX PIN_CAN0_TX_1 +#define PIN_CAN0_RX PIN_CAN0_RX_1 +#define PIN_CAN1_TX PIN_CAN1_TX_1 +#define PIN_CAN1_RX PIN_CAN1_RX_1 +#define PIN_CAN2_TX PIN_CAN2_TX_1 +#define PIN_CAN2_RX PIN_CAN2_RX_1 + #endif /* __BOARDS_ARM_S32K148EVB_INCLUDE_BOARD_H */ diff --git a/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_clockconfig.c b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_clockconfig.c index d41060bbfb..ac597ce531 100644 --- a/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_clockconfig.c +++ b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_clockconfig.c @@ -165,7 +165,7 @@ const struct clock_configuration_s g_initial_clkconfig = }, .lpoclk = /* Low Power Clock configuration. */ { - .rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */ + .rtc_source = SIM_RTCCLK_SEL_LPO_32K, /* RTCCLKSEL */ .lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */ .initialize = true, /* Initialize */ .lpo32k = true, /* LPO32KCLKEN */