arch/arm/src/samd5e5: Updates to clock configuration from initial testing. With these changes the boot up gets through clock configuration but hangs in the low-level USART configuration before completing the boot.
This commit is contained in:
Gregory Nutt
parent
345d088661
commit
ff906b0bef
@ -48,7 +48,7 @@
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* Pre-processor Definitions
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********************************************************************************************/
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#define SAM_NGLCK 12 /* 12 Clock generators, 0-11 */
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#define SAM_NGCLK 12 /* 12 Clock generators, 0-11 */
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#define SAM_NCHANNELS 48 /* 48 Clock generators, 0..47 */
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/* GCLK register offsets ********************************************************************/
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@ -98,7 +98,7 @@
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# define GCLK_GENCTRL_SRC_XOSC0 (0 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC 0 oscillator input */
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# define GCLK_GENCTRL_SRC_XOSC1 (1 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC 1 oscillator input */
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# define GCLK_GENCTRL_SRC_GCLK_IN (2 << GCLK_GENCTRL_SRC_SHIFT) /* Generator input pad */
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# define GCLK_GENCTRL_SRC_GLCK_GEN1 (3 << GCLK_GENCTRL_SRC_SHIFT) /* Generic clock generater 1 output */
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# define GCLK_GENCTRL_SRC_GCLK_GEN1 (3 << GCLK_GENCTRL_SRC_SHIFT) /* Generic clock generater 1 output */
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# define GCLK_GENCTRL_SRC_OSCULP32K (4 << GCLK_GENCTRL_SRC_SHIFT) /* OSCULP32K oscillator output */
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# define GCLK_GENCTRL_SRC_XOSC32K (5 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC32K oscillator output */
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# define GCLK_GENCTRL_SRC_DFLL (6 << GCLK_GENCTRL_SRC_SHIFT) /* DFLL oscillator output */
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@ -277,7 +277,7 @@
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#define OSCCTRL_DPLLCTRLB_REFLCK_SHIFT (5) /* Bits 5-7: Reference clock selection */
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#define OSCCTRL_DPLLCTRLB_REFLCK_MASK (3 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT)
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# define OSCCTRL_DPLLCTRLB_REFLCK(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT)
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# define OSCCTRL_DPLLCTRLB_REFLCK_GLCK (0 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* Dedicated GCLK clock reference */
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# define OSCCTRL_DPLLCTRLB_REFLCK_GCLK (0 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* Dedicated GCLK clock reference */
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# define OSCCTRL_DPLLCTRLB_REFLCK_XOSC32 (1 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC32K clock reference (default) */
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# define OSCCTRL_DPLLCTRLB_REFLCK_XOSC0 (2 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC0 clock reference */
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# define OSCCTRL_DPLLCTRLB_REFLCK_XOSC1 (3 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC2 clock reference */
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@ -78,8 +78,8 @@ static const struct sam_clockconfig_s g_initial_clocking =
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{
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.waitstates = BOARD_FLASH_WAITSTATES,
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.cpudiv = BOARD_MCLK_CPUDIV,
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.glckset1 = BOARD_GCLK_SET1,
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.glckset2 = BOARD_GCLK_SET2,
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.gclkset1 = BOARD_GCLK_SET1,
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.gclkset2 = BOARD_GCLK_SET2,
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.cpu_frequency = BOARD_CPU_FREQUENCY,
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#if BOARD_HAVE_XOSC32K != 0
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.xosc32k =
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@ -141,6 +141,7 @@ static const struct sam_clockconfig_s g_initial_clocking =
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.bplckc = BOARD_DFLL_BPLCKC,
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.waitlock = BOARD_DFLL_WAITLOCK,
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.caliben = BOARD_DFLL_CALIBEN,
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.gclklock = BOARD_DFLL_GCLKLOCK,
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.fcalib = BOARD_DFLL_FCALIB,
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.ccalib = BOARD_DFLL_CCALIB,
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.fstep = BOARD_DFLL_FSTEP,
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@ -157,6 +158,7 @@ static const struct sam_clockconfig_s g_initial_clocking =
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.wuf = BOARD_DPLL0_WUF,
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.runstdby = BOARD_DPLL0_RUNSTDBY,
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.ondemand = BOARD_DPLL0_ONDEMAND,
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.reflock = BOARD_DPLL0_REFLOCK,
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.refclk = BOARD_DPLL0_REFCLK,
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.ltime = BOARD_DPLL0_LTIME,
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.filter = BOARD_DPLL0_FILTER,
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@ -173,6 +175,7 @@ static const struct sam_clockconfig_s g_initial_clocking =
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.wuf = BOARD_DPLL1_WUF,
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.runstdby = BOARD_DPLL1_RUNSTDBY,
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.ondemand = BOARD_DPLL1_ONDEMAND,
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.reflock = BOARD_DPLL1_REFLOCK,
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.refclk = BOARD_DPLL1_REFCLK,
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.ltime = BOARD_DPLL1_LTIME,
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.filter = BOARD_DPLL1_FILTER,
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@ -609,7 +612,7 @@ static inline void sam_mclk_configure(uint8_t cpudiv)
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* Name: sam_gclk_configure
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*
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* Description:
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* Configure one GLCK
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* Configure one GCLK
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*
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****************************************************************************/
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@ -618,11 +621,11 @@ static void sam_gclk_configure(uintptr_t regaddr,
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{
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uint32_t regval;
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/* Are we enabling or disabling the GLCK? */
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/* Are we enabling or disabling the GCLK? */
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if (config->enable)
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{
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/* Get the GLCK configuration */
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/* Get the GCLK configuration */
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regval = GCLK_GENCTRL_SRC(config->source) | GCLK_GENCTRL_GENEN |
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GCLK_GENCTRL1_DIV(config->div);
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@ -654,7 +657,7 @@ static void sam_gclk_configure(uintptr_t regaddr,
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}
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else
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{
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/* Disable the GLCK */
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/* Disable the GCLK */
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regval = 0;
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}
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@ -668,7 +671,7 @@ static void sam_gclk_configure(uintptr_t regaddr,
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* Name: sam_gclkset_configure
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*
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* Description:
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* Configure a set of GLCKs
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* Configure a set of GCLKs
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*
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****************************************************************************/
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@ -680,7 +683,7 @@ static void sam_gclkset_configure(uint16_t gclkset,
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/* Try every GCLK */
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for (gclk = 0; gclk < SAM_NGLCK && gclkset != 0; gclk++)
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for (gclk = 0; gclk < SAM_NGCLK && gclkset != 0; gclk++)
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{
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/* Check if this one is in the set */
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@ -720,14 +723,17 @@ static void sam_dfll_configure(const struct sam_dfll_config_s *config)
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putreg8(0, SAM_OSCCTRL_DFLLCTRLA);
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/* If we are running in closed loop mode and we are in USB clock recover
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* mode, then set up the input source GCLK channel.
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* mode, then set up the input source GCLK channel (unless it has already
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* been configured and the configuration is locked).
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*/
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if (config->usbcrm && config->mode)
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if (config->usbcrm && config->mode &&
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!sam_gclk_chan_locked(GCLK_CHAN_OSCCTRL_DFLL))
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{
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/* Configure the GCLK channel */
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/* Configure the DFLL GCLK channel to use the GCLK source. */
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sam_gclk_chan_enable(GCLK_CHAN_OSCCTRL_DFLL, config->gclk, true);
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sam_gclk_chan_enable(GCLK_CHAN_OSCCTRL_DFLL, config->gclk,
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(bool)config->gclklock);
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}
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/* Setup the DFLLMUL register */
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@ -905,7 +911,7 @@ static void sam_dfll_gclkready(const struct sam_dfll_config_s *config)
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{
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}
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/* Set the source of GLCK0 to to the configured source. */
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/* Set the source of GCLK0 to to the configured source. */
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regval32 = getreg32(SAM_GCLK_GENCTRL(0));
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regval32 &= ~GCLK_GENCTRL_SRC_MASK;
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@ -924,15 +930,16 @@ static void sam_dfll_gclkready(const struct sam_dfll_config_s *config)
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static void sam_dpll_gclkchannel(uint8_t chan,
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const struct sam_dpll_config_s *config)
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{
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/* Check if we are using a dedicated GCLK as the reference clock (vs. the
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* common GCLK0).
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/* Check if we are using a dedicated GCLK as the reference clock. If so
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* configure GCLK unless it has already been configured and configuration
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* registers have been locked.
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*/
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if (config->refclk != 0)
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if (config->refclk == 0 && !sam_gclk_chan_locked(chan))
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{
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/* Yes.. configure the GCLK channel */
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/* Yes.. configure the GCLK channel that will be used as refclk source */
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sam_gclk_chan_enable(chan, config->gclk, true);
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sam_gclk_chan_enable(chan, config->gclk, (bool)config->reflock);
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}
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}
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@ -1109,7 +1116,7 @@ void sam_clock_configure(const struct sam_clockconfig_s *config)
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/* Pre-configure some GCLKs before configuring the DPLLs */
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sam_gclkset_configure(config->glckset1, config->gclk);
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sam_gclkset_configure(config->gclkset1, config->gclk);
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/* Configure loops: DFLL, DPLL0, and DPLL1. */
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@ -1117,7 +1124,7 @@ void sam_clock_configure(const struct sam_clockconfig_s *config)
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/* Configure the renaming GCLKs before configuring the DPLLs */
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sam_gclkset_configure(config->glckset2, config->gclk);
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sam_gclkset_configure(config->gclkset2, config->gclk);
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/* Check if the number of wait states is increasing or decreasing */
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@ -127,6 +127,7 @@ struct sam_dfll_config_s
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uint8_t bplckc : 1; /* Bypass coarse clock */
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uint8_t waitlock : 1; /* Wait lock */
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uint8_t caliben : 1; /* Overwrite factory calibration */
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uint8_t gclklock : 1; /* Lock GCLK source clock configuration */
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uint8_t fcalib; /* Fine calibration value (if caliben != 0) */
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uint8_t ccalib; /* Coarse calibration value (if caliben != 0) */
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uint8_t fstep; /* Fine maximum step */
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@ -145,6 +146,7 @@ struct sam_dpll_config_s
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uint8_t wuf : 1; /* Wake up fast */
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uint8_t runstdby : 1; /* Run in standby */
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uint8_t ondemand : 1; /* On demand clock activation */
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uint8_t reflock : 1; /* Lock GCLK clock reference configuration */
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uint8_t refclk; /* Reference clock selection
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* 0 Dedicated GCLK clock reference
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* 1 XOSC32K clock reference
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@ -190,7 +192,7 @@ struct sam_gclk_config_s
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uint8_t oe : 1; /* True: Output enable */
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uint8_t divsel : 1; /* True: Clock source divider */
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uint8_t runstdby : 1; /* Run in standby */
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uint8_t source; /* GLCK clock source:
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uint8_t source; /* GCLK clock source:
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* 0 XOSC 0 oscillator input
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* 1 XOSC 1 oscillator input
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* 2 Generator input pad
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@ -209,8 +211,8 @@ struct sam_clockconfig_s
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{
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uint8_t waitstates; /* NVM read wait states 9-15 */
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uint8_t cpudiv; /* MCLK divider to get CPU frequency */
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uint16_t glckset1; /* GLCKs to initialize prior to DPLL init */
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uint16_t glckset2; /* GLCKs to initialize after to DPLL init */
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uint16_t gclkset1; /* GCLKs to initialize prior to DPLL init */
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uint16_t gclkset2; /* GCLKs to initialize after to DPLL init */
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uint32_t cpu_frequency; /* Resulting CPU frequency */
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#if BOARD_HAVE_XOSC32K != 0
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struct sam_xosc32_config_s xosc32k; /* XOSC32 configuration */
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@ -223,7 +225,7 @@ struct sam_clockconfig_s
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#endif
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struct sam_dfll_config_s dfll; /* DFLL configuration */
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struct sam_dpll_config_s dpll[2]; /* DPLL0/1 configurations */
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struct sam_gclk_config_s gclk[12]; /* GLCK configurations */
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struct sam_gclk_config_s gclk[12]; /* GCLK configurations */
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};
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/************************************************************************************
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@ -145,10 +145,10 @@ int sam_eic_initialize(void)
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*/
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regaddr = SAM_GCLK_PCHCTRL(GCLK_CHAN_EIC);
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regval = GCLK_PCHCTRL_GEN(BOARD_GLCK_EIC) | GCLK_PCHCTRL_CHEN;
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regval = GCLK_PCHCTRL_GEN(BOARD_GCLK_EIC) | GCLK_PCHCTRL_CHEN;
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putreg32(regval, regaddr);
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/* Enable the EIC, selecting clocking via the GLCK_EIC */
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/* Enable the EIC, selecting clocking via the GCLK_EIC */
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putreg8(EIC_CTRLA_ENABLE | EIC_CTRLA_ENABLE, SAM_EIC_CTRLA);
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sam_eic_syncwait();
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/arm/src/samd5e5/sam_glck.c
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* arch/arm/src/samd5e5/sam_gclk.c
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -61,7 +61,7 @@
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* the clock domains is complete.
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*
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* Input Parameters:
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* glck - GCLK clock index
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* gclk - GCLK clock index
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*
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* Returned Value:
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* None
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@ -233,7 +233,7 @@ void sam_gclk_chan_enable(uint8_t channel, uint8_t srcgen, bool wrlock)
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/* Configure the peripheral channel */
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regval = GCLK_PCHCTRL_GEN(srcgen);
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regval = GCLK_PCHCTRL_GEN(srcgen);
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putreg32(regval, regaddr);
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/* Enable the peripheral channel, setting the writelock if so requested. */
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@ -45,6 +45,7 @@
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#include <stdint.h>
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#include <stdbool.h>
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#include "up_arch.h"
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#include "sam_config.h"
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#include "chip/sam_gclk.h"
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@ -141,6 +142,39 @@ void sam_gclk_chan_enable(uint8_t channel, uint8_t srcgen, bool wrlock);
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void sam_gclk_chan_disable(uint8_t channel);
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/****************************************************************************
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* Name: sam_gclk_chan_locked
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*
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* Description:
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* Return true if the GCLK cannot be configured because the wrtlock is set
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* int the PCHCTRL register.
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*
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* Input Parameters:
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* channel - Index of the GCLK channel to be checked
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*
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* Returned Value:
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* True if the the wrtlock bit is set in the channel's PCHCTRL register.
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*
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****************************************************************************/
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static inline bool sam_gclk_chan_locked(uint8_t channel)
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{
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uint32_t regaddr;
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uint32_t regval;
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/* Get the address of the peripheral channel control register */
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regaddr = SAM_GCLK_PCHCTRL(channel);
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/* Get content of the peripheral channel control register */
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regval = getreg32(regaddr);
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/* Return true if the WRTLOCK bit is set in the register */
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return (regval & GCLK_PCHCTRL_WRTLOCK) != 0;
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}
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#undef EXTERN
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#if defined(__cplusplus)
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}
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@ -36,18 +36,21 @@ STATUS
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There is a placeholder from the SAML21, but it is currently stubbed out
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in the Make.defs file. Configuration options in the board.h header
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file are bogus and also just cloned from the SAML21.
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2018-07-29: Clock configuration logic now complete. board.h
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configuration options still need to be verified. Unverified SERCOM
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USART, SPI, I2C, Port configuration, and DMA support have been added.
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I still have no hardware in hand to test.
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2018-07-20: Brought in the USB driver from the SAML21. It is the same
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USB IP with only small differences. There a a few, small open issues
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still to be resolved.
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2018-08-01: Hardware in hand. Initial attempts to program the board
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using a Segger J-Link connected via SWD were unsuccessful. I believe
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that the FLASH is locked. See "Unlocking FLASH with J-Link Commander"
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below. After unlocking the FLASH, I was able to successfully write
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the NuttX image.
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using a Segger J-Link connected via SWD were unsuccessful because the
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Metro M4 comes with an application in FLASH and the FLASH locked. See
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"Unlocking FLASH with J-Link Commander" below. After unlocking the
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FLASH, I was able to successfully write the NuttX image.
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Unfortunately, the board seems to have become unusable after the first
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NuttX image was written to FLASH. I am unable to connect the JTAG
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@ -56,17 +59,23 @@ STATUS
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to halt the CPU.
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This is most likely a consequence of something happening in the NuttX
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boot-up sequence that interferes with JTAG operation. When I continue
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debugging in the future, I will put an infinite loop, branch-on-self
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at the code startup up (__start) so that I can attached the debugger
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and step through the initial configuration.
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boot-up sequence that interferes with JTAG operation.
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Future me: This boot-up failure was do to bad clock initialization
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logic that caused infinite loops during clock configuration. Unlocking
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and erasing the FLASH is innocuous, but the JTAG will apparently not
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work if the clocks are not in a good state.
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2018-08-03: Added a configuration option to run out of SRAM vs FLASH.
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This should be a safer way to do the initial board bring-up since
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it does not modify the FLASH image nor does it require unlocking
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the FLASH pages.
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2018-08-31: I finally have a new Metro M4 and have been successfully
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debugging from SRAM. Several errors in clock configuration logic
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have been corrected but it still hangs in the clock configuration.
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debugging from SRAM (with FLASH unlocked and erased). Several
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errors in clock configuration logic have been corrected and it now
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gets through clock configuration okay. It now hangs in the low-level
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USART initialzation.
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Unlocking FLASH
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===============
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@ -167,6 +176,15 @@ Unlocking FLASH
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You will, of course, have to change the path as appropriate for your system.
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4. Erase FLASH (optional)
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J-Link>erase
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Erasing device (ATSAMD51P19)...
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J-Link: Flash download: Total time needed: 2.596s (Prepare: 0.031s, Compare: 0.000s, Erase: 2.553s, Program: 0.000s, Verify: 0.000s, Restore: 0.012s)
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J-Link: Flash download: Total time needed: 0.066s (Prepare: 0.038s, Compare: 0.000s, Erase: 0.016s, Program: 0.000s, Verify: 0.000s, Restore: 0.010s)
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Erasing done.
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J-Link>
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Serial Console
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==============
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@ -141,8 +141,8 @@
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/* GCLK */
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#define BOARD_GCLK_SET1 0x0000 /* The empty set */
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||||
#define BOARD_GCLK_SET2 0x0fff /* All GCLKs */
|
||||
#define BOARD_GCLK_SET1 0x0020 /* Pre-configure: GCLK5 needed by DPLL0 */
|
||||
#define BOARD_GCLK_SET2 0x0fdf /* Post-configure: All GCLKs except GCLK5 */
|
||||
|
||||
#define BOARD_GCLK0_ENABLE true /* Enable GCLK0 */
|
||||
#define BOARD_GCLK0_IDC false /* Don't improve duty cycle */
|
||||
@ -150,7 +150,7 @@
|
||||
#define BOARD_GCLK0_OE true /* Generate output on GCLK_IO */
|
||||
#define BOARD_GCLK0_DIVSEL 0 /* GCLK frequency is source/DIV */
|
||||
#define BOARD_GCLK0_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK0_SOURCE 7 /* Select DPLL0 output as GLCK0 source */
|
||||
#define BOARD_GCLK0_SOURCE 7 /* Select DPLL0 output as GCLK0 source */
|
||||
#define BOARD_GCLK0_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK1_ENABLE true /* Enable GCLK1 */
|
||||
@ -159,7 +159,7 @@
|
||||
#define BOARD_GCLK1_OE true /* Generate output on GCLK_IO */
|
||||
#define BOARD_GCLK1_DIVSEL 0 /* GCLK frequency is source/DIV */
|
||||
#define BOARD_GCLK1_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK1_SOURCE 6 /* Select DFLL output as GLCK1 source */
|
||||
#define BOARD_GCLK1_SOURCE 6 /* Select DFLL output as GCLK1 source */
|
||||
#define BOARD_GCLK1_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK2_ENABLE false /* Don't enable GCLK2 */
|
||||
@ -168,7 +168,7 @@
|
||||
#define BOARD_GCLK2_OE false /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK2_DIVSEL 1 /* GCLK frequency is source/(2^(N+1) */
|
||||
#define BOARD_GCLK2_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK2_SOURCE 5 /* Select XOSC32K as GLCK2 source */
|
||||
#define BOARD_GCLK2_SOURCE 5 /* Select XOSC32K as GCLK2 source */
|
||||
#define BOARD_GCLK2_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK3_ENABLE false /* Don't enable GCLK3 */
|
||||
@ -177,7 +177,7 @@
|
||||
#define BOARD_GCLK3_OE false /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK3_DIVSEL 0 /* GCLK frequency is source/DIV */
|
||||
#define BOARD_GCLK3_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK3_SOURCE 5 /* Select XOSC32K as GLCK3 source */
|
||||
#define BOARD_GCLK3_SOURCE 5 /* Select XOSC32K as GCLK3 source */
|
||||
#define BOARD_GCLK3_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK4_ENABLE true /* Enable GCLK4 */
|
||||
@ -186,7 +186,7 @@
|
||||
#define BOARD_GCLK4_OE true /* Generate output on GCLK_IO */
|
||||
#define BOARD_GCLK4_DIVSEL 0 /* GCLK frequency is source/DIV */
|
||||
#define BOARD_GCLK4_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK4_SOURCE 7 /* Select DPLL0 output as GLCK4 source */
|
||||
#define BOARD_GCLK4_SOURCE 7 /* Select DPLL0 output as GCLK4 source */
|
||||
#define BOARD_GCLK4_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK5_ENABLE true /* Enable GCLK5 */
|
||||
@ -195,7 +195,7 @@
|
||||
#define BOARD_GCLK5_OE true /* Generate output on GCLK_IO */
|
||||
#define BOARD_GCLK5_DIVSEL 0 /* GCLK frequency is source/DIV */
|
||||
#define BOARD_GCLK5_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK5_SOURCE 6 /* Select DFLL output as GLCK5 source */
|
||||
#define BOARD_GCLK5_SOURCE 6 /* Select DFLL output as GCLK5 source */
|
||||
#define BOARD_GCLK5_DIV 24 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK6_ENABLE false /* Don't enable GCLK6 */
|
||||
@ -204,7 +204,7 @@
|
||||
#define BOARD_GCLK6_OE false /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK6_DIVSEL 0 /* GCLK frequency is source/DIV */
|
||||
#define BOARD_GCLK6_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK6_SOURCE 1 /* Select XOSC1 as GLCK5 source */
|
||||
#define BOARD_GCLK6_SOURCE 1 /* Select XOSC1 as GCLK6 source */
|
||||
#define BOARD_GCLK6_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK7_ENABLE false /* Don't enable GCLK7 */
|
||||
@ -213,7 +213,7 @@
|
||||
#define BOARD_GCLK7_OE false /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK7_DIVSEL 0 /* GCLK frequency is source/DIV */
|
||||
#define BOARD_GCLK7_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK7_SOURCE 1 /* Select XOSC1 as GLCK5 source */
|
||||
#define BOARD_GCLK7_SOURCE 1 /* Select XOSC1 as GCLK7 source */
|
||||
#define BOARD_GCLK7_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK8_ENABLE false /* Don't enable GCLK8 */
|
||||
@ -222,7 +222,7 @@
|
||||
#define BOARD_GCLK8_OE false /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK8_DIVSEL 0 /* GCLK frequency is source/DIV */
|
||||
#define BOARD_GCLK8_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK8_SOURCE 1 /* Select XOSC1 as GLCK5 source */
|
||||
#define BOARD_GCLK8_SOURCE 1 /* Select XOSC1 as GCLK8 source */
|
||||
#define BOARD_GCLK8_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK9_ENABLE false /* Don't enable GCLK9 */
|
||||
@ -231,7 +231,7 @@
|
||||
#define BOARD_GCLK9_OE false /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK9_DIVSEL 0 /* GCLK frequency is source/DIV */
|
||||
#define BOARD_GCLK9_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK9_SOURCE 1 /* Select XOSC1 as GLCK5 source */
|
||||
#define BOARD_GCLK9_SOURCE 1 /* Select XOSC1 as GCLK9 source */
|
||||
#define BOARD_GCLK9_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK10_ENABLE false /* Don't enable GCLK10 */
|
||||
@ -240,7 +240,7 @@
|
||||
#define BOARD_GCLK10_OE false /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK10_DIVSEL 0 /* GCLK frequency is source/DIV */
|
||||
#define BOARD_GCLK10_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK10_SOURCE 1 /* Select XOSC1 as GLCK5 source */
|
||||
#define BOARD_GCLK10_SOURCE 1 /* Select XOSC1 as GCLK10 source */
|
||||
#define BOARD_GCLK10_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK11_ENABLE false /* Don't enable GCLK11 */
|
||||
@ -249,7 +249,7 @@
|
||||
#define BOARD_GCLK11_OE false /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK11_DIVSEL 0 /* GCLK frequency is source/DIV */
|
||||
#define BOARD_GCLK11_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK11_SOURCE 1 /* Select XOSC1 as GLCK5 source */
|
||||
#define BOARD_GCLK11_SOURCE 1 /* Select XOSC1 as GCLK11 source */
|
||||
#define BOARD_GCLK11_DIV 1 /* Division factor */
|
||||
#define BOARD_GCLK11_FREQUENCY BOARD_XOSC1_FREQUENCY
|
||||
|
||||
@ -267,6 +267,7 @@
|
||||
#define BOARD_DFLL_BPLCKC false /* No ypass coarse clock */
|
||||
#define BOARD_DFLL_WAITLOCK true /* Wait lock */
|
||||
#define BOARD_DFLL_CALIBEN false /* Don't verwrite factory calibration */
|
||||
#define BOARD_DFLL_GCLKLOCK false /* Don't lock the GCLK source */
|
||||
#define BOARD_DFLL_FCALIB 128 /* Coarse calibration value (if caliben) */
|
||||
#define BOARD_DFLL_CCALIB (31 / 4) /* Fine calibration value (if caliben) */
|
||||
#define BOARD_DFLL_FSTEP 1 /* Fine maximum step */
|
||||
@ -301,11 +302,13 @@
|
||||
#define BOARD_DPLL0_WUF false /* Wake up fast */
|
||||
#define BOARD_DPLL0_RUNSTDBY false /* Run in standby */
|
||||
#define BOARD_DPLL0_ONDEMAND false /* On demand clock activation */
|
||||
#define BOARD_DPLL0_REFLOCK false /* Do not lock reference clock section */
|
||||
#define BOARD_DPLL0_REFCLK 0 /* Reference clock selection */
|
||||
#define BOARD_DPLL0_LTIME 0 /* Lock time */
|
||||
#define BOARD_DPLL0_FILTER 0 /* Proportional integer filter selection */
|
||||
#define BOARD_DPLL0_DCOFILTER 0 /* Sigma-delta DCO filter selection */
|
||||
#define BOARD_DPLL0_GCLK 5 /* GCLK5 source (if refclock == 0) */
|
||||
#define BOARD_DPLL0_GCLK 5 /* GCLK source (if refclock == 0) */
|
||||
#define BOARD_DPLL0_GCLKLOCK 0 /* Don't lock GCLK source clock configuration */
|
||||
#define BOARD_DPLL0_LDRFRAC 0 /* Loop divider fractional part */
|
||||
#define BOARD_DPLL0_LDRINT 59 /* Loop divider ratio */
|
||||
#define BOARD_DPLL0_DIV 0 /* Clock divider */
|
||||
@ -316,11 +319,13 @@
|
||||
#define BOARD_DPLL1_WUF false /* Wake up fast */
|
||||
#define BOARD_DPLL1_RUNSTDBY false /* Run in standby */
|
||||
#define BOARD_DPLL1_ONDEMAND false /* On demand clock activation */
|
||||
#define BOARD_DPLL1_REFLOCK false /* Do not lock reference clock section */
|
||||
#define BOARD_DPLL1_REFCLK 1 /* Reference clock = XOSCK32 */
|
||||
#define BOARD_DPLL1_LTIME 0 /* Lock time */
|
||||
#define BOARD_DPLL1_FILTER 0 /* Sigma-delta DCO filter selection */
|
||||
#define BOARD_DPLL1_DCOFILTER 0 /* Sigma-delta DCO filter selection */
|
||||
#define BOARD_DPLL1_GCLK 0 /* GCLK source (if refclock == 0) */
|
||||
#define BOARD_DPLL1_GCLKLOCK 0 /* Don't lock GCLK source clock configuration */
|
||||
#define BOARD_DPLL1_LDRFRAC 13 /* Loop divider fractional part */
|
||||
#define BOARD_DPLL1_LDRINT 1463 /* Loop divider ratio */
|
||||
#define BOARD_DPLL1_DIV 0 /* Clock divider */
|
||||
@ -335,7 +340,7 @@
|
||||
|
||||
/* Peripheral clocking */
|
||||
|
||||
#define BOARD_GLCK_EIC 4 /* EIC GLCK index */
|
||||
#define BOARD_GCLK_EIC 4 /* EIC GCLK index */
|
||||
|
||||
/* FLASH wait states
|
||||
*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user