From ff906b0bef306d6a946b5850e83a9ab38e49d825 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 31 Aug 2018 09:58:53 -0600 Subject: [PATCH] arch/arm/src/samd5e5: Updates to clock configuration from initial testing. With these changes the boot up gets through clock configuration but hangs in the low-level USART configuration before completing the boot. --- arch/arm/src/samd5e5/chip/sam_gclk.h | 4 +-- arch/arm/src/samd5e5/chip/sam_oscctrl.h | 2 +- arch/arm/src/samd5e5/sam_clockconfig.c | 47 ++++++++++++++----------- arch/arm/src/samd5e5/sam_clockconfig.h | 10 +++--- arch/arm/src/samd5e5/sam_eic.c | 4 +-- arch/arm/src/samd5e5/sam_gclk.c | 6 ++-- arch/arm/src/samd5e5/sam_gclk.h | 34 ++++++++++++++++++ configs/metro-m4/README.txt | 38 ++++++++++++++------ configs/metro-m4/include/board.h | 37 ++++++++++--------- 9 files changed, 124 insertions(+), 58 deletions(-) diff --git a/arch/arm/src/samd5e5/chip/sam_gclk.h b/arch/arm/src/samd5e5/chip/sam_gclk.h index 647ab8f7c6..9dbba1d04b 100644 --- a/arch/arm/src/samd5e5/chip/sam_gclk.h +++ b/arch/arm/src/samd5e5/chip/sam_gclk.h @@ -48,7 +48,7 @@ * Pre-processor Definitions ********************************************************************************************/ -#define SAM_NGLCK 12 /* 12 Clock generators, 0-11 */ +#define SAM_NGCLK 12 /* 12 Clock generators, 0-11 */ #define SAM_NCHANNELS 48 /* 48 Clock generators, 0..47 */ /* GCLK register offsets ********************************************************************/ @@ -98,7 +98,7 @@ # define GCLK_GENCTRL_SRC_XOSC0 (0 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC 0 oscillator input */ # define GCLK_GENCTRL_SRC_XOSC1 (1 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC 1 oscillator input */ # define GCLK_GENCTRL_SRC_GCLK_IN (2 << GCLK_GENCTRL_SRC_SHIFT) /* Generator input pad */ -# define GCLK_GENCTRL_SRC_GLCK_GEN1 (3 << GCLK_GENCTRL_SRC_SHIFT) /* Generic clock generater 1 output */ +# define GCLK_GENCTRL_SRC_GCLK_GEN1 (3 << GCLK_GENCTRL_SRC_SHIFT) /* Generic clock generater 1 output */ # define GCLK_GENCTRL_SRC_OSCULP32K (4 << GCLK_GENCTRL_SRC_SHIFT) /* OSCULP32K oscillator output */ # define GCLK_GENCTRL_SRC_XOSC32K (5 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC32K oscillator output */ # define GCLK_GENCTRL_SRC_DFLL (6 << GCLK_GENCTRL_SRC_SHIFT) /* DFLL oscillator output */ diff --git a/arch/arm/src/samd5e5/chip/sam_oscctrl.h b/arch/arm/src/samd5e5/chip/sam_oscctrl.h index a6b7fa2ec6..e975dcb13b 100644 --- a/arch/arm/src/samd5e5/chip/sam_oscctrl.h +++ b/arch/arm/src/samd5e5/chip/sam_oscctrl.h @@ -277,7 +277,7 @@ #define OSCCTRL_DPLLCTRLB_REFLCK_SHIFT (5) /* Bits 5-7: Reference clock selection */ #define OSCCTRL_DPLLCTRLB_REFLCK_MASK (3 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) # define OSCCTRL_DPLLCTRLB_REFLCK(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) -# define OSCCTRL_DPLLCTRLB_REFLCK_GLCK (0 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* Dedicated GCLK clock reference */ +# define OSCCTRL_DPLLCTRLB_REFLCK_GCLK (0 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* Dedicated GCLK clock reference */ # define OSCCTRL_DPLLCTRLB_REFLCK_XOSC32 (1 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC32K clock reference (default) */ # define OSCCTRL_DPLLCTRLB_REFLCK_XOSC0 (2 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC0 clock reference */ # define OSCCTRL_DPLLCTRLB_REFLCK_XOSC1 (3 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC2 clock reference */ diff --git a/arch/arm/src/samd5e5/sam_clockconfig.c b/arch/arm/src/samd5e5/sam_clockconfig.c index 243355815e..c152026cc2 100644 --- a/arch/arm/src/samd5e5/sam_clockconfig.c +++ b/arch/arm/src/samd5e5/sam_clockconfig.c @@ -78,8 +78,8 @@ static const struct sam_clockconfig_s g_initial_clocking = { .waitstates = BOARD_FLASH_WAITSTATES, .cpudiv = BOARD_MCLK_CPUDIV, - .glckset1 = BOARD_GCLK_SET1, - .glckset2 = BOARD_GCLK_SET2, + .gclkset1 = BOARD_GCLK_SET1, + .gclkset2 = BOARD_GCLK_SET2, .cpu_frequency = BOARD_CPU_FREQUENCY, #if BOARD_HAVE_XOSC32K != 0 .xosc32k = @@ -141,6 +141,7 @@ static const struct sam_clockconfig_s g_initial_clocking = .bplckc = BOARD_DFLL_BPLCKC, .waitlock = BOARD_DFLL_WAITLOCK, .caliben = BOARD_DFLL_CALIBEN, + .gclklock = BOARD_DFLL_GCLKLOCK, .fcalib = BOARD_DFLL_FCALIB, .ccalib = BOARD_DFLL_CCALIB, .fstep = BOARD_DFLL_FSTEP, @@ -157,6 +158,7 @@ static const struct sam_clockconfig_s g_initial_clocking = .wuf = BOARD_DPLL0_WUF, .runstdby = BOARD_DPLL0_RUNSTDBY, .ondemand = BOARD_DPLL0_ONDEMAND, + .reflock = BOARD_DPLL0_REFLOCK, .refclk = BOARD_DPLL0_REFCLK, .ltime = BOARD_DPLL0_LTIME, .filter = BOARD_DPLL0_FILTER, @@ -173,6 +175,7 @@ static const struct sam_clockconfig_s g_initial_clocking = .wuf = BOARD_DPLL1_WUF, .runstdby = BOARD_DPLL1_RUNSTDBY, .ondemand = BOARD_DPLL1_ONDEMAND, + .reflock = BOARD_DPLL1_REFLOCK, .refclk = BOARD_DPLL1_REFCLK, .ltime = BOARD_DPLL1_LTIME, .filter = BOARD_DPLL1_FILTER, @@ -609,7 +612,7 @@ static inline void sam_mclk_configure(uint8_t cpudiv) * Name: sam_gclk_configure * * Description: - * Configure one GLCK + * Configure one GCLK * ****************************************************************************/ @@ -618,11 +621,11 @@ static void sam_gclk_configure(uintptr_t regaddr, { uint32_t regval; - /* Are we enabling or disabling the GLCK? */ + /* Are we enabling or disabling the GCLK? */ if (config->enable) { - /* Get the GLCK configuration */ + /* Get the GCLK configuration */ regval = GCLK_GENCTRL_SRC(config->source) | GCLK_GENCTRL_GENEN | GCLK_GENCTRL1_DIV(config->div); @@ -654,7 +657,7 @@ static void sam_gclk_configure(uintptr_t regaddr, } else { - /* Disable the GLCK */ + /* Disable the GCLK */ regval = 0; } @@ -668,7 +671,7 @@ static void sam_gclk_configure(uintptr_t regaddr, * Name: sam_gclkset_configure * * Description: - * Configure a set of GLCKs + * Configure a set of GCLKs * ****************************************************************************/ @@ -680,7 +683,7 @@ static void sam_gclkset_configure(uint16_t gclkset, /* Try every GCLK */ - for (gclk = 0; gclk < SAM_NGLCK && gclkset != 0; gclk++) + for (gclk = 0; gclk < SAM_NGCLK && gclkset != 0; gclk++) { /* Check if this one is in the set */ @@ -720,14 +723,17 @@ static void sam_dfll_configure(const struct sam_dfll_config_s *config) putreg8(0, SAM_OSCCTRL_DFLLCTRLA); /* If we are running in closed loop mode and we are in USB clock recover - * mode, then set up the input source GCLK channel. + * mode, then set up the input source GCLK channel (unless it has already + * been configured and the configuration is locked). */ - if (config->usbcrm && config->mode) + if (config->usbcrm && config->mode && + !sam_gclk_chan_locked(GCLK_CHAN_OSCCTRL_DFLL)) { - /* Configure the GCLK channel */ + /* Configure the DFLL GCLK channel to use the GCLK source. */ - sam_gclk_chan_enable(GCLK_CHAN_OSCCTRL_DFLL, config->gclk, true); + sam_gclk_chan_enable(GCLK_CHAN_OSCCTRL_DFLL, config->gclk, + (bool)config->gclklock); } /* Setup the DFLLMUL register */ @@ -905,7 +911,7 @@ static void sam_dfll_gclkready(const struct sam_dfll_config_s *config) { } - /* Set the source of GLCK0 to to the configured source. */ + /* Set the source of GCLK0 to to the configured source. */ regval32 = getreg32(SAM_GCLK_GENCTRL(0)); regval32 &= ~GCLK_GENCTRL_SRC_MASK; @@ -924,15 +930,16 @@ static void sam_dfll_gclkready(const struct sam_dfll_config_s *config) static void sam_dpll_gclkchannel(uint8_t chan, const struct sam_dpll_config_s *config) { - /* Check if we are using a dedicated GCLK as the reference clock (vs. the - * common GCLK0). + /* Check if we are using a dedicated GCLK as the reference clock. If so + * configure GCLK unless it has already been configured and configuration + * registers have been locked. */ - if (config->refclk != 0) + if (config->refclk == 0 && !sam_gclk_chan_locked(chan)) { - /* Yes.. configure the GCLK channel */ + /* Yes.. configure the GCLK channel that will be used as refclk source */ - sam_gclk_chan_enable(chan, config->gclk, true); + sam_gclk_chan_enable(chan, config->gclk, (bool)config->reflock); } } @@ -1109,7 +1116,7 @@ void sam_clock_configure(const struct sam_clockconfig_s *config) /* Pre-configure some GCLKs before configuring the DPLLs */ - sam_gclkset_configure(config->glckset1, config->gclk); + sam_gclkset_configure(config->gclkset1, config->gclk); /* Configure loops: DFLL, DPLL0, and DPLL1. */ @@ -1117,7 +1124,7 @@ void sam_clock_configure(const struct sam_clockconfig_s *config) /* Configure the renaming GCLKs before configuring the DPLLs */ - sam_gclkset_configure(config->glckset2, config->gclk); + sam_gclkset_configure(config->gclkset2, config->gclk); /* Check if the number of wait states is increasing or decreasing */ diff --git a/arch/arm/src/samd5e5/sam_clockconfig.h b/arch/arm/src/samd5e5/sam_clockconfig.h index 73ccade05f..6cd95801e8 100644 --- a/arch/arm/src/samd5e5/sam_clockconfig.h +++ b/arch/arm/src/samd5e5/sam_clockconfig.h @@ -127,6 +127,7 @@ struct sam_dfll_config_s uint8_t bplckc : 1; /* Bypass coarse clock */ uint8_t waitlock : 1; /* Wait lock */ uint8_t caliben : 1; /* Overwrite factory calibration */ + uint8_t gclklock : 1; /* Lock GCLK source clock configuration */ uint8_t fcalib; /* Fine calibration value (if caliben != 0) */ uint8_t ccalib; /* Coarse calibration value (if caliben != 0) */ uint8_t fstep; /* Fine maximum step */ @@ -145,6 +146,7 @@ struct sam_dpll_config_s uint8_t wuf : 1; /* Wake up fast */ uint8_t runstdby : 1; /* Run in standby */ uint8_t ondemand : 1; /* On demand clock activation */ + uint8_t reflock : 1; /* Lock GCLK clock reference configuration */ uint8_t refclk; /* Reference clock selection * 0 Dedicated GCLK clock reference * 1 XOSC32K clock reference @@ -190,7 +192,7 @@ struct sam_gclk_config_s uint8_t oe : 1; /* True: Output enable */ uint8_t divsel : 1; /* True: Clock source divider */ uint8_t runstdby : 1; /* Run in standby */ - uint8_t source; /* GLCK clock source: + uint8_t source; /* GCLK clock source: * 0 XOSC 0 oscillator input * 1 XOSC 1 oscillator input * 2 Generator input pad @@ -209,8 +211,8 @@ struct sam_clockconfig_s { uint8_t waitstates; /* NVM read wait states 9-15 */ uint8_t cpudiv; /* MCLK divider to get CPU frequency */ - uint16_t glckset1; /* GLCKs to initialize prior to DPLL init */ - uint16_t glckset2; /* GLCKs to initialize after to DPLL init */ + uint16_t gclkset1; /* GCLKs to initialize prior to DPLL init */ + uint16_t gclkset2; /* GCLKs to initialize after to DPLL init */ uint32_t cpu_frequency; /* Resulting CPU frequency */ #if BOARD_HAVE_XOSC32K != 0 struct sam_xosc32_config_s xosc32k; /* XOSC32 configuration */ @@ -223,7 +225,7 @@ struct sam_clockconfig_s #endif struct sam_dfll_config_s dfll; /* DFLL configuration */ struct sam_dpll_config_s dpll[2]; /* DPLL0/1 configurations */ - struct sam_gclk_config_s gclk[12]; /* GLCK configurations */ + struct sam_gclk_config_s gclk[12]; /* GCLK configurations */ }; /************************************************************************************ diff --git a/arch/arm/src/samd5e5/sam_eic.c b/arch/arm/src/samd5e5/sam_eic.c index a740f8abcf..4e13298956 100644 --- a/arch/arm/src/samd5e5/sam_eic.c +++ b/arch/arm/src/samd5e5/sam_eic.c @@ -145,10 +145,10 @@ int sam_eic_initialize(void) */ regaddr = SAM_GCLK_PCHCTRL(GCLK_CHAN_EIC); - regval = GCLK_PCHCTRL_GEN(BOARD_GLCK_EIC) | GCLK_PCHCTRL_CHEN; + regval = GCLK_PCHCTRL_GEN(BOARD_GCLK_EIC) | GCLK_PCHCTRL_CHEN; putreg32(regval, regaddr); - /* Enable the EIC, selecting clocking via the GLCK_EIC */ + /* Enable the EIC, selecting clocking via the GCLK_EIC */ putreg8(EIC_CTRLA_ENABLE | EIC_CTRLA_ENABLE, SAM_EIC_CTRLA); sam_eic_syncwait(); diff --git a/arch/arm/src/samd5e5/sam_gclk.c b/arch/arm/src/samd5e5/sam_gclk.c index d8c87c6620..eb992d7735 100644 --- a/arch/arm/src/samd5e5/sam_gclk.c +++ b/arch/arm/src/samd5e5/sam_gclk.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/samd5e5/sam_glck.c + * arch/arm/src/samd5e5/sam_gclk.c * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -61,7 +61,7 @@ * the clock domains is complete. * * Input Parameters: - * glck - GCLK clock index + * gclk - GCLK clock index * * Returned Value: * None @@ -233,7 +233,7 @@ void sam_gclk_chan_enable(uint8_t channel, uint8_t srcgen, bool wrlock) /* Configure the peripheral channel */ - regval = GCLK_PCHCTRL_GEN(srcgen); + regval = GCLK_PCHCTRL_GEN(srcgen); putreg32(regval, regaddr); /* Enable the peripheral channel, setting the writelock if so requested. */ diff --git a/arch/arm/src/samd5e5/sam_gclk.h b/arch/arm/src/samd5e5/sam_gclk.h index f3fa1dc053..3dd11a6864 100644 --- a/arch/arm/src/samd5e5/sam_gclk.h +++ b/arch/arm/src/samd5e5/sam_gclk.h @@ -45,6 +45,7 @@ #include #include +#include "up_arch.h" #include "sam_config.h" #include "chip/sam_gclk.h" @@ -141,6 +142,39 @@ void sam_gclk_chan_enable(uint8_t channel, uint8_t srcgen, bool wrlock); void sam_gclk_chan_disable(uint8_t channel); +/**************************************************************************** + * Name: sam_gclk_chan_locked + * + * Description: + * Return true if the GCLK cannot be configured because the wrtlock is set + * int the PCHCTRL register. + * + * Input Parameters: + * channel - Index of the GCLK channel to be checked + * + * Returned Value: + * True if the the wrtlock bit is set in the channel's PCHCTRL register. + * + ****************************************************************************/ + +static inline bool sam_gclk_chan_locked(uint8_t channel) +{ + uint32_t regaddr; + uint32_t regval; + + /* Get the address of the peripheral channel control register */ + + regaddr = SAM_GCLK_PCHCTRL(channel); + + /* Get content of the peripheral channel control register */ + + regval = getreg32(regaddr); + + /* Return true if the WRTLOCK bit is set in the register */ + + return (regval & GCLK_PCHCTRL_WRTLOCK) != 0; +} + #undef EXTERN #if defined(__cplusplus) } diff --git a/configs/metro-m4/README.txt b/configs/metro-m4/README.txt index b317821864..a85bc8485e 100644 --- a/configs/metro-m4/README.txt +++ b/configs/metro-m4/README.txt @@ -36,18 +36,21 @@ STATUS There is a placeholder from the SAML21, but it is currently stubbed out in the Make.defs file. Configuration options in the board.h header file are bogus and also just cloned from the SAML21. + 2018-07-29: Clock configuration logic now complete. board.h configuration options still need to be verified. Unverified SERCOM USART, SPI, I2C, Port configuration, and DMA support have been added. I still have no hardware in hand to test. + 2018-07-20: Brought in the USB driver from the SAML21. It is the same USB IP with only small differences. There a a few, small open issues still to be resolved. + 2018-08-01: Hardware in hand. Initial attempts to program the board - using a Segger J-Link connected via SWD were unsuccessful. I believe - that the FLASH is locked. See "Unlocking FLASH with J-Link Commander" - below. After unlocking the FLASH, I was able to successfully write - the NuttX image. + using a Segger J-Link connected via SWD were unsuccessful because the + Metro M4 comes with an application in FLASH and the FLASH locked. See + "Unlocking FLASH with J-Link Commander" below. After unlocking the + FLASH, I was able to successfully write the NuttX image. Unfortunately, the board seems to have become unusable after the first NuttX image was written to FLASH. I am unable to connect the JTAG @@ -56,17 +59,23 @@ STATUS to halt the CPU. This is most likely a consequence of something happening in the NuttX - boot-up sequence that interferes with JTAG operation. When I continue - debugging in the future, I will put an infinite loop, branch-on-self - at the code startup up (__start) so that I can attached the debugger - and step through the initial configuration. + boot-up sequence that interferes with JTAG operation. + + Future me: This boot-up failure was do to bad clock initialization + logic that caused infinite loops during clock configuration. Unlocking + and erasing the FLASH is innocuous, but the JTAG will apparently not + work if the clocks are not in a good state. + 2018-08-03: Added a configuration option to run out of SRAM vs FLASH. This should be a safer way to do the initial board bring-up since it does not modify the FLASH image nor does it require unlocking the FLASH pages. + 2018-08-31: I finally have a new Metro M4 and have been successfully - debugging from SRAM. Several errors in clock configuration logic - have been corrected but it still hangs in the clock configuration. + debugging from SRAM (with FLASH unlocked and erased). Several + errors in clock configuration logic have been corrected and it now + gets through clock configuration okay. It now hangs in the low-level + USART initialzation. Unlocking FLASH =============== @@ -167,6 +176,15 @@ Unlocking FLASH You will, of course, have to change the path as appropriate for your system. + 4. Erase FLASH (optional) + + J-Link>erase + Erasing device (ATSAMD51P19)... + J-Link: Flash download: Total time needed: 2.596s (Prepare: 0.031s, Compare: 0.000s, Erase: 2.553s, Program: 0.000s, Verify: 0.000s, Restore: 0.012s) + J-Link: Flash download: Total time needed: 0.066s (Prepare: 0.038s, Compare: 0.000s, Erase: 0.016s, Program: 0.000s, Verify: 0.000s, Restore: 0.010s) + Erasing done. + J-Link> + Serial Console ============== diff --git a/configs/metro-m4/include/board.h b/configs/metro-m4/include/board.h index 3905a4ca6b..a7c111e560 100644 --- a/configs/metro-m4/include/board.h +++ b/configs/metro-m4/include/board.h @@ -141,8 +141,8 @@ /* GCLK */ -#define BOARD_GCLK_SET1 0x0000 /* The empty set */ -#define BOARD_GCLK_SET2 0x0fff /* All GCLKs */ +#define BOARD_GCLK_SET1 0x0020 /* Pre-configure: GCLK5 needed by DPLL0 */ +#define BOARD_GCLK_SET2 0x0fdf /* Post-configure: All GCLKs except GCLK5 */ #define BOARD_GCLK0_ENABLE true /* Enable GCLK0 */ #define BOARD_GCLK0_IDC false /* Don't improve duty cycle */ @@ -150,7 +150,7 @@ #define BOARD_GCLK0_OE true /* Generate output on GCLK_IO */ #define BOARD_GCLK0_DIVSEL 0 /* GCLK frequency is source/DIV */ #define BOARD_GCLK0_RUNSTDBY false /* Don't run in standby */ -#define BOARD_GCLK0_SOURCE 7 /* Select DPLL0 output as GLCK0 source */ +#define BOARD_GCLK0_SOURCE 7 /* Select DPLL0 output as GCLK0 source */ #define BOARD_GCLK0_DIV 1 /* Division factor */ #define BOARD_GCLK1_ENABLE true /* Enable GCLK1 */ @@ -159,7 +159,7 @@ #define BOARD_GCLK1_OE true /* Generate output on GCLK_IO */ #define BOARD_GCLK1_DIVSEL 0 /* GCLK frequency is source/DIV */ #define BOARD_GCLK1_RUNSTDBY false /* Don't run in standby */ -#define BOARD_GCLK1_SOURCE 6 /* Select DFLL output as GLCK1 source */ +#define BOARD_GCLK1_SOURCE 6 /* Select DFLL output as GCLK1 source */ #define BOARD_GCLK1_DIV 1 /* Division factor */ #define BOARD_GCLK2_ENABLE false /* Don't enable GCLK2 */ @@ -168,7 +168,7 @@ #define BOARD_GCLK2_OE false /* No generator output of GCLK_IO */ #define BOARD_GCLK2_DIVSEL 1 /* GCLK frequency is source/(2^(N+1) */ #define BOARD_GCLK2_RUNSTDBY false /* Don't run in standby */ -#define BOARD_GCLK2_SOURCE 5 /* Select XOSC32K as GLCK2 source */ +#define BOARD_GCLK2_SOURCE 5 /* Select XOSC32K as GCLK2 source */ #define BOARD_GCLK2_DIV 1 /* Division factor */ #define BOARD_GCLK3_ENABLE false /* Don't enable GCLK3 */ @@ -177,7 +177,7 @@ #define BOARD_GCLK3_OE false /* No generator output of GCLK_IO */ #define BOARD_GCLK3_DIVSEL 0 /* GCLK frequency is source/DIV */ #define BOARD_GCLK3_RUNSTDBY false /* Don't run in standby */ -#define BOARD_GCLK3_SOURCE 5 /* Select XOSC32K as GLCK3 source */ +#define BOARD_GCLK3_SOURCE 5 /* Select XOSC32K as GCLK3 source */ #define BOARD_GCLK3_DIV 1 /* Division factor */ #define BOARD_GCLK4_ENABLE true /* Enable GCLK4 */ @@ -186,7 +186,7 @@ #define BOARD_GCLK4_OE true /* Generate output on GCLK_IO */ #define BOARD_GCLK4_DIVSEL 0 /* GCLK frequency is source/DIV */ #define BOARD_GCLK4_RUNSTDBY false /* Don't run in standby */ -#define BOARD_GCLK4_SOURCE 7 /* Select DPLL0 output as GLCK4 source */ +#define BOARD_GCLK4_SOURCE 7 /* Select DPLL0 output as GCLK4 source */ #define BOARD_GCLK4_DIV 1 /* Division factor */ #define BOARD_GCLK5_ENABLE true /* Enable GCLK5 */ @@ -195,7 +195,7 @@ #define BOARD_GCLK5_OE true /* Generate output on GCLK_IO */ #define BOARD_GCLK5_DIVSEL 0 /* GCLK frequency is source/DIV */ #define BOARD_GCLK5_RUNSTDBY false /* Don't run in standby */ -#define BOARD_GCLK5_SOURCE 6 /* Select DFLL output as GLCK5 source */ +#define BOARD_GCLK5_SOURCE 6 /* Select DFLL output as GCLK5 source */ #define BOARD_GCLK5_DIV 24 /* Division factor */ #define BOARD_GCLK6_ENABLE false /* Don't enable GCLK6 */ @@ -204,7 +204,7 @@ #define BOARD_GCLK6_OE false /* No generator output of GCLK_IO */ #define BOARD_GCLK6_DIVSEL 0 /* GCLK frequency is source/DIV */ #define BOARD_GCLK6_RUNSTDBY false /* Don't run in standby */ -#define BOARD_GCLK6_SOURCE 1 /* Select XOSC1 as GLCK5 source */ +#define BOARD_GCLK6_SOURCE 1 /* Select XOSC1 as GCLK6 source */ #define BOARD_GCLK6_DIV 1 /* Division factor */ #define BOARD_GCLK7_ENABLE false /* Don't enable GCLK7 */ @@ -213,7 +213,7 @@ #define BOARD_GCLK7_OE false /* No generator output of GCLK_IO */ #define BOARD_GCLK7_DIVSEL 0 /* GCLK frequency is source/DIV */ #define BOARD_GCLK7_RUNSTDBY false /* Don't run in standby */ -#define BOARD_GCLK7_SOURCE 1 /* Select XOSC1 as GLCK5 source */ +#define BOARD_GCLK7_SOURCE 1 /* Select XOSC1 as GCLK7 source */ #define BOARD_GCLK7_DIV 1 /* Division factor */ #define BOARD_GCLK8_ENABLE false /* Don't enable GCLK8 */ @@ -222,7 +222,7 @@ #define BOARD_GCLK8_OE false /* No generator output of GCLK_IO */ #define BOARD_GCLK8_DIVSEL 0 /* GCLK frequency is source/DIV */ #define BOARD_GCLK8_RUNSTDBY false /* Don't run in standby */ -#define BOARD_GCLK8_SOURCE 1 /* Select XOSC1 as GLCK5 source */ +#define BOARD_GCLK8_SOURCE 1 /* Select XOSC1 as GCLK8 source */ #define BOARD_GCLK8_DIV 1 /* Division factor */ #define BOARD_GCLK9_ENABLE false /* Don't enable GCLK9 */ @@ -231,7 +231,7 @@ #define BOARD_GCLK9_OE false /* No generator output of GCLK_IO */ #define BOARD_GCLK9_DIVSEL 0 /* GCLK frequency is source/DIV */ #define BOARD_GCLK9_RUNSTDBY false /* Don't run in standby */ -#define BOARD_GCLK9_SOURCE 1 /* Select XOSC1 as GLCK5 source */ +#define BOARD_GCLK9_SOURCE 1 /* Select XOSC1 as GCLK9 source */ #define BOARD_GCLK9_DIV 1 /* Division factor */ #define BOARD_GCLK10_ENABLE false /* Don't enable GCLK10 */ @@ -240,7 +240,7 @@ #define BOARD_GCLK10_OE false /* No generator output of GCLK_IO */ #define BOARD_GCLK10_DIVSEL 0 /* GCLK frequency is source/DIV */ #define BOARD_GCLK10_RUNSTDBY false /* Don't run in standby */ -#define BOARD_GCLK10_SOURCE 1 /* Select XOSC1 as GLCK5 source */ +#define BOARD_GCLK10_SOURCE 1 /* Select XOSC1 as GCLK10 source */ #define BOARD_GCLK10_DIV 1 /* Division factor */ #define BOARD_GCLK11_ENABLE false /* Don't enable GCLK11 */ @@ -249,7 +249,7 @@ #define BOARD_GCLK11_OE false /* No generator output of GCLK_IO */ #define BOARD_GCLK11_DIVSEL 0 /* GCLK frequency is source/DIV */ #define BOARD_GCLK11_RUNSTDBY false /* Don't run in standby */ -#define BOARD_GCLK11_SOURCE 1 /* Select XOSC1 as GLCK5 source */ +#define BOARD_GCLK11_SOURCE 1 /* Select XOSC1 as GCLK11 source */ #define BOARD_GCLK11_DIV 1 /* Division factor */ #define BOARD_GCLK11_FREQUENCY BOARD_XOSC1_FREQUENCY @@ -267,6 +267,7 @@ #define BOARD_DFLL_BPLCKC false /* No ypass coarse clock */ #define BOARD_DFLL_WAITLOCK true /* Wait lock */ #define BOARD_DFLL_CALIBEN false /* Don't verwrite factory calibration */ +#define BOARD_DFLL_GCLKLOCK false /* Don't lock the GCLK source */ #define BOARD_DFLL_FCALIB 128 /* Coarse calibration value (if caliben) */ #define BOARD_DFLL_CCALIB (31 / 4) /* Fine calibration value (if caliben) */ #define BOARD_DFLL_FSTEP 1 /* Fine maximum step */ @@ -301,11 +302,13 @@ #define BOARD_DPLL0_WUF false /* Wake up fast */ #define BOARD_DPLL0_RUNSTDBY false /* Run in standby */ #define BOARD_DPLL0_ONDEMAND false /* On demand clock activation */ +#define BOARD_DPLL0_REFLOCK false /* Do not lock reference clock section */ #define BOARD_DPLL0_REFCLK 0 /* Reference clock selection */ #define BOARD_DPLL0_LTIME 0 /* Lock time */ #define BOARD_DPLL0_FILTER 0 /* Proportional integer filter selection */ #define BOARD_DPLL0_DCOFILTER 0 /* Sigma-delta DCO filter selection */ -#define BOARD_DPLL0_GCLK 5 /* GCLK5 source (if refclock == 0) */ +#define BOARD_DPLL0_GCLK 5 /* GCLK source (if refclock == 0) */ +#define BOARD_DPLL0_GCLKLOCK 0 /* Don't lock GCLK source clock configuration */ #define BOARD_DPLL0_LDRFRAC 0 /* Loop divider fractional part */ #define BOARD_DPLL0_LDRINT 59 /* Loop divider ratio */ #define BOARD_DPLL0_DIV 0 /* Clock divider */ @@ -316,11 +319,13 @@ #define BOARD_DPLL1_WUF false /* Wake up fast */ #define BOARD_DPLL1_RUNSTDBY false /* Run in standby */ #define BOARD_DPLL1_ONDEMAND false /* On demand clock activation */ +#define BOARD_DPLL1_REFLOCK false /* Do not lock reference clock section */ #define BOARD_DPLL1_REFCLK 1 /* Reference clock = XOSCK32 */ #define BOARD_DPLL1_LTIME 0 /* Lock time */ #define BOARD_DPLL1_FILTER 0 /* Sigma-delta DCO filter selection */ #define BOARD_DPLL1_DCOFILTER 0 /* Sigma-delta DCO filter selection */ #define BOARD_DPLL1_GCLK 0 /* GCLK source (if refclock == 0) */ +#define BOARD_DPLL1_GCLKLOCK 0 /* Don't lock GCLK source clock configuration */ #define BOARD_DPLL1_LDRFRAC 13 /* Loop divider fractional part */ #define BOARD_DPLL1_LDRINT 1463 /* Loop divider ratio */ #define BOARD_DPLL1_DIV 0 /* Clock divider */ @@ -335,7 +340,7 @@ /* Peripheral clocking */ -#define BOARD_GLCK_EIC 4 /* EIC GLCK index */ +#define BOARD_GCLK_EIC 4 /* EIC GCLK index */ /* FLASH wait states *