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arch: x86_64: Add option to disable interrupt controller initialization

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This commit is contained in:
Yang Chung-Fan 2020-05-05 15:35:47 +09:00 committed by Brennan Ashton
parent c63c8a3841
commit ffa2027226
2 changed files with 24 additions and 1 deletions
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8
arch/x86_64/src/intel64/Kconfig
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@ -53,4 +53,12 @@ config ARCH_INTEL64_HAVE_RDRAND
---help---
Select to enable the use of RDRAND for /dev/random
config ARCH_INTEL64_DISABLE_INT_INIT
bool "Disable Initialization of 8259/APIC/IO-APIC"
default n
---help---
Select to disable all initialization related to interrupt
controllers. This is necessary if those are already
initialized, i.e. Jailhouse system.
endif

17
arch/x86_64/src/intel64/up_irq.c
View File

@ -53,7 +53,6 @@
****************************************************************************/
static void up_apic_init(void);
static void up_ioapic_init(void);
static void up_idtentry(unsigned int index, uint64_t base, uint16_t sel,
uint8_t flags, uint8_t ist);
static inline void up_idtinit(void);
@ -211,6 +210,7 @@ static void up_ist_init(void)
*
****************************************************************************/
#ifndef CONFIG_ARCH_INTEL64_DISABLE_INT_INIT
static void up_deinit_8259(void)
{
/* First do an initialization to for any pending interrupt to vanish */
@ -247,6 +247,7 @@ static void up_deinit_8259(void)
outb(X86_PIC_EOI, X86_IO_PORT_PIC1_CMD);
outb(X86_PIC_EOI, X86_IO_PORT_PIC2_CMD);
}
#endif
/****************************************************************************
* Name: up_init_apic
@ -262,16 +263,19 @@ static void up_apic_init(void)
uint32_t icrl;
uint32_t apic_base;
#ifndef CONFIG_ARCH_INTEL64_DISABLE_INT_INIT
/* Enable the APIC in X2APIC MODE */
apic_base = read_msr(MSR_IA32_APIC_BASE) & 0xfffff000;
write_msr(MSR_IA32_APIC_BASE, apic_base | MSR_IA32_APIC_EN |
MSR_IA32_APIC_X2APIC | MSR_IA32_APIC_BSP);
#endif
/* Enable the APIC and setup an spurious interrupt vector */
write_msr(MSR_X2APIC_SPIV, MSR_X2APIC_SPIV_EN | IRQ_SPURIOUS);
#ifndef CONFIG_ARCH_INTEL64_DISABLE_INT_INIT
/* Disable the LINT interrupt lines */
write_msr(MSR_X2APIC_LINT0, MSR_X2APIC_MASKED);
@ -313,6 +317,7 @@ static void up_apic_init(void)
/* Enable interrupts on the APIC (but not on the processor). */
write_msr(MSR_X2APIC_TPR, 0);
#endif
}
/****************************************************************************
@ -338,6 +343,7 @@ static int __attribute__((unused))
*
****************************************************************************/
#ifndef CONFIG_ARCH_INTEL64_DISABLE_INT_INIT
static void up_ioapic_init(void)
{
int i;
@ -357,6 +363,7 @@ static void up_ioapic_init(void)
return;
}
#endif
/****************************************************************************
* Name: up_idtentry
@ -480,17 +487,21 @@ void up_irqinitialize(void)
up_ist_init();
#ifndef CONFIG_ARCH_INTEL64_DISABLE_INT_INIT
/* Disable 8259 PIC */
up_deinit_8259();
#endif
/* Initialize the APIC */
up_apic_init();
#ifndef CONFIG_ARCH_INTEL64_DISABLE_INT_INIT
/* Initialize the IOAPIC */
up_ioapic_init();
#endif
/* Initialize the IDT */
@ -513,10 +524,12 @@ void up_irqinitialize(void)
void up_disable_irq(int irq)
{
#ifndef CONFIG_ARCH_INTEL64_DISABLE_INT_INIT
if (irq >= IRQ0)
{
up_ioapic_mask_pin(irq - IRQ0);
}
#endif
}
/****************************************************************************
@ -529,10 +542,12 @@ void up_disable_irq(int irq)
void up_enable_irq(int irq)
{
#ifndef CONFIG_ARCH_INTEL64_DISABLE_INT_INIT
if (irq >= IRQ0)
{
up_ioapic_unmask_pin(irq - IRQ0);
}
#endif
}
/****************************************************************************