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Alexey T, Bitbuck Issue 73:

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Lower part of STM32 CAN driver arch/arm/src/stm32/stm32_can.c uses all three hw tx mailboxes and clears TXFP bit in the CAN_MCR register (it means transmission order is defined by identifier and mailbox number).

This creates situation when order frames are put in upper part of CAN driver (via can_write) and order frames are sent on bus can be different (and I experience this in wild).

Since CAN driver API pretends to be "file like" I expect data to be read from fd the same order it is written. So I consider described behaviour to be a bug.

I propose either to set TXFP bit in the CAN_MCR register (FIFO transmit order) or to use only one mailbox.
This commit is contained in:
Gregory Nutt 2017-10-19 06:34:54 -06:00
parent 9b5f56ba5b
commit ffca71b9bf
1 changed files with 7 additions and 3 deletions
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10
arch/arm/src/stm32/stm32_can.c
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@ -1878,12 +1878,16 @@ static int stm32can_cellinit(FAR struct stm32_can_s *priv)
* - Automatic wake-up mode
* - No automatic retransmission
* - Receive FIFO locked mode
*
* Enable:
*
* - Transmit FIFO priority
*/
regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET);
regval &= ~(CAN_MCR_TXFP | CAN_MCR_RFLM | CAN_MCR_NART |
CAN_MCR_AWUM | CAN_MCR_ABOM | CAN_MCR_TTCM);
regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET);
regval &= ~(CAN_MCR_RFLM | CAN_MCR_NART | CAN_MCR_AWUM |
CAN_MCR_ABOM | CAN_MCR_TTCM);
regval |= CAN_MCR_TXFP;
stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
/* Configure bit timing. */