From ffca71b9bf7e91926684ca08d768cf2b817b5309 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 19 Oct 2017 06:34:54 -0600 Subject: [PATCH] Alexey T, Bitbuck Issue 73: Lower part of STM32 CAN driver arch/arm/src/stm32/stm32_can.c uses all three hw tx mailboxes and clears TXFP bit in the CAN_MCR register (it means transmission order is defined by identifier and mailbox number). This creates situation when order frames are put in upper part of CAN driver (via can_write) and order frames are sent on bus can be different (and I experience this in wild). Since CAN driver API pretends to be "file like" I expect data to be read from fd the same order it is written. So I consider described behaviour to be a bug. I propose either to set TXFP bit in the CAN_MCR register (FIFO transmit order) or to use only one mailbox. --- arch/arm/src/stm32/stm32_can.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/stm32/stm32_can.c b/arch/arm/src/stm32/stm32_can.c index 1f9a06b600..a2fc3fac1d 100644 --- a/arch/arm/src/stm32/stm32_can.c +++ b/arch/arm/src/stm32/stm32_can.c @@ -1878,12 +1878,16 @@ static int stm32can_cellinit(FAR struct stm32_can_s *priv) * - Automatic wake-up mode * - No automatic retransmission * - Receive FIFO locked mode + * + * Enable: + * * - Transmit FIFO priority */ - regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); - regval &= ~(CAN_MCR_TXFP | CAN_MCR_RFLM | CAN_MCR_NART | - CAN_MCR_AWUM | CAN_MCR_ABOM | CAN_MCR_TTCM); + regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); + regval &= ~(CAN_MCR_RFLM | CAN_MCR_NART | CAN_MCR_AWUM | + CAN_MCR_ABOM | CAN_MCR_TTCM); + regval |= CAN_MCR_TXFP; stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); /* Configure bit timing. */