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More LPC1788 updates from Rommel Marcelo

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5759 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2013-03-19 13:33:00 +00:00
parent ef7fe77616
commit ffd85ebe97
4 changed files with 26 additions and 21 deletions
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7
arch/arm/src/armv7-m/nvic.h
View File

@ -483,11 +483,12 @@
#define NVIC_SYSH_PRIORITY_PR15_SHIFT 24
#define NVIC_SYSH_PRIORITY_PR15_MASK (0xff << NVIC_SYSH_PRIORITY_PR15_SHIFT)
/* Vector Table Offset Register (VECTAB) */
/* Vector Table Offset Register (VECTAB). This mask seems to vary among
* ARMv7-M implementations. It may be be redefined in the architecture-
* specific chip.h header file.
*/
#define NVIC_VECTAB_TBLOFF_MASK (0xffffffc0)
#define NVIC_VECTAB_TBLBASE (0)
#define NVIC_VECTAB_ALIGN_MASK (0x0000003f)
/* Application Interrupt and Reset Control Register (AIRCR) */

10
arch/arm/src/armv7-m/up_ramvec_initialize.c
View File

@ -100,7 +100,7 @@ void up_ramvec_initialize(void)
/* The vector table must be aligned */
DEBUGASSERT(((uintptr)g_ram_vectors & NVIC_VECTAB_ALIGN_MASK) == 0);
DEBUGASSERT(((uintptr)g_ram_vectors & ~NVIC_VECTAB_TBLOFF_MASK) == 0);
/* Copy the ROM vector table at address zero to RAM vector table.
*
@ -116,13 +116,9 @@ void up_ramvec_initialize(void)
*dest++ = *src++;
}
/* Now configure the NVIC to use the new vector table. The TBLBASE bit
* indicates that the vectors are in RAM. NOTE: These fields appear to
* differ among various ARMv7-M implementations.
*/
/* Now configure the NVIC to use the new vector table. */
putreg32(((uint32_t)g_ram_vectors & NVIC_VECTAB_TBLOFF_MASK) | NVIC_VECTAB_TBLBASE,
NVIC_VECTAB);
putreg32((uint32_t)g_ram_vectors, NVIC_VECTAB);
}
#endif /* !CONFIG_ARCH_RAMVECTORS */

10
arch/arm/src/lpc17xx/chip.h
View File

@ -61,17 +61,15 @@
# endif
#endif
/* Vector Table Offset Register (VECTAB). Redefine some bits defined in
/* Vector Table Offset Register (VECTAB). Redefine the mask defined in
* arch/arm/src/armv7-m/nvic.h; The LPC178x/7x User manual definitions
* do not match the ARMv7M field definitions.
* do not match the ARMv7M field definitions. Any bits set above bit
* 29 would be an error and apparently the register wants 8- not 6-bit
* alignment.
*/
#undef NVIC_VECTAB_TBLOFF_MASK
#define NVIC_VECTAB_TBLOFF_MASK (0x3fffff00)
#undef NVIC_VECTAB_TBLBASE
#define NVIC_VECTAB_TBLBASE (1 << 29)
#undef NVIC_VECTAB_ALIGN_MASK
#define NVIC_VECTAB_ALIGN_MASK (0x000000ff)
/* Include the memory map file. Other chip hardware files should then include
* this file for the proper setup.

20
arch/arm/src/lpc17xx/lpc17_gpioint.c
View File

@ -261,9 +261,9 @@ static int lpc17_irq2pin(int irq)
/* Set 3: 15 interrupts p2.16-p2.30
*
* LPC17_VALID_SHIFT2H 0 - Bit 0 is the first bit in a group of 14 interrupts
* LPC17_VALID_FIRST2H irq - IRQ number associated with p2.0
* LPC17_VALID_NIRQS2H 15 - 15 interrupt bits in the group
* LPC17_VALID_SHIFT2L 0 - Bit 0 is the first bit in a group of 14 interrupts
* LPC17_VALID_FIRST2L irq - IRQ number associated with p2.0
* LPC17_VALID_NIRQS2L 15 - 15 interrupt bits in the group
*/
else if (irq >= LPC17_VALID_FIRST2H && irq < (LPC17_VALID_FIRST2H+LPC17_VALID_NIRQS2H))
@ -418,12 +418,22 @@ void lpc17_gpioirqinitialize(void)
putreg32(0, LPC17_GPIOINT2_INTENR);
putreg32(0, LPC17_GPIOINT2_INTENF);
/* Attach and enable the GPIO IRQ. Note: GPIO0 and GPIO2 interrupts share
* the same position in the NVIC with External Interrupt 3
/* Attach and enable the GPIO IRQ. */
#if defined(LPC176x)
/* For the LPC176x family, GPIO0 and GPIO2 interrupts share the same
* position in the NVIC with External Interrupt 3
*/
(void)irq_attach(LPC17_IRQ_EINT3, lpc17_gpiointerrupt);
up_enable_irq(LPC17_IRQ_EINT3);
#elif defined(LPC178x)
(void)irq_attach(LPC17_IRQ_GPIO, lpc17_gpiointerrupt);
up_enable_irq(LPC17_IRQ_GPIO);
#endif
}
/****************************************************************************