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Add interrupt enable logic

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1111 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2008-10-31 23:28:12 +00:00
parent 64fc59aabb
commit fffbb2eb8b
6 changed files with 102 additions and 15 deletions
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2
arch/arm/include/str71x/irq.h
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@ -110,6 +110,8 @@ extern "C" {
* Public Functions
************************************************************************************/
EXTERN int up_irqpriority(int irq, ubyte priority); /* Set interrupt priority (0-15) */
#undef EXTERN
#ifdef __cplusplus
}

6
arch/arm/src/str71x/str71x_decodeirq.c
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@ -91,9 +91,11 @@ void up_decodeirq(uint32 *regs)
current_regs = regs;
PANIC(OSERR_ERREXCEPTION);
#else
/* Read the IRQ number from the IVR register */
/* Read the IRQ number from the IVR register (Could probably get the same
* info from CIC register without the setup.
*/
unsigned int irq = getreq32(STR71X_EIC_IVR_OFFSET);
unsigned int irq = getreq32(STR71X_EIC_IVR);
/* Verify that the resulting IRQ number is valid */

16
arch/arm/src/str71x/str71x_eic.h
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@ -142,6 +142,22 @@
/* Register bit settings ************************************************************/
/* Interrupt control register (ICR) bit definitions */
#define STR71X_EICICR_IRQEN (0x00000001) /* Bit 0: IRQ output enable */
#define STR71X_EICICR_FIQEN (0x00000002) /* Bit 1: FIQ output enable */
/* Fast interrupt register (FIR) bit definitions */
#define STR71X_EICFIR_FIE (0x00000001) /* Bit 0: FIQ channel 1/0 enable */
#define STR71X_EICFIR_FIP (0x00000002) /* Bit 1: channel 1/0 FIQ pending */
/* Source interrrupt register definitions */
#define STR71X_EICSIR_SIPLMASK (0x0000000f) /* Bits 0-3: Source interrupt priority level */
#define STR71X_EICSIR_SIVMASK (0xffff0000) /* Bits 16-31: Source interrupt vector */
/************************************************************************************
* Public Types
************************************************************************************/

73
arch/arm/src/str71x/str71x_irq.c
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@ -72,10 +72,16 @@ uint32 *current_regs;
void up_irqinitialize(void)
{
uint32 reg32;
/* The bulk of IRQ initialization if performed in str71x_head.S, so we
* have very little to do here:
*/
/* Enable IRQs (but not FIQs -- they aren't used) */
putreg32(STR71X_EICICR_IRQEN, STR71X_EIC_ICR)
/* Currents_regs is non-NULL only while processing an interrupt */
current_regs = NULL;
@ -97,7 +103,16 @@ void up_irqinitialize(void)
void up_disable_irq(int irq)
{
# warning "To be provided"
uint32 reg32;
if ((unsigned)irq < NR_IRQS)
{
/* Mask the IRQ by clearing the associated bit in the IER register */
reg32 = getreg32(STR71X_EIC_IER);
reg32 &= ~(1 << irq);
putreg32(reg32, STR71X_EIC_IER);
}
}
/****************************************************************************
@ -110,7 +125,16 @@ void up_disable_irq(int irq)
void up_enable_irq(int irq)
{
# warning "To be provided"
uint32 reg32;
if ((unsigned)irq < NR_IRQS)
{
/* Enable the IRQ by setting the associated bit in the IER register */
reg32 = getreg32(STR71X_EIC_IER);
reg32 |= (1 << irq);
putreg32(reg32, STR71X_EIC_IER);
}
}
/****************************************************************************
@ -123,5 +147,48 @@ void up_enable_irq(int irq)
void up_maskack_irq(int irq)
{
# warning "To be provided"
uint32 reg32;
if ((unsigned)irq < NR_IRQS)
{
/* Mask the IRQ by clearing the associated bit in the IER register */
reg32 = getreg32(STR71X_EIC_IER);
reg32 &= ~(1 << irq);
putreg32(reg32, STR71X_EIC_IER);
/* Clear the interrupt by writing a one to the corresponding bit in the
* IPR register.
*/
reg32 = getreg32(STR71X_EIC_IPR);
reg32 |= (1 << irq);
putreg32(reg32, STR71X_EIC_IPR);
}
}
/****************************************************************************
* Name: up_irqpriority
*
* Description:
* set interrupt priority
*
****************************************************************************/
int up_irqpriority(int irq, ubyte priority)
{
uint32 reg32;
if ((unsigned)irq < NR_IRQS && priority < 16)
{
uint32 addr = STR71X_EIC_SIR(irq);
reg32 = getreg32(addr);
reg32 &= STR71X_EICSIR_SIPLMASK;
reg32 |= priority;
putreg32(reg32, addr);
return OK;
}
return -EINVAL;
}

12
arch/arm/src/str71x/str71x_lowputc.c
View File

@ -314,20 +314,20 @@ void up_lowsetup(void)
*/
#if HAVE_UART
reg16 = getreg16(STR71X_GPIO_PC0_OFFSET);
reg16 = getreg16(STR71X_GPIO0_PC0);
reg16 &= STR71X_GPIO0_MASK;
reg16 |= STR71X_GPIO0_PC0BITS;
putreg16(reg16, STR71X_GPIO_PC0_OFFSET);
putreg16(reg16, STR71X_GPIO0_PC0);
reg16 = getreg16(STR71X_GPIO_PC1_OFFSET);
reg16 = getreg16(STR71X_GPIO0_PC1);
reg16 &= STR71X_GPIO0_MASK;
reg16 |= STR71X_GPIO0_PC1BITS;
putreg16(reg16, STR71X_GPIO_PC1_OFFSET);
putreg16(reg16, STR71X_GPIO0_PC1);
reg16 = getreg16(STR71X_GPIO_PC2_OFFSET);
reg16 = getreg16(STR71X_GPIO0_PC2);
reg16 &= STR71X_GPIO0_MASK;
reg16 |= STR71X_GPIO0_PC2BITS;
putreg16(reg16, STR71X_GPIO_PC2_OFFSET);
putreg16(reg16, STR71X_GPIO0_PC2);
#endif
}

8
arch/arm/src/str71x/str71x_serial.c
View File

@ -529,18 +529,18 @@ static int up_setup(struct uart_dev_s *dev)
cr |= STR71X_UARTCR_STOPBIT05;
}
putreg16(cr, STR71X_UART_CR_OFFSET);
up_serialout(priv, STR71X_UART_CR_OFFSET, cr);
/* Clear FIFOs */
putreg16(0, STR71X_UART2_TXRSTR_OFFSET);
putreg16(0, SSTR71X_UART2_RXRSTR_OFFSET);
up_serialout(priv, STR71X_UART2_TXRSTR_OFFSET, 0);
up_serialout(priv, SSTR71X_UART2_RXRSTR_OFFSET, 0);
/* We will take RX interrupts on either the FIFO half full or upon
* a timeout. The timeout is based upon BAUD rate ticks
*/
putreg16(50, STR71X_UART_TOR_OFFSET);
up_serialout(priv, STR71X_UART_TOR_OFFSET, 50);
/* Set up the IER */