We need to record the parent's integer register context upon exception
entry to a separate non-volatile area. Why?
Because xcp.regs can move due to a context switch within the fork() system
call, be it either via interrupt or a synchronization point.
Fix this by adding a "sregs" area where the saved user context is placed.
The critical section within fork() is also unnecessary.
reason:
1 On different architectures, we can utilize more optimized strategies
to implement up_current_regs/up_set_current_regs.
eg. use interrupt registersor percpu registers.
code size
before
text data bss dec hex filename
262848 49985 63893 376726 5bf96 nuttx
after
text data bss dec hex filename
262844 49985 63893 376722 5bf92 nuttx
size change -4
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
-machine virt,virtualization=on,gic-version=3 \
-net none -chardev stdio,id=con,mux=on -serial chardev:con \
-mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
This applies uintreg_t in risc-v commons and fixes araised ci issues
for multiple devices. The FLAT build runs on qemu-rv64ilp32 target.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This patch changes how user service calls are executed:
Instead of using the common interrupt logic, execute the user service
call directly.
Why? When a user makes a service call request, all of the service call
parameters are already loaded into the correct registers, thus it makes
no sense to first clobber them and then reload them, which is what the
old logic does. It is much more effective to run the system call directly.
During a user system call the interrupts must be re-enabled, which the
new logic does as soon as we know the exception is a user service call
request.
This patch does NOT change the behavior of reserved system calls (like
switch_context), only the user service call request is affected.
- Save the FPU registers into the tcb so they don't get lost if the stack
frame for xcp.regs moves (as it does)
- Handle interger and FPU register save/load separately
- Integer registers are saved/loaded always, like before
- FPU registers are only saved during a context switch:
- Save ONLY if FPU is dirty
- Restore always if FPU has been used (not in FSTATE_OFF, FSTATE_INIT)
- Remove all lazy-FPU related logic from the macros, it is not needed
- Save the FPU registers into the tcb so they don't get lost if the stack
frame for xcp.regs moves (as it does)
- Handle interger and FPU register save/load separately
- Integer registers are saved/loaded always, like before
- FPU registers are only saved during a context switch:
- Save ONLY if FPU is dirty
- Restore always if FPU has been used (not in FSTATE_OFF, FSTATE_INIT)
- Remove all lazy-FPU related logic from the macros, it is not needed
If a kernel stack exists, use that whenever the user process is in
privileged mode, i.e. running an exception or in system call. Previously
the exception context was stored into the user's stack, which is not ideal.
Why?
1. Because the exception entry status (REG_INT_CTX) is needed by the
kernel, and this is now in user memory which requires that the correct
user mappings are active when it is accessed.
2. The user must currently account for the exception stack frame (which
is BIG) in its own stack allocation. Moving the exception context save
to the kernel stack offloads this responsibility from the user to the
kernel, which is IMO the correct behavior.
3. The kernel access to user memory is currently allowed without condition,
however this is not ideal either. The privileged mode status CSR allows
blocking access to user memory via the STATUS_SUM-bit, which should be
disabled by default and only enabled when access to user space is really
needed. This patch allows implementing such features.
1.Move __XSTR from include/arch.h to include/irq.h
2.Move FLOAD/FSTORE and REGLOAD/REGSTORE from include/arch.h to src/common/riscv_internal.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
The FPU register saving upon vfork entry was missing.
Also added macro that tells the actual size of an FPU reg, instead
of just having a coefficient for qfpu/no-qfpu.
IRQ_NSTACKS, ARCH_CPU_COUNT, CONFIG_SMP_NCPUS all relate to each
other. However, a bit of clean up can be done and everything can
be merged into SMP_NCPUS.
The MPFS bootloader case works also as it requires only 1 IRQ stack
for the hart that executes as bootloader.
- Add config "ARCH_USE_S_MODE" which controls whether the kernel
runs in M-mode or S-mode
- Add more MSTATUS and most of the SSTATUS register definitions
- Add more MIP flags for interrupt delegation
- Add handling of interrupts from S-mode
- Add handling of FPU from S-mode
- Add new context handling functions that are not dependent on the trap
handlers / ecall
NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
thus S-mode is not usable as is, yet.
Ken Pettit has submitted the ICLA and we can migrate the licenses
to Apache.
Sebastien Lorquet has submitted the ICLA and we can migrate the licenses
to Apache.
Gregory Nutt has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: risc-v: Remove unused typedef for irqstate_t
NOTE: irqstate_t is defined in arch/risc-v/include/types.h
* arch: risc-v: Add typedef irqstate_t for __LP64__
* arch: risc-v: Add SMP support to K210 (RV64GC) processor
* boards: maxi-bit: Update READMEs and add smp/defconfig
Author: Gregory Nutt <gnutt@nuttx.org>
Run all .c and .h modified in PR through nxstyle.
Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>
feature k210 (#16)
* arch: risc-v: Add support for __LP64__ to types.h
* arch: risc-v: Add support for RV64GC to common files
* arch: risc-v: Add support for Kendryte K210 processor (RV64GC)
* boards: risk-v: Add support for Sipeed Maix Bit with K210
* tools: Add support for Kendryte K210 processor
HiFive1 with qemu
* arch: risc-v: Add include/.gitignore
* arch: risc-v: Add src/.gitignore
* arch: risc-v: Remove uncommon function prototypes in include/irq.h
* arch: risc-v: Add missing symbols and function prototypes in src/common/up_internal.h
* arch: risc-v: Add src/common/up_modifyreg32.c
* arch: risc-v: Enable include Make.dep in src/Makefile
* arch: risc-v: Fix stack coloration in common/up_createstack.c
* arch: risc-v: Add common/up_puts.c
* arch: risc-v: Add common/up_checkstack.c
* arch: rv32im: Move all logics from up_dumpstate.c to up_assert.c
This change is same as other architectures like arm/src/armv7-m
* arch: Select ARCH_HAVE_STACKCHECK for RISC-V in Kconfig
* arch: risc-v: Add SiFive fe310 processor
NOTE: Currently only tested with qemu
* boards: hifive1-revb: Add SiFive hifive1-revb board
NOTE: Currently only tested with qemu
* tools: Add fe310 processor to configure.sh
Approved-by: Alan Carvalho de Assis <acassis@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Squashed commit of the following:
Author: Gregory Nutt <gnutt@nuttx.org>
Completes review of configs/gapuino.
arch/risc-v/include/gap8/chip.h: Replace the moved chip.h header file with a dummy chip.h header file just to keep the system happy.
Move include/gap8/chip.h to src/gap8/chip.h. Internal details should not be exposed outside of arch/ and configs/. Review all headers files in src/gap8
Review of arch/risc-v/include.
Author: hhuysqt <hyq9606@126.com>
corrected author and email
Add app initialization, add signal support, cleanup irq context and configs
fix some warnings
gapuino initial port
GAP8 initial port
