The class device only handles descriptor information specific to the class,
and shared descriptor information is passed through parameters and
handled by the composite driver.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Whevenever the bit rate is going to be set, it's necessary to first
set the master clock if the underlying device supports it. If it
fails, just return the error code.
According to the struct `mclk_rate_s`, set the default sample rate
to its lowest valid value. This prevents the underlying driver from
setting unsupported values.
Create bmi160_base.h, bmi160_base.c bmi160_uorb.c files, the bmi160_base file stores
public function interfaces, and the bmi160_uorb file stores functions related to the
uorb framework. Switch the character interface and UORB interface through the
macro CONFIG_SENSORS_BMI160_UORB.
Signed-off-by: likun17 <likun17@xiaomi.com>
A usbdev has only one serial string, so use a unique macro to control it.
For boards that enable board serial string using COMPOSITE_BOARD_SERIALSTR,
PL2303_BOARD_SERIALSTR, CDCACM_BOARD_SERIALSTR, USBADB_BOARD_SERIALSTR,
USBMSC_BOARD_SERIALSTR, and RNDIS_BOARD_SERIALSTR, they need to be replaced
with BOARD_USBDEV_SERIALSTR.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Commit 50a8ec6 broke many mmc devices. Only if the flag
priv->caps & SDIO_CAPS_4BIT_ONLY was set, it migth work.
Without the flag, the mmc clock is never set (mmcsd_widebus()
call is terminated early stopping the clock). This flag
is probably not very generic because most mmc hw support
1, 4 and 8 bit modes.
JEDEC specifies a bus width selection procedure, but it's
not implemented in this mmcsd_sdio.c driver. Thus, it's
not known whether the hw supports 1, 4 anf 8 bit modes or
a combination of them.
However, with priv->caps & SDIO_CAPS_4BIT_ONLY the driver
suddenly assigns priv->buswidth = MMCSD_SCR_BUSWIDTH_4BIT
making it the only way to have the driver working.
Fix this by relaxing the above mentioned restrictions.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This commit adds basic support for electrically isolated 8 bit expander.
The expander communicates with the MCU via SPI interface. Both single
and multiple pin read are supported.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
isx019 driver freezes by I2C access in the interrupt context.
This I2C access is intended to stop data output from FPGA.
Delete this I2C access for the following reasons.
- Data output from FPGA does not affect power consumption
- There are no problems in capture restart without data output stop
since restart is done by image data block first.
This commit adds support for galvanic isolated ISO1H812G SPI expander.
Both single pin and multiple pin writes are supported.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Documentation for PWMIOC_SETCHARACTERISTICS ioctl command mentioned
that this command will neither start nor stop the pulsed output. This
however is incorrect as PWMIOC_SETCHARACTERISTICS command leads to
pwm_start() function which starts the pulsed output.
While this might not be the correct behaviour (I would probably welcome
the option to set PWM characteristics without starting the pulsed output)
it is the way the PWM driver is coded for many architectures. Future
enhancement might be to add function pwm_setchar() for example to just
set characteristics without starting the PWM output.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
TCP receive tested with different IOB_BUFSIZE:
| | 256B vs 1534B | 512B vs 1534B | 768B vs 1534B |
| :---------: | :-----------: | :-----------: | :-----------: |
| Non-SMP | ~85% | ~93% | ~96% |
| armv8a-SMP | ~66% | ~84% | ~92% |
| rv32/64-SMP | ~52% | ~72% | ~83% |
It seems we still get performance penalty on smaller IOBs, and may be
affected more under SMP mode. It may be caused by critical sections in
IOB operations.
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
Some driver like virtio-net can offload fragmented IOBs, so an interface
to support this feature is needed.
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
Previously, the CONFIG_NET_LL_GUARDSIZE is fixed to 32 (64-Bit) or
28 (32-Bit), it's a little bit tricky.
Now add support to any value greater than minimal size.
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
In a multi-core heterogeneous architecture, tun device nodes of protocol
stack core can be accessed by other cores through ioctl
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
