Commit Graph

227 Commits

Author SHA1 Message Date
ligd
3844efb5b8 stack: update up_get_intstackbase API to support cpu id
For crash dump all the CPU intstack

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-04-09 16:59:00 -03:00
simbit18
9967989b02 Fix Kconfig style
Remove spaces from Kconfig files
Remove TABs
Add comments
2024-04-09 10:49:23 +08:00
xuxin19
2c9d46f176 cmake:enable libxx for CMake build
distinguish whether to add the CXX header file search path
according to the target Language.

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-03-15 01:28:53 +08:00
p-szafonimateusz
768c5a28a1 arch/x86_64: move common Make.defs to common
cosmetic change to simplify intel64 Make.defs

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-12 08:30:37 -03:00
p-szafonimateusz
0fe777abd4 arch/intel64: move timer frequency configuration to common files
this logic can be common for intel64 chips

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-09 11:52:29 +08:00
p-szafonimateusz
636b2309e4 arch/intel64: cosmetic changes for TSC
cosmetic changes for TSC:
- remove unused variables
- add g_ prefix to global variables

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-09 11:52:29 +08:00
p-szafonimateusz
0a24f60e1b arch/intel64: select the system clock source with choice option
this will make it easier to add other sources as system clock

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-09 11:52:29 +08:00
p-szafonimateusz
b1fd3da0f6 intel64/intel64_irq.c: support interrupts up to 255
From now all intel64 interrupts are supported.
Required step towards MSI/MSI-X

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-08 20:18:39 -03:00
p-szafonimateusz
2d3c9e00ab intel64/intel64_irq.c: check if IRQ is busy before using
check if interrupt is busy when IRQCHAIN is disabled

this allows user to catch configuration errors and fail early when the
already busy vector is reused

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-08 20:18:39 -03:00
p-szafonimateusz
53aef8e93d arch/x86_64: add SSE instruction support
at default x86_64 supports SSE, SSE2, this commit adds support for
SSE3, SSSE3, SSE41, SSE42 and SSE4A

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-08 08:51:20 +08:00
p-szafonimateusz
8fe76e1271 x86_64/x86_64_initialzie.c: remove up_calibratedelay
This function is not used anywhere.
For udelay calibration we have the calib_udelay app

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-08 08:50:35 +08:00
p-szafonimateusz
83abf9bd27 arch/x86_64: add addrenv support
this commit adds simple addrenv support for x86_64

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-08 08:50:35 +08:00
p-szafonimateusz
7d95bec148 qemu-intel64: move PCI initialization back to board logic
this partly revert 4123615621 which works OK for PCI serial and network cards
but breaks QEMU EDU due to usage of sem and usleep in IDLE thread context.
Another solution will be provided later.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-07 15:03:40 -03:00
Yanfeng Liu
a66c7c3ee1 comments/docs: fix typos in comments
This fix some typos in comments.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-06 13:31:50 +08:00
trns1997
54e9e582d5 Use C++ standard lib from toolchain
Signed-off-by: trns1997 <trns1997@gmail.com>
2024-03-06 08:42:44 +08:00
p-szafonimateusz
d4b17f963d arch/intel64: add HPET timer support as oneshot timer
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-03-03 02:24:40 +08:00
Marco Casaroli
447cc9698f use apps-or-nuttx-Make.defs for archs
This will allow apps to tweak build configuration of NuttX
2024-03-01 12:59:16 -03:00
p-szafonimateusz
4123615621 x86_64: move PCI bus initialization from qemu-intel64 to common x86_64 and initialize PCI in up_initialize()
many PCI devices must be initialized early during boot process (e.g. PCI serial port)

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-27 10:30:54 -03:00
p-szafonimateusz
cdfce8a055 arch/x86_64: add spinlock support
Add spinlock support for x86_64, needed for SMP

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-27 10:27:34 -03:00
p-szafonimateusz
b3c4f3afc3 x86_64/common/Toolchain.defs: change optimization to -Os for CONFIG_DEBUG_FULLOPT
change optimization to -Os for CONFIG_DEBUG_FULLOPT to be compatible with other architectures
and add an option to select CONFIG_DEBUG_CUSTOMOPT

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-26 18:18:20 -03:00
p-szafonimateusz
3a3341ba0e arch/intel64: enable FPU and implement up_fpucmp to pass ostest
enable FPU and implement up_fpucmp to pass ostest

With aggressive optimization enabled (-O2/-O3), ostest FPU test will fail.
This is because the compiler will generate additional vector
instructions between subsequent up_fpucmp() calls (loop vectorization
somewhere in usleep() call), which will consequently overwrite
the expected FPU context (XMM registers).

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-26 18:17:37 -03:00
p-szafonimateusz
5288e063ec newlib: fix support for x86
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-26 23:56:47 +08:00
p-szafonimateusz
b14c3e1e2e arch/intel64: add software reset support
This adds a software reset for intel64, enables the use of
the reboot command from NSH
2024-02-26 23:55:14 +08:00
p-szafonimateusz
743bbfcd7e arch/intel64/Kconfig: add chip choice option
this will be useful for auto selecting CPU features
2024-02-26 20:06:35 +08:00
p-szafonimateusz
39c7ae683f arch/x86_64/Kconfig: remove unused QEMU options
boards definition should be in /boards
2024-02-26 20:06:35 +08:00
p-szafonimateusz
5c85b8618c arch/intel64: prase multiboot2 header before revoking the lower memory
__revoke_low_memory() is called in intel64_lowsetup()

fixes b4b96a6435 (PR #11758) in which the multiboot2 header was accessed
after revoking the low memory which caused page fault.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-24 09:21:04 -08:00
p-szafonimateusz
8c4612be50 arch/intel64: add g_ prefix to global data
to follow NuttX coding standard

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-23 18:16:10 -08:00
p-szafonimateusz
8a43bf1b50 arch/intel64: clear BSS in __nxstart
BSS nulling can now be optimized by the compiler, so it is necessary
to enable SSE instructions early in __nxstart

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-23 18:16:10 -08:00
p-szafonimateusz
b4b96a6435 arch/intel64: convert __nxstart to C function and move appropriate functions there
to follow the approach in other architectures

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-23 18:16:10 -08:00
p-szafonimateusz
f76017ca8a arch/intel64: format asm files, remove unused debug macros
use tab at the beginning of lines, remove C++ comments, fix some tabs to spaces

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-23 18:16:10 -08:00
p-szafonimateusz
16e47d6c8b arch/intel64: fix stack alignment
The stack pointer must be aligned to 16 bytes, otherwise the system crash on the first unaligned data access with vector instruction.
The problem is only observable with optimization enabled, when vector instructions are generated.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-02-23 12:04:54 -03:00
p-szafonimateusz
c3d41195c7 arch/intel64/stackframe.c: fix memset size
this is a follow up to the change from 2335b69120 which missed
updating stack frame length for this memset

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-23 12:04:54 -03:00
p-szafonimateusz
9b0017659c arch/x86_64: add cmake support
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-02-23 07:45:57 +08:00
Bowen Wang
de61a8e009 intel64/Toolchain.defs: move toolchain releated option to Toolchain.defs
Follow other arch does, move common toolchain option to Toolchain.defs

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-02-18 05:34:53 -08:00
Bowen Wang
415f13372d x86_64_netinitialize: support CONFIG_NETDEV_LATEINIT for x86_64
Now x86_64 can use config CONFIG_NETDEV_LATEINIT

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-02-18 05:34:53 -08:00
raiden00pl
a12fdd8876 cosmetic changes after pci code rebase 2024-01-25 09:09:30 -08:00
raiden00pl
2e758f33ee fix various compilation errors after pci code rebase 2024-01-25 09:09:30 -08:00
Brennan Ashton
0ed4123326 x86_64: Early framebuffer console
This adds support for creating an early frame buffer and primatives for
writing to this frame buffer as a console. This does require the font
infrastructure as well as multiboot2.

Additionally this can now be used with a UEFI bootloader long as it
boots NuttX via Multiboot2.  There does seem to be a PCI interrupt
issue when running in UEFI mode.

I was able to boot my laptop using this and see PCI devices enumerate.

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>

x86_64: Add conditionals around the multiboot framebuffer
2024-01-25 09:09:30 -08:00
Yanfeng Liu
1e9434e2db arch/: remove duplicated task exit logs
Newly added logging in `sched/task_exit.c` obsoletes the existing
ones in `arch/up_exit()`, thus remove the latter to reduce duplications.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-17 09:18:17 -08:00
anjiahao
749655d785 tcbinfo:remove total_num form tcbinfo.
total_num is not required
test:

make -f tools/Makefile.host
cp tools/jlink-nuttx /opt/SEGGER/JLink_V786a/libnuttxplugin.so
JLinkGDBServer -if SWD -speed 5000 -device STM32F429ZI -NoGui 1 -rtos libnuttxplugin

can run normally

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-11-21 21:52:24 -08:00
chao an
64cf63475c arch/dumponexit: unify dump on exit to common code
remove arch implement and move to common code

Signed-off-by: chao an <anchao@xiaomi.com>
2023-11-15 08:28:25 -08:00
raiden00pl
5b87fdfb9d Documentation: remove all migrated READMEs 2023-10-29 21:03:54 -03:00
Simon Piriou
c166c98e0c arch: x86_64: Fix idle stack assignment 2023-10-12 10:08:58 +08:00
Xiang Xiao
cb11747f36 arch: add use_data to g_tcbinfo
to avoid compiler/linker remove it from the final image

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-09-29 08:00:18 +03:00
zhangyuan21
8f39ba6ae4 arch: update g_running_tasks when context switch occurred
When supporting high-priority interrupts, updating the
g_running_tasks within a high-priority interrupt may be
cause problems. The g_running_tasks should only be updated
when it is determined that a task context switch has occurred.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-08-01 09:35:18 -07:00
Xiang Xiao
46b25b3849 arch: Compute the array size by nitems
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-07-26 09:33:38 +02:00
Xiang Xiao
94f273130e arch/x86_64: Add g_tcb_info
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-07-26 09:33:38 +02:00
Xiang Xiao
427f8a1624 arch: Fix the mismath in comment
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-07-16 14:39:20 -03:00
Xiang Xiao
7990f90915 Indent the define statement by two spaces
follow the code style convention

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-21 09:52:08 -03:00
Xiang Xiao
7dc0d70092 arch: Save sigdeliver into xcp in the case of signal self delevery
to avoid the infinite recusive dispatch:
*0  myhandler (signo=27, info=0xf3e38b9c, context=0x0) at ltp/testcases/open_posix_testsuite/conformance/interfaces/sigqueue/7-1.c:39
*1  0x58f1c39e in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:167
*2  0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*3  0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049334) at signal/sig_dispatch.c:115
*4  0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049334) at signal/sig_dispatch.c:435
*5  0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*6  0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*7  0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*8  0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049304) at signal/sig_dispatch.c:115
*9  0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049304) at signal/sig_dispatch.c:435
*10 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*11 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*12 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*13 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf40492d4) at signal/sig_dispatch.c:115
*14 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf40492d4) at signal/sig_dispatch.c:435
*15 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*16 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*17 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*18 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf40492a4) at signal/sig_dispatch.c:115
*19 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf40492a4) at signal/sig_dispatch.c:435
*20 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*21 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*22 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*23 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049274) at signal/sig_dispatch.c:115
*24 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049274) at signal/sig_dispatch.c:435
*25 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*26 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*27 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*28 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049244) at signal/sig_dispatch.c:115
*29 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049244) at signal/sig_dispatch.c:435
*30 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*31 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-17 11:53:18 -06:00