- Define RV_MMU_PT_LEVELS as the arch max
- Add way to find the PPN from a PTE
- Make utility function to create a satp register value, instead of
combining this to mmu_enable
- Add function to read the current satp value
- Add function to write the satp register, also fix the fence instruction
Sv39 is the only mode supported for now. However, it should be trivial
to extend the driver to support the other modes (including Sv32) as well.
The driver is tested with mpfs only, but it should work with any riscv
implementation.
u-boot/kernel may use any uart, not just uart1, depending
on the device tree configuration. They will also reset the
corresponding uarts as well. It doesn't need to be done
here.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This drops the dependency to riscv_internal.h which ensures
less redefinition conflicts. OpenSBI declares some of the
variables again which are spread in many NuttX files.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
There is no such section. Instead, place the object mpfs_head.o at the start of
the text.
Put mpfs_head.o directly into the arch library; there is no need to define
it separately in HEAD_ASRC.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Add a new configuration for CONFIG_N_IRQ_STACKS, whcih defaults to
CONFIG_SMP_NCPUS or 1
- this allows configuring multiple IRQ stacks also in the case where SMP
support is not needed
- this is specifically needed in mpfs target, where "bootloader" build boots
only on one hart, but the startup code executes on all harts and handles SW IRQs
Also don't store/restore GP if RISCV_SAVE_GP is not defined. If the GP is not
stored in fork, it can't be restored for new tasks
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
For Linux, we rename the section so that they are not invoked.
However, it doesn't work for macOS.
Notes:
* Renaming the sections (as the Linux version does) doesn't work
because the section is looked by its flags, not by its names.
* No convenient tools available to alter the relevant bit in
the section flags.
* The constructors are invoked before the program entry point.
As in _xtensa_syscall_handler, a3 was save and reused before
_xtensa_context_save, a3 save in _xtensa_context_save will generate
error.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
1. error in A3 push stack
2. when interrupt stack enable, push a12 is xtensa_irq_dispatch
parameter 1, instead of sp. As sp is interrupt stack address set by
`setintstack`, not the interruptee stack address
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
includes following parts:
add support of sparc in arch/Kconfig
add support of sparc in boards/Kconfig
add sparc dir in arch, add sparc dir in boards
add support of sparc in libs/libc/machine
modify all the coding style problem about saprc
Some SoC like bl602 require the exception entry 8 byte align, it should
be safe for other chips so we can apply it globally.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
