Abdelatif Guettouche
4edc5fb701
xtensa: Rename up_stack_color to xtensa_stack_color since it's an
...
internal function.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-01-04 02:45:45 +08:00
Petro Karashchenko
4b190fbce1
arch/arm/samv7: correct number on interrupts
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-03 22:10:22 +08:00
Petro Karashchenko
6c2b40f98a
typos: fix typos in many files
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-03 22:10:07 +08:00
Gustavo Henrique Nihei
c04fbb0365
risc-v/esp32c3: Sort LIBC_ARCH_* configs alphabetically
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-03 10:37:04 -03:00
Gustavo Henrique Nihei
78362b0949
xtensa/esp32: Use ROM implementations of libc functions
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-03 10:37:04 -03:00
Petro Karashchenko
c7d3a674fd
drivers/sensors/as5048b: fix lower half init issue
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-03 11:38:44 +08:00
Xiang Xiao
d2309195da
boards/sim: Add vncserver config for test
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-03 11:19:32 +08:00
Petro Karashchenko
d23ad9b9b0
userspace: fix typos in comments
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-02 20:50:30 +01:00
Huang Qi
b11e90f384
arch/risc-v: Refine riscv_initialstate.c
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-02 01:21:48 +08:00
Gustavo Henrique Nihei
c1fac720ec
xtensa/esp32: Add missing param documentation for SPI Flash function
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-01 20:37:44 +08:00
Gustavo Henrique Nihei
25f2dc2077
risc-v/esp32c3: Enable the creation of encrypted Flash partitions
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-01 20:37:44 +08:00
Gustavo Henrique Nihei
9e5e60ba48
esp32s2/esp32c3: Build MCUboot bootloader with Flash Encryption support
2022-01-01 20:37:44 +08:00
Norman Rasmussen
185de258bf
Fix preprocessing directives for uart flow control
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commit 58bd873729
had a mix of
`#if defined(X)` and `#ifdef X`, but used `#if X` in its TCSETS ioctl
logic which causes compile warnings.
2021-12-31 18:51:17 +08:00
Dong Heng
c56c58020a
risc-v/esp32c3: SPI flash MTD device uses all flash space
2021-12-31 11:40:23 +08:00
Gustavo Henrique Nihei
f130d8b91e
xtensa/esp32s2: Remove unavailable support for ROM Basic Console
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This feature is only available for ESP32 chips.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-31 00:56:08 +08:00
Gustavo Henrique Nihei
74c02fbadb
risc-v/esp32c3: Remove unavailable support for ROM Basic Console
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This feature is only available on ESP32 chips.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-31 00:56:08 +08:00
Huang Qi
33df35f003
arch/risc-v: Correct epc adjustment with C ISA
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-30 22:54:17 +09:00
chao.an
736add0fe8
arch/backtrace: correct the skip counter
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-30 16:57:40 +08:00
Gustavo Henrique Nihei
80da9abd6a
xtensa/esp32: Move assertions after logging to improve debugging
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-30 12:35:41 +08:00
Gustavo Henrique Nihei
b6addaa4c7
xtensa/esp32: Enable the creation of encrypted Flash partitions
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-30 12:35:41 +08:00
Gustavo Henrique Nihei
340e0c8a8f
xtensa/esp32: Build MCUboot bootloader with Flash Encryption support
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-30 12:35:41 +08:00
Jukka Laitinen
3beecbe905
risc-v/mpfs: Add MSSIO GPIO pinmap configuration
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Add a pinmap header for mpfs to be able to configure MSSIO GPIOs
This also adds Kconfigs for some different chip/package types of the PolarFire SOC
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-12-30 11:49:00 +08:00
Huang Qi
2de22980e5
arch/risc-v: Refine syscall interface
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-30 11:47:42 +08:00
Norman Rasmussen
091322ba4a
Add backtrace to risc-v common sources
2021-12-30 01:30:08 +08:00
Xiang Xiao
b92c90ee81
arch/arm: Fix rebase error in arm_backtrace_thumb.c
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 20:42:05 +08:00
Huang Qi
c15195b126
arch/risc-v: Refine riscv_testset.S
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-29 06:06:01 -06:00
Xiang Xiao
228442ee23
arch/renesas: Undefine macro B0 to avoid the confliction
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 08:11:08 -03:00
Huang Qi
901361be48
arch/risc-v: Move more files to common
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-29 01:19:30 -06:00
Huang Qi
22ae2e0121
arch/risc-v: Refine riscv_fpu.S
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-29 01:19:30 -06:00
ChenWen
6ce335fa84
xtensa/esp32: Fix some Wi-Fi issues
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1. Fix the issue that Wi-Fi can't connect to some special routers occasionally.
2. Update Wi-Fi driver code to fix issue of failure to send pkt.
3. Replace software random with hardware random
2021-12-28 23:48:25 -06:00
chao.an
7ed0b97414
make/allsyms: skip the unnecessary link operation
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For incremental compilation, skip the stage 1 dummy link
operation if nuttx elf has been generated
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-28 23:47:10 -06:00
Xiang Xiao
186ac17f1f
arch: Select ARCH_HAVE_BACKTRACE in Kconfig for supported arch
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 13:34:02 +08:00
Xiang Xiao
dd942f0b04
sched/backtrace: Dump the complete stack regardless the depth
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 12:09:54 +08:00
Xiang Xiao
f302e8fd40
arch/sim: Implement up_backtrace
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 11:03:08 +08:00
Xiang Xiao
f061766801
video/fb: Fix typo error in include/nuttx/video/fb.h
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-28 17:21:18 -03:00
Huang Qi
e75321e61c
arch/risc-v: Move riscv_blocktask.c to common
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 11:32:15 -06:00
Norman Rasmussen
934a79736a
Use userspace chosen channel numbers when starting bl602 pwm
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commit 2889315c20
added support for pwm
but didn't read the channel numbers provided by user-space. They should
be, otherwise it's not possible to start a sub-set of channels that are
not the first "n" channels.
2021-12-28 06:27:51 -06:00
chao.an
cf2dfa8985
arch/arm/assert: move the arm_assert to common code
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-28 05:09:30 -06:00
Huang Qi
d71cfc178a
arch/risc-v: Remove unneeded kconfigs
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CONFIG_RV32IM_HW_MULDIV can be safely removed since this behavior is
controlled by M extension.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 05:02:42 -06:00
chao.an
579738c8fa
arch/arm: move the backtrace implement to common code
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-28 03:02:01 -06:00
Norman Rasmussen
1e2f067181
pwm: add option to break the loops when using multiple PWM channels
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commit 7354ab187e
added an option to break
the loops when using multiple PWM channels to arm pwm drivers. This adds
the same support to the risc-v pwm drivers.
2021-12-28 03:01:27 -06:00
Huang Qi
c2e8c92b25
arch/risc-v: Refine Toolchain.defs
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 00:30:10 -06:00
chao.an
a42aa8415d
compile/flags: add FRAME_POINTER into Toolchain.defs
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-27 22:31:27 -06:00
chao.an
8eb999ff03
arch/arm: select ARM_THUMB by default for Cortex-M
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-27 22:30:53 -06:00
Petro Karashchenko
3ccb657dc2
nuttx: remove space befone newline in logs
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-27 21:01:19 -06:00
Huang Qi
0751bcd4ca
arch/sim: Support vncserver as display device
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-24 11:59:43 -06:00
Alan C. Assis
01e4e249cc
Add WiFi/BLE Coexistence support
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Co-authored-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-23 20:42:23 -06:00
chao.an
6069433d2d
arch/arm/cortex-a/r: dump all registers with alias
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-23 06:54:32 -06:00
Eero Nurkkala
3394dca826
risc-v/opensbi: Make.defs: use a wildcard for file listing
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The source directory contents of the OpenSBI directory lib/sbi may be
listed with a one-line wildcard. This makes the Make.defs file look
simpler. The rest of the files need to be picked one at a time.
Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-23 02:42:09 -06:00
Eero Nurkkala
b128ce334f
mpfs: introduce OpenSBI
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OpenSBI may be compiled as an external library. OpenSBI commit d249d65
(Dec. 11, 2021) needs to be reverted as it causes memcpy / memcmp to
end up in the wrong section. That issue has yet no known workaround.
OpenSBI may be lauched from the hart0 (e51). It will start the U-Boot
and eventually the Linux kernel on harts 1-4.
OpenSBI, once initialized properly, will trap and handle illegal
instructions (for example, CSR time) and unaligned address accesses
among other things.
Due to size size limitations for the mpfs eNVM area where the NuttX
is located, we actually set up the OpenSBI on its own section which
is in the bottom of the DDR memory. Special care must be taken so that
the kernel doesn't override the OpenSBI. For example, the Linux device
tree may reserve some space from the beginning:
opensbi_reserved: opensbi@80000000 {
reg = <0x80000000 0x200000>;
label = "opensbi-reserved";
};
The resulting nuttx.bin file is very large, but objcopy is used to
create the final binary images for the regions (eNVM and DDR) using
the nuttx elf file.
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-22 20:48:12 -06:00
Eero Nurkkala
491ae6cc53
mpfs: cache: assign ways to L2 zero device
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Assign ways to L2 zerodevice. L2 zero device is used for
the scratchpad functionality. The area may be used for the
harts communicating to each other.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-22 20:48:12 -06:00
David Sidrane
74e692b3c1
stm32f7:sdmmc invalidate before DMA to avoid eviction overwrite
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For FAT the same buffer is used for read and writes, there
is a possibility a cache line is dirty. But the fs is
not dirty and will not write the sector to disk. This can
be seen https://github.com/PX4/NuttX/pull/175
When the system is busy that cache line can be evicted after the
RX DMA has completed and overwrite the data in memory. The solution
is to invalidate before the DMA to prevent an evection causing an
overwite, and after the DMA it to insure coherency.
2021-12-22 20:44:04 -06:00
chao.an
fe2830ec94
xtensa: enhance the task dump
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add irq stack information
add cpu loading
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-22 11:46:02 -03:00
chao.an
362fe2c6f8
arch/risc-v: enhance the task dump
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add irq stack information
add cpu loading
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-22 11:46:02 -03:00
chao.an
a0b61bbf6f
arm/cortex-a/r: enhance the task dump
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add irq stack information
add cpu loading
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-22 11:46:02 -03:00
Abdelatif Guettouche
4f0dd95fe1
arch/Kconfig: Add HAVE_SYSCALL_HOOKS configs to Xtensa arch.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-22 06:26:36 -06:00
Xiang Xiao
b03886415f
sim/netdev: Update IFF_RUNNING flag by netdev_carrier_on and netdev_carrier_off
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-22 07:15:00 -03:00
chao.an
2737701996
cortex-m/hardfault: add secure-fault handler
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-21 07:08:13 -06:00
ChenWen
6d165506d5
risc-v/esp32c3: Initialize rtc and peripheral parameters by default when chip starts
2021-12-21 10:03:58 -03:00
Gustavo Henrique Nihei
c471f0fe96
risc-v/esp32c3: Remove deprecated note about Flash Detect feature
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Flash Detect option is already available on esptool.py installed via pip
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei
1c8e84b341
risc-v/esp32c3: Add Secure Boot support on top of MCUboot
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei
f542ab4564
xtensa/esp32s2: Add Secure Boot support on top of MCUboot
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei
d22a2aa7a0
xtensa/esp32: Refactor makefiles for compliance to Function Call Syntax
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According to Make documentation:
- "Commas and unmatched parentheses or braces cannot appear in the text
of an argument as written";
- "Leading spaces cannot appear in the text of the first argument as
written".
Although in the current state it was not resulting in parsing issues, it
is better to fix it.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei
6c3223289f
xtensa/esp32: Add Secure Boot support on top of MCUboot
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This adds the capabitlity of building signed images on NuttX.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-21 07:02:40 -06:00
Juha Niskanen
54b652235c
Update arch/Kconfig
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Co-authored-by: Gustavo Henrique Nihei <38959758+gustavonihei@users.noreply.github.com>
2021-12-21 03:26:16 -06:00
Juha Niskanen
422ceec99b
Fix typos in comments and Kconfig files
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Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2021-12-21 03:26:16 -06:00
chao.an
287348475c
sim/usrsock: increase the sim usrsock buffer size
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1. Increase the sim usrsock buffer size:
arch/sim/src/sim/up_usrsock.c
2. Fix build break
arch/sim/src/sim/up_usrsock_host.c
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-21 00:53:31 -06:00
Simon Filgis
6cc48ff6ff
arch/arm/samv7: initial support for LIN bus communication
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-20 18:23:05 -03:00
Petro Karashchenko
3e76c3266e
assert: unify stack and register dump across platforms
...
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-20 00:02:12 -03:00
Petro Karashchenko
67d8a82393
Kconfig: fix non-string default values uniformity
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-20 00:10:57 +01:00
David Sidrane
e269b5fa28
Revert "stm32h7 sdmmc: set SDMMC_CK pin to high speed (50 MHz) mode. When it was in slow speed mode (by default), the output SDMMC_CK clock rise and fall times were about 13 ns each, that were very slow and prevented some SDIO devices from working."
...
This reverts commit 0aecfe8691
.
2021-12-19 01:40:35 -06:00
chao.an
c1c1882783
sim/usrsock: Reuse all addresses to avoid bind fail
...
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-18 13:15:46 -06:00
raiden00pl
87a8b1bed9
nrf52/Kconfig: NRF52_SDC_LE_CODED_PHY not available for nrf52832
2021-12-18 12:27:59 -06:00
raiden00pl
f3fdd5a019
arch/arm/src/nrf52/Kconfig: select IRQPRIO for SoftDevice
2021-12-18 09:13:36 -06:00
raiden00pl
a6c64795f4
arch/arm/src/nrf52/nrf52_sdc.c: raise error if BT device not selected
2021-12-18 09:13:36 -06:00
raiden00pl
cf2dae8d79
arch/arm/src/nrf52/nrf52_sdc.c: nxstyle fixes
2021-12-17 12:35:17 -06:00
raiden00pl
af143c96fc
arch/arm/src/nrf52/nrf52_sdc.c: public device address and static device address support
2021-12-17 12:35:17 -06:00
raiden00pl
c7f6ac63b0
arch/arm/src/nrf52/nrf52_sdc.c: add option to register UART H4 device
2021-12-17 12:35:17 -06:00
raiden00pl
23ef3ea64c
arch/arm/src/nrf52/nrf52_sdc.c: remove nedless new lines
2021-12-17 12:35:17 -06:00
raiden00pl
26951f5018
arch/arm/src/nrf52/nrf52_sdc.c: print HCI opcode as hex
2021-12-17 12:35:17 -06:00
raiden00pl
07c9204fd6
arch/arm/src/nrf52/nrf52_sdc.c: fix status byte offset
2021-12-17 12:35:17 -06:00
raiden00pl
ab66800e13
arch/arm/src/nrf52/Kconfig: fix typos
2021-12-17 12:35:17 -06:00
raiden00pl
ba6e8696b2
arch/arm/src/nrf52/hardware/nrf52_ficr.h: add device address types
2021-12-17 12:35:17 -06:00
Jiuzhu Dong
5a22d33475
up_putc: do up_putc when enable CONFIG_ARCH_LOWPUTC
...
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-12-17 11:43:08 -06:00
raiden00pl
07d295b8db
add 5-Clause Nordic License barrier for Nordic SoftDevice Controller
2021-12-17 11:22:39 -06:00
xiewenxiang
b1d051b651
riscv/esp32c3: Initialize the BLE Mac
2021-12-16 22:31:02 -03:00
Gerson Fernando Budke
2dd5578d50
arch/arm/src/samv7/Kconfig: Define mem sizes
...
Current samv7 platform does not define SoC memories sizes. This define
both internal flash and sram memories sizes and update all defconfig
files.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2021-12-16 06:56:42 -03:00
Alexander Lunev
0aecfe8691
stm32h7 sdmmc: set SDMMC_CK pin to high speed (50 MHz) mode.
...
When it was in slow speed mode (by default), the output SDMMC_CK clock rise and
fall times were about 13 ns each, that were very slow and
prevented some SDIO devices from working.
2021-12-16 01:28:05 -06:00
chao.an
b11833cbba
arch/assert: flush the syslog before stack dump
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flush the syslog before stack dump to avoid buffer overwrite
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-15 12:00:35 -06:00
chao.an
56ef1419dd
arch/xtensa: set the current reg before print syslog
...
ensure the semantics of the up_interrupt_context() works as expected
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-14 21:40:03 -06:00
chao.an
2fe06ac083
arch: xtensa: save current SP before overwrting
...
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-14 21:40:03 -06:00
chao.an
93b133fe66
arch/xtensa: correct the interrupt stack on irq handler
...
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-14 21:40:03 -06:00
Petro Karashchenko
51a2db6ffc
Kconfig: improve uniformity
...
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-14 07:32:48 -06:00
Jiuzhu Dong
6b5a7a73ba
sim: add CONFIG_SIM_STACKSIZE_ADJUSTMENT to reduce variability
...
between sim and other different platform stack size setting
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-12-13 21:15:30 -06:00
Petro Karashchenko
af614ac77d
tls: restore C89 compatibility for TLS
...
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-13 21:14:53 -06:00
chao.an
c2fd66bfab
arch/arm/risc-v/xtensa: add support of all symbols for debugging
...
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-13 08:31:13 -06:00
Abdelatif Guettouche
d31a0d8aca
arch/xtensa/esp32: Show CPU activity on IDLE task and on interrupts.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-13 08:30:58 -06:00
Abdelatif Guettouche
6262f7e99a
esp32_idle.c: Change private function's name to start with esp32_
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instead of up_.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-13 08:30:58 -06:00
chao.an
89e2f00dad
arch/assert: fix the stack dump overflow
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[ EMERG] kasan_report: kasan detected a read access error, address at 0x3c24fca8, size is 4
[ EMERG] up_assert: Assertion failed at file:kasan/kasan.c line: 104 task: init
[ EMERG] backtrace|10: 0x2c334666 0x2c35f0d6 0x2c359ef6 0x2c35f830 0x2c360ed4 0x2c3615c0 0x2c324e0c 0x2c30a168
[ EMERG] up_registerdump: R0: ffffffff R1: 00000004 R2: ffffffff R3: ffffffff
[ EMERG] up_registerdump: R4: 3c20d4f0 R5: 2c35acd5 R6: 00000000 FP: 3c24fae8
[ EMERG] up_registerdump: R8: 3c20d504 SB: ffffffff SL: 2c413e7c R11: 2c411eb8
[ EMERG] up_registerdump: IP: 00000002 SP: 3c24fae8 LR: 00000003 PC: 2c35f0d6
[ EMERG] up_registerdump: xPSR: 61010000 BASEPRI: 000000e0 CONTROL: 00000004
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-13 01:43:18 -06:00
chao.an
0b7b8d274f
arm/cortex-m: enhance the crash dump
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1. add irq stack information to list
2. add cpu loading into list
before:
Idle Task: PID=0 PRI=0 Stack Used=512 of 3048
hpwork: PID=1 PRI=224 Stack Used=304 of 2016
lpwork: PID=2 PRI=100 Stack Used=304 of 2016
rptun: PID=4 PRI=224 Stack Used=856 of 2008
after:
[ EMERG] [ap] up_showtasks: PID PRI USED STACK FILLED CPU COMMAND
[ EMERG] [ap] up_showtasks: ---- ---- 928 2048 45.3% ---- irq
[ EMERG] [ap] up_dump_task: 0 0 512 3048 16.7% 99.4% Idle Task
[ EMERG] [ap] up_dump_task: 1 224 304 2016 15.0% 0.0% hpwork
[ EMERG] [ap] up_dump_task: 2 100 304 2016 15.0% 0.0% lpwork
[ EMERG] [ap] up_dump_task: 4 224 856 2008 42.6% 0.0% rptun
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-12 21:40:29 -06:00
lupyuen
2a87b37a69
riscv/bl602: Swap SPI MISO and MOSI
2021-12-12 20:40:49 -06:00
Huang Qi
8ce3337e85
arch/risc-v: Implement TLS support
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-12 10:19:00 -06:00
Matheus Castello
294694bb2f
arch: arm: select LIBC_ARCH_ATOMIC when config ARCH_CHIP_RP2040
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Use the common atomic operations when needed.
Signed-off-by: Matheus Castello <matheus@castello.eng.br>
2021-12-11 11:32:17 -06:00
Juha Niskanen
a35d205f3b
arch/arm/src/stm32l4/stm32l4_pwm.c: fix printf format
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Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2021-12-10 12:30:26 -06:00
Daniel Agar
efc949bceb
arch/arm/src/stm32/Kconfig STM32_STM32F412 add SPI2 & SPI3
2021-12-09 21:30:41 -06:00
chao.an
3d75c25737
cortex-m/hardfault: enhance the dump information of mem/hard-fault
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 11:42:21 -06:00
chao.an
66e604b40e
cortex-m/hardfault: add usage-fault handler
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 11:42:21 -06:00
chao.an
2f449245cc
cortex-m/hardfault: add bus-fault handler
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 11:42:21 -06:00
chao.an
99fa58c871
arm/cortex-m23: armv8-m baseline do not support mem-fault
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 05:36:00 -06:00
chao.an
3e812dd88c
cortex-m/fault: add CFSR(Configurable Fault Status Register) Definitions
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 04:30:06 -06:00
Xiang Xiao
6357523892
arch: Add _wchar_t typedef like other basic types
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-09 16:57:23 +09:00
chao.an
9b502dca05
arm/backtrace: disable the sanitize address check
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 01:05:46 -06:00
chao.an
7a61588b00
cortex-m/backtrace: remove the push process to simplify backtrace
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 01:05:46 -06:00
chao.an
437c81f8d0
cortex-m/assert: dump all registers with alias
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 00:16:04 -06:00
Michal Lenc
ae57492189
samv7: enable MCAN driver support for both rev A and rev B
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This commit enables the MCAN driver to function with both rev A and rev B
version of the chip. The version of the chip is selected automtically from
SAM_CHIPID_CIDR register so there is no need to predefined it in the
configuration.
The functonality was tested on rev B version of the chip. The rev A was
not tested since I do not have the functional board but the code remains
the same as in the previous NuttX version so it should not cause any
additional troubles.
The code is co-authored by Miloš Pokorný who wrote the initial transition
to rev B of the chip.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Co-authored-by: Miloš Pokorný <milos.pokorny@seznam.cz>
2021-12-07 23:36:11 -06:00
Huang Qi
58e0781e2e
arch/arm: Implement TLS support
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Signed-off-by: Huang Qi <no1wudi@qq.com>
2021-12-07 23:31:41 -06:00
Masayuki Ishikawa
bec9058b4c
arch: lc823450: Replace the critical section with spinlock in lc823450_serial.c
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Summary:
- This commit replaces the critical section with spinlock
- The logic is the same as cxd56_serial.c
Impact:
- None
Testing:
- Tested with lc823450-xgevk:bt
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-12-07 23:28:54 -06:00
Huang Qi
63ab2f4308
arch/risc-v: Introduce basic support for qemu rv32
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-07 23:28:33 -06:00
raiden00pl
54e3b148e9
arch/sim/src/sim/up_assert.c: fix implicit declaration warning
2021-12-07 07:51:44 -06:00
anjiahao
9d6c92f0fa
arch:move debug.h form headfile to c file
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Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2021-12-07 04:01:27 -08:00
fenghang
c39ef4420e
1.phyplus update files to accord with the requirement of chcekpatch.sh
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2.fix some files to fix compile warning
3.remove blueteeth header files, which are not used in nuttx core.
4.fix configs and add lost files
5.update defconfig, remove useless items
6.fix compile warning for nuttx phyplus
7.delete useless: ble, h4, zblue defconfig files form phyplus configure folder
8.fix file format check error on phyplus source code
9.fix phyplus kconfig param error
10.update configure file for nuttx
2021-12-07 01:37:29 -06:00
fenghang
073c9880a3
phyplus first submit
2021-12-07 01:37:29 -06:00
chao.an
437a30d117
arch/tcbinfo: fix build break if task name disabled
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-06 00:47:58 -06:00
Dong Heng
698f1f76ff
risc-v/esp32c3: Refactor SPI Flash to support umask interrupt when R/W/E SPI Flash
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This can fix BLE assert when erase SPI Flash.
2021-12-06 13:13:11 +09:00
Xiang Xiao
a0990ee416
arch: Remove the duplicated up_tls_info implementation
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Define up_tls_info in arch/arch.h directly if the general one isn't suitable
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-05 20:59:53 -06:00
Xiang Xiao
19e5ee6ce0
arch: Remove FILE dump code from _up_dumponexit
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since the kernel build can't access the userspace memory
inside other process directly
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-06 11:23:58 +09:00
Abdelatif Guettouche
50d217a9e8
esp32_cpustart.c: Improve comments around the usage of the inter-cpu
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startup handshake.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-02 11:21:49 -06:00
Abdelatif Guettouche
b34951e3a0
esp32_cpustart.c: Remove the CONFIG_SMP condition on some part of code
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because the whole file is only built if CONFIG_SMP is enabled.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-02 11:21:49 -06:00
Xiang Xiao
b65c7c26cf
arch: Dump task name through tcb_s::name instead of argv[0]
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since argv is defined in task_tcb_s not tcb_s
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-01 16:04:15 +01:00
Gerson Fernando Budke
c3307fce6b
arch/arm/Kconfig: Add ARCH_HAVE_PROGMEM config
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The Atmel samv7 implements progmem functionality. However, there is
missing ARCH_HAVE_PROGMEM Kconfig symbol. This add missing symbol.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2021-11-29 21:31:08 -06:00
Petro Karashchenko
31809724e1
boards/same70-xplained: disable systick before loading MCUboot application
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-28 20:33:53 -06:00
Petro Karashchenko
fae27cc945
arch/samv7: fix unaligned address write for progmem interface
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-28 11:04:28 -06:00
Michal Lenc
ce53ea5da6
arch/arm/src/samv7: add DMA and TC trigger support to AFEC driver
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This commit adds DMA and TC support to SAMV7 AFEC driver. The AFEC (ADC)
can now be triggered by Timer/counter at chosen frewuency and samples can
be transfered via DMA with configurable number of samples. Timer/counter
trigger is now set as a default option with the possibility to change it
to software generated trigger.
DMA is inspired by SAMA5 driver and also uses ping pong buffers.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-11-27 06:17:45 -06:00
Michal Lenc
6f2e23ad0c
arch/arm/src/samv7/sam_tc.c: fix compile warnings and errors
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Just a minor change fixing some compile warnings and errros, does not have
any impact on functionality.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-11-27 06:17:45 -06:00
Abdelatif Guettouche
251b8a3445
esp32xx_rtc: Include "clock/clock.h" to have a declaration of
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g_basetime.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-26 15:23:47 -03:00
Abdelatif Guettouche
af11cf6cd1
esp32xx_rtc.c: Fix a duplicated assignment.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-26 15:23:47 -03:00
Dong Heng
66023da10c
risc-v/esp32c3: Refactor ADC calibration
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Use calibration parameters from efuse rather than self-calibration.
2021-11-26 15:23:24 -03:00
Petro Karashchenko
0d9425676d
arch/arm/src/samv7: add flash progmem erasestate ioctl support
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-26 14:55:34 -03:00
Petro Karashchenko
134b2e6ec9
arch/arm/include/samv7: fix typo in samv7 irq header files
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-26 14:55:34 -03:00
Petro Karashchenko
dd647d200e
arch/samv7/sam_progmem: fix page size flash writing
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-26 08:47:08 -06:00
Xiang Xiao
e30a5f3790
arch/sim: Add new option to enable arch specific hostfs
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we have many different hostfs implementation now, so it's better
to select the implementation explicitly, just like what we have
done for arm(FS_HOSTFS vs. ARM_SEMIHOSTING_HOSTFS).
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-25 14:42:23 +01:00
zhuyanlin
1b3005accf
arch:cache_invalidate: fix unalign cacheline invalidate
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Only invalidate may corrupt data in unalign start and end.
Use writeback and invalidate instead.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-24 22:48:13 -06:00
zhuyanlin
4db5016d83
arch:hostfs: add cache coherence config for semihosting option
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N/A
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-24 22:48:13 -06:00
David Sidrane
ad7e36d83f
stm32f7:sdmmc defer invalidate until after DMA completion
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The FAT was not coherent. Resulting in a write failed
with errno:28 No space left on device.
It is unclear how the memory is acesses prior to the DMA
completion. But this restructuring ensures the data
is coherent.
This issue was not detected on the stm32h7
2021-11-24 20:38:23 -06:00
Jani Paalijarvi
4dfd3c9160
arch/riscv: Add ARCH_HAVE_SPI_CS_CONTROL for mpfs
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Make it possible to override SPI CS function in board logic
Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-11-24 06:50:32 -06:00
Lee Lup Yuen
6e68d55f8a
Fix GPIO output
2021-11-24 06:48:50 -06:00
chao.an
7cbb8da692
binfmt/elf: add bare metal coredump support
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-11-23 20:48:00 -06:00
chao.an
0f76ff42eb
arch/sim: add arch elf define
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-11-23 20:34:56 +09:00
chao.an
4c76c356ef
arch/arm: add more arch elf define
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-11-23 20:34:56 +09:00
Abdelatif Guettouche
65db787eff
esp32_irq.c: Fix retrieving IRQ number and peripheral ID when it comes
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to GPIOs in SMP mode.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-22 11:41:10 -06:00