15303 Commits

Author SHA1 Message Date
Xiang Xiao
7990f90915 Indent the define statement by two spaces
follow the code style convention

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-21 09:52:08 -03:00
raiden00pl
1de1b8adb7 arch/nrf53: add SPI support 2023-05-20 10:18:49 -07:00
David Sidrane
b4a6c63d47 s32k3xx:edma {s|d}last needs to be total xfer size 2023-05-20 18:32:01 +08:00
David Sidrane
280bf95d8a s32k1xx:edma {s|d}last needs to be total xfer size 2023-05-20 18:32:01 +08:00
David Sidrane
cd92cf4496 kinetis:edma {s|d}last needs to be total xfer size 2023-05-20 18:32:01 +08:00
raiden00pl
3493ea399f arch/nrf53: add I2C support 2023-05-19 21:36:49 -07:00
raiden00pl
22d4a492e4 arch/nrf53: UART0-3, SPI0-3 and TWI0-3 instances share the same interrupt vectors 2023-05-19 21:36:49 -07:00
simbit18
8a124f1a6f arch/arm/src: Fix Kconfig style
Remove spaces from Kconfig files
2023-05-19 21:18:51 +08:00
simbit18
5d0bbf20f7 arch/arm/src/imxrt/Kconfig: Fix Kconfig style
Remove spaces from Kconfig files
2023-05-19 21:18:51 +08:00
simbit18
09fcec8fae arch/arm/src/stm32f7/Kconfig: Fix Kconfig style
Remove spaces from Kconfig files
2023-05-19 21:18:51 +08:00
simbit18
fe8289bbc0 arch/arm/src/gd32f4/Kconfig: Fix texts GD32F4_TIMER0_CH3O
correct  GD32F4_TIMER0_CHANNEL2 -> GD32F4_TIMER0_CHANNEL3
fix texts
Remove spaces from Kconfig files
2023-05-19 21:18:51 +08:00
zhangyuan21
3b074b153b arch/armv8-m: add ARMV8M_TRUSTZONE_HYBRID feature
Some chips only have one core that supports secure in smp mode,
so need change EXC_RETURN to non-secure when switching to a core that
does not support secure.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-19 11:55:18 +08:00
jturnsek
ba411fb53d Wrong dlastsga or slast setting if doff or soff larger than one 2023-05-19 10:23:29 +08:00
jturnsek
8976ded08a Base address missing from imxrt_flexio_get_shifter_buffer_address returned address 2023-05-19 10:23:19 +08:00
Petro Karashchenko
e85afaf6cf arch/arm/src/cxd56xx: fix style issues
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-05-19 02:40:38 +08:00
simbit18
c2779e5171 arch\arm\src\lpc54xx\Kconfig: Fix indentation
Remove TABs
2023-05-18 15:43:22 +03:00
simbit18
0b97979378 arch/arm/src/stm32h7/stm32_usbhost.c: Fix nxstyle errors
error: Long line found
2023-05-18 20:14:45 +08:00
zhangyuan21
3d47505ec7 arch/arm: Add a "cc" flag to instructions that may modify condition flag.
Notify the compiler that the condition flag has changed to prevent the
compiler from optimizing and reordering instructions, which may cause exceptions.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-18 17:23:16 +08:00
zhangyuan21
150680d677 arch/arm: set arm_testset to weak function
Some chips require the implementation of
their own unique test set function.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-18 13:46:27 +08:00
Xiang Xiao
7dc0d70092 arch: Save sigdeliver into xcp in the case of signal self delevery
to avoid the infinite recusive dispatch:
*0  myhandler (signo=27, info=0xf3e38b9c, context=0x0) at ltp/testcases/open_posix_testsuite/conformance/interfaces/sigqueue/7-1.c:39
*1  0x58f1c39e in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:167
*2  0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*3  0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049334) at signal/sig_dispatch.c:115
*4  0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049334) at signal/sig_dispatch.c:435
*5  0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*6  0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*7  0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*8  0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049304) at signal/sig_dispatch.c:115
*9  0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049304) at signal/sig_dispatch.c:435
*10 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*11 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*12 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*13 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf40492d4) at signal/sig_dispatch.c:115
*14 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf40492d4) at signal/sig_dispatch.c:435
*15 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*16 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*17 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*18 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf40492a4) at signal/sig_dispatch.c:115
*19 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf40492a4) at signal/sig_dispatch.c:435
*20 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*21 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*22 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*23 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049274) at signal/sig_dispatch.c:115
*24 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049274) at signal/sig_dispatch.c:435
*25 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*26 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*27 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*28 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049244) at signal/sig_dispatch.c:115
*29 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049244) at signal/sig_dispatch.c:435
*30 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*31 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-17 11:53:18 -06:00
Xiang Xiao
7a8cf7ff70 Indent the include statement by two spaces
follow the coding style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-16 12:34:32 -03:00
Lwazi Dube
555506a584 arch/arm/sama5: Make EHCI work with slow devices.
Make low/full speed devices work with EHCI while OHCI is disabled. A
high speed USB hub has to be plugged into the root hub. This change
will also allow the optional use of a full speed hub between the
high speed hub and the low/full speed device. A recursive mutex is
used to avoid deadlocks.
2023-05-16 08:14:54 +02:00
raiden00pl
507aa430c9 stm32h7/Kconfig: fix CI 2023-05-16 03:11:29 +08:00
Sebastien Lorquet
567a3ca37c Fix some warnings in STM32H7 IWDG 2023-05-15 19:34:17 +08:00
raiden00pl
5c3fa2d788 stm32h7/otg: allow USBDEV and USBHOST to work simultaneously 2023-05-15 17:32:32 +08:00
raiden00pl
eee25ea1eb stm32h7/otg: move sanity checks to common header file for use USBDEV and USBHOST 2023-05-15 17:32:32 +08:00
simbit18
ac392b5306 arch/arm/src/stm32f7/stm32_usbhost.c: Fix nxstyle errors
error: Long line found
2023-05-15 10:44:17 +08:00
TimJTi
b4b9a180c0 Add ATSAMA5D2/D4 Secure Fuse Controller (SFC) driver 2023-05-12 16:29:48 -03:00
simbit18
aa0cb3f76f Fix typos (s/FRQUENCY/FREQUENCY/)
Fix various typos FRQUENCY -> FREQUENCY
2023-05-13 00:31:26 +08:00
raiden00pl
d205c8c0e0 arch/stm32f7: fixes for pinmap 2023-05-12 11:43:08 +08:00
Alan Carvalho de Assis
54d92d1a0f Fix typo -EACESS -> -EACCES 2023-05-12 06:29:35 +03:00
Lwazi Dube
d66282a893 usbhost: Fix function address generation for multi-port root hubs.
Devices connected to the same USB bus should have unique function addresses.
This was not true for root hubs with multiple ports. After this change,
enumeration is more reliable on the sama5d3-xplained board when both root hub
ports are used.

This change amounts to using one usbhost_devaddr_s object per root hub
instead of one per root hub port. For the majority of boards only one
root hub port is available so no change in behavior should be expected.
2023-05-11 09:44:18 +02:00
Takumi Ando
08eef2a700 stm32f0l0g0: Fix GPIO port definitions
These series have the following GPIO ports:
- STM32F03X: A to D, and F
- STM32F05/07/09X: A to F
- STM32G0X: A to F
- STM32L0X: A to E, and H

Signed-off-by: Takumi Ando <t-ando@advaly.co.jp>
2023-05-10 18:01:07 +08:00
Takumi Ando
94eb8a0ee0 stm32f0l0g0: Add GPIOE to STM32G0x
All STM32G0x series have 6 GPIO ports A to F.

Refered: RM0444, RM0454

Signed-off-by: Takumi Ando <t-ando@advaly.co.jp>
2023-05-10 18:01:07 +08:00
David Sidrane
8068dc0238 stm32h7:sdmmc It is not an error if no wait was needed
If the CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE is enabled and the
   card is found to be ready in the waitenable call. Then
   we do not need a Watchdog nor to configure the pin for
   IRQ to detect ready.

   This was reported as an error, and it is not, it simply means
   we do not have to wait.
2023-05-10 00:46:44 +08:00
simbit18
58ebf26b98 arch/arm/src/tlsr82/Kconfig: Fix indentation
Remove spaces from Kconfig
Add TABs
2023-05-10 00:45:29 +08:00
simbit18
79d6d56532 arch/arm/src/sama5/Kconfig: Fix indentation
Remove spaces from Kconfig
Add TABs
2023-05-10 00:45:29 +08:00
simbit18
64c4fb0a53 arch/arm/src/s32k3xx/Kconfig: Fix indentation
Remove spaces from Kconfig
Add TABs
2023-05-10 00:45:29 +08:00
simbit18
02c9e20b8d arch/arm/src/lpc43xx/Kconfig: Fix indentation
Remove spaces from Kconfig
2023-05-10 00:45:29 +08:00
simbit18
1fc6a4469a arch/arm/src/kinetis/Kconfig: Fix indentation
Remove spaces from Kconfig
2023-05-10 00:45:29 +08:00
simbit18
75b02b037c arch/arm/src/imx6/Kconfig: Fix indentation
Remove spaces from Kconfig
Add TABs
2023-05-10 00:45:29 +08:00
Filipe Cavalcanti
c5f3d3d596 arch/arm/src/common/tiva_i2c.c: Update the current message buffer before writing to I2C data register. 2023-05-09 12:22:48 +03:00
Lwazi Dube
5a553db88a arch/arm/sama5: Fix OHCI SchedulingOverrun interrupt storm.
The following message is printed continuously and the nsh
shell is unusable on sama5d3-xplained.
"OHCI ERROR: Unhandled interrupts pending: 000001". This
happens when a keyboard is removed and reinserted on
port3 (lower port) while a bluetooth dongle is in port2.
2023-05-09 10:18:34 +08:00
simbit18
8a0729ac18 arch/arm/src/stm32h7/kconfig
Remove spaces from Kconfig
2023-05-08 12:42:54 -03:00
simbit18
5ed2d90c31 arch/arm/src/sama5/kconfig: Fix indentation
Remove spaces from Kconfig
Add TABs
2023-05-08 12:42:54 -03:00
simbit18
4d48e4626d arch/arm/src/imxrt/Kconfig: Fix indentation
Remove spaces from Kconfig
2023-05-08 12:42:54 -03:00
Filipe Cavalcanti
9355bd9d01 boards/arm/tiva: mpu6050 driver binding to TM4C1294
Fixed printf warning during compilation and added MPU6050 to bringup of tm4c.
2023-05-08 11:48:06 -03:00
Xiang Xiao
6f6fce95a2 Replace all sprintf with snprintf
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-08 09:57:01 +02:00
hujun5
0f243bde33 arch: fix the issue of asynchronous signal processing
in SMP, signal processing cannot be nested, we use xcp.sigdeliver to identify whether there is currently a signal being processed, but this state does not match the actual situation
One possible scenario is that signal processing has already been completed, but an interrupt occurs, resulting in xcp.sigdeliver not being correctly set to NULL,
At this point, a new signal arrives, which can only be placed in the queue and cannot be processed immediately
Our solution is that signal processing and signal complete status are set in the same critical section, which can ensure status synchronization

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-08 09:11:14 +02:00
zhangyuan21
841b178782 assert: show stacks with the sp from regs
1. Get the value of sp from dump regs when an exception occurs,
   to avoid getting the value of fp from up_getsp and causing
   incomplete stack printing.
2. Determine which stack the value belongs to based on the value
   of SP to avoid false reports of stack overflow

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-05 13:40:04 +08:00