When using HSE to clock RTC NuttX internal time is gaining 5.5 second per
minute. Problem was NuttX using 7182 for one of the RTC division factors,
it should have been 7812. The incorrect factors used are 7182 and 0xff.
These are used in 3-4 places within Nuttx and other places as 7812 and 0xff.
However, the STMicro app note AN4759 suggests using 7999 and 124, which is
what I've used.
Explanation: These 2 factors are used to divide the HSE clock (which at this
point is 1 MHz) to 1 Hz for the RTC hardware.
To test the 2 factors, add 1 to both numbers and multiply them together.
The result needs to be as close as possible to 1 MHz.
The suggested values of 7999 and 124 => 8000*125 = 1,000,000, the prime
factors. So, the best fix for Nuttx would be these values.
Issue discovered and fixed by Peter Moody
This patch adds corrected implementation of FLASH memory to be used
with progmem driver for use with mtd filesystems like nxffs or smartfs.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
Summary:
- I noticed that QEMU shows a high CPU load.
- This commit re-adds imx_idle.c to avoid this issue.
Impact:
- None
Testing:
- Tested with sabre-6quad:smp with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This patch implements working support for EXTI GPIO.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
--
v1 -> v2:
Suggested by: Petro Karashchenko
- change (1 << n) to (1 << (n)) in macro definition
- change 1 << X to (1 << X) in code
- fix alignment
v2 -> v3:
Suggested by: Petro Karashchenko
- I was supposed to change (1 << pin) to 1 << pin, not the other way around:)
This patch adds new chip family, stm32wl5x. This is bare minimum
implementation of said chip. I've tested this by running nsh.
There are only two chips in this family, stm32wl55 and stm32wl54.
The only difference between them is that stm32wl55 has LORA.
stm32wl5 is dual CPU (not core!). Right now only CPU1 is implemented.
CPU0 has access to radio hardware (while CPU1 does not). Chip is
designed so that CPU0 handles radio traffic while CPU1 does the
heavy lifting with data - there is communication pipe between two
CPUs.
I plan to use nuttx on CPU1 and LORA from stm32cube on CPU0 so I
don't have implementing CPU0 right now - once we have working LORA
in nuttx this may change.
Peripherals (except for radio) are shared so it's best to focus on
CPU1 to initialize all peripherals so that CPU0 can only use them
later. There is no real benefit to implement CPU0 if we don't have
working LORA/radio support in nuttx.
In time I will be implementing more and more things from this chip.
Right now I would like this minimal implementation to be merged in
case someone wants to work on this chip as well.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
---
patch v1->v2
- fixed formatting (suggested by Alan Carvalho de Assis)
- rebased patch to master (previous patch was based on nuttx-10.2
and did not compile on master)
Change pin initialization timing for camera from board power on to camera device
power on for the following purposes.
- avoid unnecessary power consumption
- Make the corresponding pins available for other uses when camera is not in use
RF and system timer interrupt are used for ble.
tlsr82_flash.c:
1. BLE will loss packets during flash operation beacause the interrupt
is disabled and the operation take too long (especially erasing,
about 100ms), so allow RF and system timer interrupt during flash
operation;
2. Add sched_lock()/sched_unlock() to avoid the task switch in ble and
system timer interrupt;
flash_boot_ble.ld:
3. Because of 1, the code executes in RF and system timer interrupt
must be in ram to avoid bus error. The sem_post() will be called and
const variable g_tasklisttable will be accessed in RF and system
timer interrupt handler;
4. To improve the performance, copy some frequently called function to
ram as well, such as: sem_take(), sched_lock(), sched_unlock(),
some lib functions, some zephyr ble functions and some tinycrypt
functions;
5. The RF and system timer interrupt handler will call some libgcc
functions, so copy all the libgcc functions to ram exclude _divdi3.o,
_udivdi3.o and _umoddi3.o;
tlsr82_serial.c
6. Make up_putc() be thread safe, add enter/leave_critical_section() in
function uart_send_byte();
tc32_doirq.c
7. Increase the RF and system timer interrupt response priority;
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
since the code could map the unsupported work to the
supported one and remove select SCHED_WORKQUEUE from
Kconfig since SCHED_[L|H]PWORK already do the selection
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
The current SAMv7 PWM driver assumes that all PWM channels should
work in sync mode, but that is a partial case of a generic PWM
driver operation.
Start SAMv7 PWM channels in async mode. The sync mode should be
implemeted either using ioctl command or via a separate Kconfig
option.
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
1. Add vbat mode for chip internal voltage sample;
2. Add adc channel config;
3. Using DFIFO2 to get the sample value, follow telink sdk.
4. Add calibration function and config;
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Number of channels are now set based on enabled modules (channels) in
configuration instead of the usage of static 4.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Number of channels are now set based on enabled channels in configuration
instead of the usage of static 4.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Implement a generic access rights modification procedure instead
of the procedures that only do one thing (enable/disable write)
to one section (text).
1. using armv6-m arm_irq();
2. simplify the interrupt number get process;
3. To improve the performance, move common exception code to ram_code.
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
fix warning:
common/arm_createstack.c: In function 'up_create_stack':
common/arm_createstack.c:154:11: warning: format '%d' expects type 'int', but argument 3 has type 'size_t'
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
1. add pulse count support for pwm0;
2. add more detailed config for pwm;
3. pwm configuration and start process optimize;
4. tlsr82/Kconfig format;
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Summary:
- TIVA_WITH_QEMU is used to run the NuttX with QEMU
- The configuration should not depend on TIVA_ETHERNET
- This commit fixes this issue
Impact:
- None
Testing:
- Tested with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- In case of SMP and ADDRENV, allocate the page table for each cpu
- Each cpu holds separated addrenv and MMU setting
Impact:
- armv7-a
Testing:
- sabre-6quad:smp w/ qemu
- sabre-6quad:knsh w/ qemu
- sabre-6quad:knsh_smp w/ qemu (WIP)
Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
Note that pinmap.h, irq.h, fdcan.h still need to be updated with proper
register definitions for the FDCAN3 peripheral present in
STM32H7[2|3][3|5] MCUs
Adds stubs for up_addrenv_text_enable/disable_write. These don't have
to do anything as the ARM MMU allows setting access per mode. Currently
the settings for user .text area grants the kernel write access, but
revokes user write access.
Summary:
- The stack pointer is subtracted to alloc xcptcontext area
in the __cpu?_start block
- Fix the stack coloration overrun to the previous cpu's xcpt area
Impact:
- armv7-a's smp configuration
Testing:
- smp and ostest on sabre-6quad:smp w/ qemu
Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
Summary:
- Use CPS instruction to change cpu mode for code simplification
- CPS which changes cpu mode is available in armv6 and above
Impact:
- armv7-a/r
Testing:
- smp and ostest on sabre-6quad:smp w/ qemu
Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
Using the Kconfig macro does not work for RISC-V target, as there the
user heap follows .data/.bss and does not obey any Kconfig provided
boundary.
Added stubs for ARM and Z80 also.
common/arm_assert.c:80:14: warning: format specifies type 'unsigned int' but the argument has type 'uint32_t' (aka 'unsigned long') [-Wformat]
stack, ptr[0], ptr[1], ptr[2], ptr[3],
^~~~~
include/debug.h:119:59: note: expanded from macro '_alert'
__arch_syslog(LOG_EMERG, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
~~~~~~ ^~~~~~~~~~~
Signed-off-by: chao.an <anchao@xiaomi.com>
Selecting this option will pass "-Map=$(TOPDIR)$(DELIM)nuttx.map" to ld
when linking NuttX ELF. That file can be useful for verifying
and debugging magic section games, and for seeing which
pieces of code get eliminated with DEBUG_OPT_UNUSED_SECTIONS.
Signed-off-by: chao.an <anchao@xiaomi.com>
Enable this option to optimization the unused input sections with the
linker by compiling with " -ffunction-sections -fdata-sections ", and
linking with " --gc-sections ".
Signed-off-by: chao.an <anchao@xiaomi.com>
This PR resolved 2 issues:
1. CURRENT_REGS is not set correctly on swint handling
2. group env is not changed properly
Signed-off-by: chao.an <anchao@xiaomi.com>
since it is broken and inefficient, and then removed by:
commit dc961baaea
Author: chao.an <anchao@xiaomi.com>
Date: Thu Apr 14 18:07:14 2022 +0800
arm/armv7-[a|r]: move fpu save/restore to assembly handler
Save/Restore FPU registers in C environment is dangerous practive,
which cannot guarantee the compiler won't generate the assembly code
with float point registers, especially in interrupt handling
Signed-off-by: chao.an <anchao@xiaomi.com>
commit 8d66dbc068
Author: chao.an <anchao@xiaomi.com>
Date: Thu Apr 7 13:48:04 2022 +0800
arm/armv[7|8]-m: skip the fpu save/restore if stack frame is integer-only
Signed-off-by: chao.an <anchao@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
