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18352 Commits

Author SHA1 Message Date
Abdelatif Guettouche
11216257cf esp32_rt_timer.c: Don't nest calls to spin_lock_irqsave with a device 
specific spinlock, this will lead to deadlocks.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
e847c61801 esp32_wifi_adapter.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
32f7471f9e esp32_wlan.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
4ae1285124 esp32_emac.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
e64390d5e9 esp32_rt_timer.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
c61009c2cf esp32/esp32_spi_slave.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
2273684cb1 esp32/esp32_spi.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
0123243f9a esp32/esp32_i2c.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
0af9a49d9c esp32/esp32_oneshot_lowerhalf.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
698af43d78 esp32/esp32_freerun.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
04bd27400a xtensa/esp32_wdt_lowerhalf.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
19a096cdfe arch/xtensa/esp32_tim_lowerhalf.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Gustavo Henrique Nihei
ff705586bb xtensa/esp32s2: Provide SPI Flash parameters to MCUboot build 
Also unify bootloader config creation to reduce duplication.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei
4d5e0f8fe1 xtensa/esp32: Provide SPI Flash parameters to MCUboot build 
Also unify bootloader config creation to reduce duplication.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei
99ac065d0a risc-v/esp32c3: Provide SPI Flash parameters to MCUboot build 
Also unify bootloader config creation to reduce duplication.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei
cc78541966 risc-v/esp32c3: Add esp-nuttx-bootloader folder to gitignore list 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei
ae25ebce4c risc-v/esp32c3: Fix wrong arch in the path to chip folder 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Abdelatif Guettouche
a7d8d9dd98 esp32s2/tie.h: Run the file though detab. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-14 07:39:54 -03:00
Abdelatif Guettouche
6d246eb18f esp32s2/tie.h: The old tie.h file was from ESP32 which doesn't apply to 
ESP32-S2.  This commit gets the correct S2 tie.h file

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-14 07:39:54 -03:00
Abdelatif Guettouche
217fd97fd3 xtensa_coproc.S: Correctly save/restore coprocessor0 state. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-14 07:39:54 -03:00
Abdelatif Guettouche
7420f245bc xtensa_context.S: Save and restore SCOMPARE1 when necessary. 
SCOMPARE1 is used by some atomic instructions and need to be preserved
during a context switch.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-14 06:32:17 -03:00
Alin Jerpelea
b9986ca016 arch: arm: update licenses to Apache 
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-10-11 10:13:07 +02:00
jsun
c58fddb915 Open ble controller adaptation code 
N/A

Signed-off-by: jsun <jsun@bouffalolab.com>
 2021-10-08 02:30:27 -07:00
Jari van Ewijk
e4752fbaee S32K1xx arch: Add (optional) support for SPI native/hardware chip select 2021-10-05 06:07:18 -07:00
Gustavo Henrique Nihei
47e804b167 risc-v/esp32c3: Make BLE adapter code compliant to nxstyle 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-05 08:45:40 -03:00
Alan C. Assis
867c6d0636 esp32: Add initial support to Bluetooth Low Energy 
Co-authored-by: saramonteiro <saramonteirosouza44@gmail.com>
Co-authored-by: Gustavo Henrique Nihei <gustavonihei@gmail.com>
 2021-10-04 15:10:37 -03:00
Abdelatif Guettouche
d22b4ec539 espxx_rng.c: Add "/" at the beginning of paths for consistency. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
Abdelatif Guettouche
c811cefa2d esp32c3_rng.c: Remove unused functions. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
Abdelatif Guettouche
5c6a30c00b esp32_rng.c: Remove the initialization guard. The init function is 
called only once during startup.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
Abdelatif Guettouche
6a262c5203 esp32_rng.c: Remove unused functions. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
liuhuan
ee6138e9ba power: Open CONFIG_PM compilation failed 
include debug.h

Signed-off-by: liuhuan <liuhuan16@xiaomi.com>
 2021-09-30 07:16:07 -07:00
Jari van Ewijk
cf6dcbc6fd S32K1XX arch: gpioread may also be used for output pins 2021-09-30 04:30:50 -07:00
Xiang Xiao
77bc1d1bdf power/battery: Move the enumurate to the common place 
so the userspace program can handle the different battery driver equally

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-30 14:58:42 +09:00
P.Brier
b9d1fcb232 Use ethernet MAC programmed in imxrt OCOTP MAC0/MAC1 (teemsy board has this) 2021-09-29 20:45:14 -07:00
Sara Souza
8a142f474e xtensa/esp32-s2/rttimer: Disable alarm before setting a new value and enabling it 2021-09-28 21:02:57 -03:00
Sara Souza
33f2d46bff risc-v/esp32-c3/rttimer: Disable alarm before setting a new value and enabling it 2021-09-28 21:02:57 -03:00
Alin Jerpelea
15a37c5a5a arch: Omni Hoverboards: update licenses to Apache 
Gregory Nutt has submitted the SGA
Omni Hoverboards has submitted the SGA
David Sidrane has submitted the ICLA
Mateusz Szafoni has submitted the ICLA
Sebastien Lorquet has submitted the ICLA
Paul Alexander Patience has submitted the ICLA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-09-28 04:37:38 -07:00
Gustavo Henrique Nihei
20341e6f17 risc-v/esp32c3: Enable support for "make bootloader" target 
This enables the provisioning of the bootloader binaries through the
build system.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-27 18:22:29 -07:00
Gustavo Henrique Nihei
3c63cb522c risc-v/esp32c3: Enable booting from MCUboot bootloader 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-27 18:22:29 -07:00
Gustavo Henrique Nihei
a5f9e29d78 xtensa/esp32s2: Enable support for "make bootloader" target 
This enables the provisioning of the bootloader binaries through the
build system.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-27 18:21:53 -07:00
Gustavo Henrique Nihei
800678ca78 xtensa/esp32s2: Enable booting from MCUboot bootloader 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-27 18:21:53 -07:00
Jari van Ewijk
62c41a723b s32k1xx_eeeprom.c - fix compiler warnings 2021-09-27 06:02:59 -07:00
Abdelatif Guettouche
5336704c77 esp32_start.c: Initialize the SPI RAM before enabling its cache. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-27 05:13:51 -07:00
Gustavo Henrique Nihei
c23986ec63 xtensa/esp32: Select ARCH_HAVE_BOOTLOADER for ESP32 chips 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-24 10:48:19 -07:00
Gustavo Henrique Nihei
86518bdf25 tools: Trigger clean_bootloader on distclean for supported chips 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-24 10:48:19 -07:00
Gustavo Henrique Nihei
4ac3044cc3 xtensa/esp32: Enable build system to download or build bins from source 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-23 20:52:25 -07:00
Sara Souza
9c2c5d3919 risc-v/esp32-c3: fix pid initiatialization on esp32c3_rt_timer.c 
pid variable was initialized to -EINVAL to prevent rt_timer_deinit
from delete an invalid kthread. But priv->pid was being overwritten in the
rt_timer_init, so in case of failure to create a kthread, it would
call rt_timer_deinit with a non expected initialization value.
 2021-09-23 19:01:27 -07:00
Sara Souza
d0e7d7b77f risc-v/esp32-c3: Remove _s of non static variables from esp32c3_rt_timer.c 2021-09-23 19:01:27 -07:00
Abdelatif Guettouche
f2f2040c44 esp32_spiram/psram/himem: Add and fix the files' sections. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-23 02:49:11 -07:00
Abdelatif Guettouche
3d8a6fb676 esp32_spiram.c: Remove esp_himem_reserved_area_size from esp32_spiram.c 
file.  This function is already defined in esp_himem and is used only
when that file is built.  We don't need another weak function.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-23 02:49:11 -07:00
Abdelatif Guettouche
2834d2a46f esp32_spiflash.c/esp32_spiram.c: Remove some unused macros/functions/variables. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-23 02:49:11 -07:00
Xiang Xiao
47c60b2de8 arch/arm: Remove -march and -mtune 
since -mcpu is enough https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58869

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-23 11:48:11 +02:00
Jari van Ewijk
bbb2f1f8c7 S32K1XX: Add LPI2C slave support 2021-09-22 19:36:34 -07:00
Sara Souza
962059f843 xtensa/esp32-s2: Adds oneshot device driver support 2021-09-22 22:53:54 -03:00
David Sidrane
6d299ce802 stm32h7:DMA_TRBUFF is DMA_SCR_TRBUFF 2021-09-22 22:48:10 -03:00
Sara Souza
fba6fa2dc1 xtensa/esp32-s2: Adds support to rt_timer and systimer to ESP32-S2. 2021-09-22 17:18:24 -03:00
Sara Souza
2cd4f4af79 xtensa/esp32-s2: Adds freerun timer wrapper 2021-09-22 09:38:10 -03:00
Gustavo Henrique Nihei
e651ef0969 arch/risc-v: Remove CODE qualifier for RISC-V-specific files 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei
06f4ee850a arch/risc-v: Remove FAR qualifier for RISC-V-specific files 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei
e9c17c9332 risc-v/rv32m1: Fix wrong position for ++ operator on serial driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei
eca1f86294 arch/xtensa: Remove CODE qualifier for Xtensa-specific files 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei
e13dd7dab9 arch/xtensa: Remove FAR qualifier for Xtensa-specific files 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei
58f87ef443 xtensa/esp32: Fix wrong position for ++ operator on I2C driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Jari van Ewijk
e5f17f6604 S32K1XX: Add FlexIO registers 2021-09-22 03:15:42 -07:00
David Sidrane
a9ff808dd1 stm32xx:sdmmc/sdio remove redundant GPIO config 
The stm32_gpiosetevent calls stm32_configgpio. So
   the pin is infact restored to the SDMMC/SDIO D0.

   The seconday init, dropped interrupts in a debug
   build with HW stack checking on after the GPIO glich
   fixes and that was how it was detected.
 2021-09-21 18:25:16 -07:00
David Sidrane
a8d5f21f81 stm32H7:Etablish device before enabling outputs 
This prevents gliches on changing to an output mode.
   If not the ALT mux can be selecting a IP block that
   is drving the line to say 0. Then the output is connected
   to that source, then swithced to the correct source.
 2021-09-21 18:25:16 -07:00
David Sidrane
5e19ebb818 stm32F7:Etablish device before enabling outputs 
This prevents gliches on changing to an output mode.
   If not the ALT mux can be selecting a IP block that
   is drving the line to say 0. Then the output is connected
   to that source, then swithced to the correct source.
 2021-09-21 18:25:16 -07:00
David Sidrane
d5e306e6f3 stm32:Etablish device before enabling outputs 
This prevents gliches on changing to an output mode.
   If not the ALT mux can be selecting a IP block that
   is drving the line to say 0. Then the output is connected
   to that source, then swithced to the correct source. This
   produced a 430 nS glich on a F4 @168 Mhz. It was a enough
   to corrupt an I2C device with a bus monitor.
 2021-09-21 18:25:16 -07:00
Sara Souza
fc12d6888b risc-v/esp32-c3: Group static variables into a struct and prevent an unitialized thread to be deleted 2021-09-21 15:45:59 +02:00
P.Brier
35824b449a Added CONFIG_ETH0_PHY_DP83825I to imxrt_enet: make driver compile for teensy 4.1 (link detection needs more checks to see if it works as expected) 2021-09-21 10:27:33 -03:00
P.Brier
f9850cf433 Fixed imxrt flexcan driver compilation error due to incorrect scope of variable 2021-09-21 10:00:12 -03:00
Abdelatif Guettouche
9f4d7e4767 xtensa_dumpstate.c: Fix the name of the TCB variable when dumping the 
backtrace.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-21 09:22:28 -03:00
Eero Nurkkala
812f504c16 mpfs: emmcsd: add Kconfig/Makefile and board files 
Add necessary Kconfig, Make.defs, Makefile and board
file changes.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-09-18 12:18:09 -03:00
Eero Nurkkala
772432e7c3 mpfs: add emmcsd driver 
This adds the emmcsd driver for the Polarfire Icicle kit.
The driver has been tested with several SD-cards, such as:

 - Kingston 32 GB SDS2 Canvas Select Plus
 - Kingston MicroSD Canvas Select Plus
 - Sandisk Extreme PRO 32 GB
 - Transcend 8 GB MicroSD

The internal eMMC hasn't been tested comprehensively.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-09-18 12:18:09 -03:00
Xiang Xiao
75a119ac1c arch: Compile up_puts in all Make.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-18 07:33:44 -03:00
Xiang Xiao
71c61b11d9 arch/riscv: Rename riscv_puts to up_puts 
since it's a common API defined in include/nuttx/arch.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-18 07:33:44 -03:00
Xiang Xiao
0625f9888c arch/z16: Implement up_puts function 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-18 07:33:44 -03:00
Xiang Xiao
5b75df2203 arch/sim: Implement up_puts function 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-18 07:33:44 -03:00
jsun
f4b6bb281c Update bl602 MTU_SIZE and TX_BUF_SIZE 
N/A

Signed-off-by: jsun <jsun@bouffalolab.com>
 2021-09-17 22:11:30 -05:00
jsun
d489392d08 Add bl602 os adapter layer 
N/A

Signed-off-by: jsun <jsun@bouffalolab.com>
 2021-09-17 22:11:30 -05:00
Abdelatif Guettouche
15b68b9abb esp32_spiflash.c: Correctly disable APP's CPU cache. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-17 17:43:45 -03:00
Masayuki Ishikawa
204d88bcf3 arch: cxd56xx: Replace the critical section with spinlock in cxd56_serial.c 
Summary:
- This commit replaces the critical section with spinlock in cxd56_serial.c

Impact:
- None

Testing:
- Tested with spresense:rndis_smp, spresense:rndis
  and spresense:rndis_wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-09-16 21:56:40 -05:00
Alin Jerpelea
48f92e6f1d author: Bill Gatliff : update licenses to Apache 
Gregory Nutt has submitted the SGA
Bill Gatliff has submitted the ICLA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-09-16 21:56:08 -05:00
Gustavo Henrique Nihei
52cea558af risc-v/esp32c3: Make the semaphore timeout on I2C configurable 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-16 14:07:26 -03:00
Gustavo Henrique Nihei
b33ccd01cf xtensa/esp32: Make the semaphore timeout on I2C configurable 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-16 14:07:26 -03:00
zhuyanlin
7947e50f06 xtensa:backtrace: flush to stack when in interrupt 
The registers may be in window during interrupt.
Flush window stack to stack first.
And fix warning in build.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-16 10:53:35 -05:00
Peter Bee
2a8b076b38 risc-v/esp32c3: fix pwm driver bug 
Wrong offset sign and pwm multichan fix

Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
 2021-09-16 08:38:49 -03:00
zhuyanlin
cdb441cc3f arch:xtensa:dumpstate: use sched_dumpstack 
Use sched_dumpstack instead. The backtrace infomation like

xtensa_user_panic: User Exception: EXCCAUSE=0009 task: hello
xtensa_registerdump:    PC: 202b32b8    PS: 00060030
xtensa_registerdump:    A0: a02acb87    A1: 20998d10    A2: ffffaaaa    A3: 12345678
xtensa_registerdump:    A4: a02ba26c    A5: 209949c0    A6: 20990994    A7: 00000258
xtensa_registerdump:    A8: a02b32af    A9: 20998cb0   A10: 0000000f   A11: 209949a0
xtensa_registerdump:   A12: a02be95c   A13: 20994980   A14: 00000003   A15: 209949d0
xtensa_registerdump:   SAR: 00000000 CAUSE: 00000009 VADDR: ffffaaaa
xtensa_registerdump:  LBEG: 00000000  LEND: 00000000  LCNT: 00000000
xtensa_registerdump:  TMP0: 202b1512  TMP1: 20998af0
sched_dumpstack: [BackTrace| 3|0]:  0x202acbae 0x202b232e 0x202b1912 0x202b19f5 0x202b24f1 0x202b152f    0x40023 0x202b32b0
sched_dumpstack: [BackTrace| 3|1]:  0x202acb87 0x202a86a4

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-16 10:32:38 +08:00
zhuyanlin
6e0f84dc88 arch:xtensa: add up_backtrace support 
Up_backtrace can be backtrace from task or interrupt.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-16 10:32:38 +08:00
zhuyanlin
3acdbef60d xtensa:arch: force up_getsp to inline 
Up_getsp may be not inline in gcc, thus get the sp
is up_getsp function's sp, not the caller function.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-16 10:32:38 +08:00
zhuyanlin
583dce0b98 arch:xtensa: remove WSBITS/WBBITS to core.h 
Remove WSBITS/WBBITS macro to core.h as may be used by
arch common code.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-16 10:32:38 +08:00
Cis van Mierlo
b316c679c1 S32K1xx: added PM support 2021-09-15 12:20:23 -03:00
SPRESENSE
74df4b70b3 drivers: video: Rearchitect video driver 
Rearchitect video driver:
- Define two video I/F(struct imgsensor_ops_s and struct imgdata_ops_s),
  and support them.
- CISIF driver supports new video I/F struct imgdata_ops_s.
- ISX012 driver supports new video I/F struct imgsensor_ops_s.
- Move ISX012 driver to general driver directory.
 2021-09-15 07:06:35 +02:00
Juha Niskanen
4487b352c0 arch/arm/src/stm32l4: fix baud rate setting for LPUART 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2021-09-14 08:57:25 -07:00
Harri Luhtala
7e3c813346 arch/arm/src/stm32l4: LPUART1 support 
Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>
 2021-09-14 08:57:25 -07:00
Abdelatif Guettouche
198c30eaa6 stm32*7/stm32_serial.c: Don't fake an interrupt when interrupts are not 
suppressed.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-14 22:50:43 +08:00
chao.an
ba9b829372 arch/arm: correct the function name from arm_getsp() to up_getsp() 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-09-14 22:48:47 +08:00
Cis van Mierlo
91c945a2e8 s32k1xx: added way to get the reset cause in proc fs 2021-09-14 08:35:41 +02:00
Sara Souza
83a9c2b24b xtensa/irq.h: Fixes the routine that clears the processor interrupt 2021-09-13 17:01:49 -03:00
Alin Jerpelea
bb54ed4227 author: OffCode Ltd : update licenses to Apache 
OffCode Ltd has submitted the SGA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-09-13 22:43:36 +08:00
zhuyanlin
8e6fbe700e xtensa:dcache_clean: use DCACHE_LINZESIZE instead of DCACHE_SIZE 
Clean_dcache use DCACHE_LINZESIZE instead of DCACHE_SIZE in addr loop

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-13 14:38:57 +08:00
Xiang Xiao
850367d5bb arch/arm: Add ARCH_CORTEXM55 Kconfig for cortex-m55 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-12 09:09:42 -03:00
Jukka Laitinen
3654db3517 mpfs: Modify IRQ handling to support also HART0 on PF 
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-09-11 23:33:01 +08:00
Janne Rosberg
8b560e7894 mpfs/i2c: fix bus initialize for i2c1 2021-09-11 23:33:01 +08:00
Janne Rosberg
1e3919e55a mpfs/corepwm: remove wrong header include 2021-09-11 23:33:01 +08:00
Janne Rosberg
7db3456824 risc-v/mpfs: serial: add termios support and init device clocks 2021-09-11 23:33:01 +08:00
Janne Rosberg
aa057e25f2 mpfs/i2c: adapt to sysreg define changes 2021-09-11 23:33:01 +08:00
Janne Rosberg
dc54ba924e mpfs/spi: adapt to sysreg define changes 2021-09-11 23:33:01 +08:00
Janne Rosberg
3e6b19dfc5 risc-v/mpfs: add more sysreg defines and fix clock and reset defines 2021-09-11 23:33:01 +08:00
Abdelatif Guettouche
31aa616bf2 stm32_serial.c: Don't fake a TX interrupt when interrupts are not 
suppressed.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-10 15:15:44 -07:00
David Sidrane
41e1696b27 stm32f4:USB otgdev Ensure proper EP state 
Repeated automated sercon, serdis on VBUS proved to fail
   for CDCACM DATA IN (device Serial TX). The root cause was
   that the EP was left active after disconnect. This resulted
   in the first serial write falling to kick-off the EP IN request.
   That should restart the EP ISR.
 2021-09-09 14:27:41 -04:00
David Sidrane
e488f0047d stm32h7:USB otgdev Ensure proper EP state 
Repeated automated sercon, serdis on VBUS proved to fail
   for CDCACM DATA IN (device Serial TX). The root cause was
   that the EP was left active after disconnect. This resulted
   in the first serial write falling to kick-off the EP IN request.
   That should restart the EP ISR.
 2021-09-09 14:27:41 -04:00
David Sidrane
21f049b43a stm32f7:USB otgdev Ensure proper EP state 
Repeated automated sercon, serdis on VBUS proved to fail
   for CDCACM DATA IN (device Serial TX). The root cause was
   that the EP was left active after disconnect. This resulted
   in the first serial write falling to kick-off the EP IN request.
   That should restart the EP ISR.
 2021-09-09 14:27:41 -04:00
Sara Souza
acf18bd82d risc-v/esp32-c3: refactor the Wi-Fi board logic. 
This commit moves the Wi-Fi initialization to
Wi-Fi specific file and to spiflash initialization.

It also reserves one partition for Wi-Fi use and for general use,
and makes it possible to me mounted by several FS.
 2021-09-09 20:14:04 +08:00
Sara Souza
11068fad1b risc-v/esp32-c3: Enable the allocation of multiple MTD SPI Flash partitions 2021-09-09 20:14:04 +08:00
Harri Luhtala
d4e59b7e8d arch/arm/src/stm32l4: add control for Vddio2 independent I/Os supply valid 
Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>
 2021-09-09 08:26:08 -03:00
Abdelatif Guettouche
4ef859924b esp32_serial.c: Release the spinlock before calling uart_xmitchars, this 
functions will call esp32_txint again which leads to deadlock since
esp32_txint has already locked the spinlock.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-09 19:35:17 +09:00
Abdelatif Guettouche
b5bb1fb8a3 esp32_serial.c: Replace critical section by a device specific spin lock. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-09 19:35:17 +09:00
Abdelatif Guettouche
f47d28c108 esp32_serial.c: Don't fake an interrupt when interrupts are not 
suppressed.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-08 09:27:08 -03:00
zhuyanlin
26b4bb3075 xtensa:cache: fix typo error 
use addr instead of add
 2021-09-08 11:19:02 +02:00
YAMAMOTO Takashi
4f7226ac4a arch/avr: Remove -nostartfiles -nodefaultlibs from LDFLAGS 
These options are not ld options.
The recent versions of ld complain on them.

https://sourceware.org/pipermail/binutils/2021-June/116826.html
 2021-09-08 09:40:48 +08:00
YAMAMOTO Takashi
58bdcbab9b Revert "Make: use gcc as LD" 
This reverts commit 45672c269d.

Because:

* It's very confusing to have cc as LD.
* I don't see what "-nostartfiles -nodefaultlibs" in LDFLAGS are
  supposed to do when we use LD directly. It would be simpler to
  remove them from our LDFLAGS.
 2021-09-08 09:40:48 +08:00
Jari van Ewijk
5f63fa391f Fix error in s32k118_pinmux.h 2021-09-07 17:34:19 -07:00
zhuyanlin
7b5c39a9d3 arch:xtensa: add xtensa_cache code support 
Add xtensa_cache code support
 2021-09-07 13:33:31 +08:00
zhuyanlin
d6fe0f18f5 arch:xtensa: add XTENSA_CACHE config support 
Add support for XTENSA_HAVE_ICACHE & XTENSA_HAVE_DACHE
 2021-09-07 13:33:31 +08:00
YAMAMOTO Takashi
5ad1cba338 Revert "arch: Replace ar and nm with gcc-ar and gcc-nm" 
This reverts commit b05737d78f.

Because it broke clang-based builds.
 2021-09-07 10:54:15 +08:00
Fotis Panagiotopoulos
eb48a0dbe0 Fix in STM32_UART8 Kconfig. 2021-09-07 10:52:44 +08:00
Jukka Laitinen
1b75b5d5aa Fix compilation of arm protected build 
Correct typos in include/nuttx/arch.h and suppress
"'noreturn' function does return" warning coming from arm_pthread_exit.c

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-09-07 00:31:47 +08:00
Juha Niskanen
b70ae9ae82 arch/arm/src/stm32l4/stm32l4_flash.c: fix FLASH_CONFIG_I to use dual-bank access 
This is currently only used on STM32L4+ devices. Page erase in
flash_erase() function supports only dual-bank mode so it makes little
sense to configure this for unsupported single-bank mode.

Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2021-09-04 14:31:16 +08:00
Sara Souza
26397c6695 xtensa/esp32: Wi-Fi board logic refactoring. 
This commit removes the initialization of the Wi-Fi partition
from the Wi-Fi board logic and moves it to the SPI Flash board code.

It creates 2 different partition (one for Wi-Fi and one for general
use).

It also allows these partitions to be mounted over several FSs.
 2021-09-04 14:30:02 +08:00
Juha Niskanen
508215581f arch/arm/src/stm32l4: fix STM32L4+ option bytes memory address 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2021-09-03 09:55:54 -03:00
liucheng5
fdb9576d7a feature: driver: Add a Linux SPI into simulator. 
When SIM_SPI is valid, a specified Linux SPI device ‘spidevN.P’(N is bus number and P is CS number) is attached to nuttx simulator, shown as 'spi0' under /dev. One may type spi command (need SPITOOL valid) in NSH to control the Linux SPI and exchange data, other devices such sensors can use it to debug in simulator on a Ubuntu PC. Note that a USB<>SPI module (e.g. CH341A/B) should be plugged in to achieve Linux SPI ports.

Change-Id: I275b2c2bbf6d14bcdf514c89efb9a2264d69e9a3
Signed-off-by: liucheng5 <liucheng5@xiaomi.com>
 2021-09-03 18:15:25 +08:00
Alin Jerpelea
a20d4ac4ec author: Aleksandr Vyhovanec: update licenses to Apache 
Aleksandr Vyhovanec has submitted the ICLA
as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-09-03 17:38:33 +08:00
Xiang Xiao
b05737d78f arch: Replace ar and nm with gcc-ar and gcc-nm 
to make enable LTO easily

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-02 10:02:14 -03:00
zhuyanlin
fd9ce0137e arch:xtensa: add xtensa mpu support 
Add support for Xtensa Memory Protect Unit.

Change-Id: I27e2f05daae24429ef7513d843b4f217daeefa0d
 2021-09-02 09:17:26 -03:00
Sara Souza
8081228556 xtensa/esp32-s2: Adds support to the timer driver 
Only one more support for ESP32-S2 chip.
 2021-09-01 14:10:01 -03:00
Gustavo Henrique Nihei
2071aadc0e sim: Inhibit stack protector on stack coloration function 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-01 23:11:03 +08:00
Michal Lenc
1ec0258407 arch/arm/src/imxrt/imxrt_flexcan.c: use SW control to check free MBs 
CAN_ESR2 register was having problems of havng the correct values when
the bus was busy (with 3 and more nods). The register bit fields were
incorrectly indicating that there is no free MB and would not updated
itself from this state which was causing the applications to freeze on
write. This change relies only on a software control which should avoid
the problems described above.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-08-31 14:47:41 -03:00
Masayuki Ishikawa
24697e8f67 arch: x86_64: Fix idle stack allocation 
Summary:
- I noticed that qemu-intel64:nsh does not work
- And I found that commit 6e6eecaa73 affected this issue
- This commit changes idle stack allocation to fix the issue

Impact:
- None

Testing:
- Tested with qemu-intel64:nsh and qemu-intel64:ostest

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-08-31 17:06:59 +08:00
Oleg
e95f23ef8b arch/arm/stm32f7/stm32_irq: Fix format strings 2021-08-31 16:56:55 +08:00
Alin Jerpelea
da92258333 arch: k210: remove extra license information 
the Apache license header uses a standard format and the extra information
should be removed.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-08-31 08:20:18 +09:00
Xiang Xiao
b0c782255c libxx: Change CXX_LIBSUPCXX to LIBSUPCXX 
align with other Kconfig(e.g. LIBCXXABI, LIBCXX, UCLIBCXX)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-28 17:14:48 -03:00
zhuyanlin
9ea7676731 arch:xtensa: rename XCHAL_INT_NLEVELS to XCHAL_NUM_INTLEVELS 
The name used in Tensilica support file core-isa.h for all vendors is
`XCHAL_NUM_INTLEVELS`.
Use a new name may be confused by newer porting xtensa arch.

Change-Id: Ie108d3fdfcc02c81f0eacfca852a1cfc9eea17de
 2021-08-28 21:51:45 +02:00
zhuyanlin
cd18d1f050 arch:riscv: remove arch atomic, use libc atomic when need 
It is more common for implement in libc/machine

Change-Id: I3da6c3db64adb78c05ddb26d3956817ac6ada93e
 2021-08-28 13:17:30 -03:00
Xiang Xiao
f0001574ed arch/armv8-m: Update per the latest architecture reference manual 
https://developer.arm.com/documentation/ddi0553/latest

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-27 11:39:27 +02:00
Abdelatif Guettouche
1385ea7673 arch/esp32: Properly handle GPIO interrupt in SMP. 
The PRO CPU and APP CPU have different peripherals for GPIO interrupts.
Each CPU needs to allocate an interrupt and attach it to its GPIO
peripheral.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-27 13:24:00 +09:00
chao.an
bcce3314e5 arch/arm/cortex-m: add up_backtrace support 
add up_backtrace support based on push/branch instruction

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-26 18:31:51 +08:00
chao.an
d5d6297ca1 arch/arm/assert: enhance the assert dump 
show the all tasks info including backtrace and registers

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-26 13:31:08 +08:00
chao.an
f14bd44001 arch/armv7: add up_backtrace support based on frame pointer 
This feature depends on frame pointer, "-fno-omit-frame-pointer" is mandatory

This feature can not be used in THUMB2 mode if you are using GCC toolchain,
More details please refer:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92172

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-26 13:30:08 +08:00
Kapil Gupta
ec99e11f5e esp32/softap: Enable the WPA2 by default to ask user password 
Signed-off-by: Kapil Gupta <kapil.gupta@espressif.com>
Co-author: Alan Carvalho de Assis <alan.carvalho@espressif.com>
 2021-08-26 13:26:57 +08:00
ligd
f1aec38ffa arm: add ARM_HAVE_NEON to Kconfig 
Change-Id: I112037aa15a6fae76cf4b7c2df10a42899c38a61
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-08-26 13:25:43 +08:00
Abdelatif Guettouche
fc594c5d25 esp32_irq.c: Extend the CPU interrupt/peripheral map to include the 
status of the interrupt (enabled/disabled).

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
810ed19b8f arch/xtensa/esp32_irq.c: Enable/disable interrupts using the Interrupt 
Matrix.

This allows manipulating interrupts from both CPUs.  Internal interrupts
however, still need to be disabled/enabled by each CPU.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
a7abd56448 arch/xtensa: Move the Xtensa specific part of interrupts to 
xtensa/include/irq.h

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
470799b0b3 arch/xtensa/esp32_irq: Remove the map/unmap IRQ functions they are used 
only inside this file.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
04cd520293 arch/xtensa/esp32: Merge esp32_intdecode with esp32_irq. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
79cc12c034 arch/xtesna/esp32: Merge the contents of esp32_cpuint and esp32_irq. 
They do the same thing (manipulate interrupts) keeping them separated
was making things harder.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
237aebb7e1 arch/xtensa/esp32_cpuint.c: Refactor retrieving the intmap and register 
address of a peripheral.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
02c17c3169 arch/esp32: Simplify the interrupt allocation process. 
Allocating and attaching interrupts were both exported outside, however
these two move hand in hand and we don't have to expose these details.
Also, the parameters passed are saved and will be used to retrieve
information about the interrupt and the attached peripheral.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
eefe7ebe5f xtensa/esp32_cpuint: export only one function to allocate a CPU 
interrupt.

That function will have a parameter to decide whether to allocate a
level sensitive interrupt or an edge sensitive interrupt.

All the drivers are also updated with this API change.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
dbdec45049 arch/xtensa/src/common: Use irq_spin APIs in modifyregXX 
Replace enter_critical_section with spin_lock_irqsave.
Replace leave_critical_section with spin_unlock_irqrestore.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-25 23:32:40 +08:00
Abdelatif Guettouche
5ff703d5d0 arch/*_testset: Fix few typos. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-25 00:20:20 +08:00
Alin Jerpelea
07d528fd8d license: Ken Pettit: update licenses to Apache 
Ken Pettit is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-08-23 11:41:41 +08:00
chao.an
6cfb132232 arch/cortex-m: replace arm_switchcontext to c-style 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-22 14:44:01 +08:00
chao.an
68d6dbf86f arch/riscv/assert: enhance the assert dump 
enhance the assert dump to show the all tasks info including backtrace and registers

[    7.617000] [ EMERG] up_assert: Assertion failed at file:rv32im/riscv_exception.c line: 94 task: init
[    7.617000] [ EMERG] riscv_dumpstate: Call Trace:
[    7.617000] [  INFO] [BackTrace| 3|0]:  0x4202001e 0x42007cb4 0x42005782 0x42000fe2 0x403801e2 0x403800e2 0x4200bdd0 0x42009894
[    7.617000] [  INFO] [BackTrace| 3|1]:  0x4200a62e 0x42008e8a 0x4200841e 0x42008320 0x42005ad0 0x42001a56
[    7.617000] [ EMERG] riscv_registerdump: EPC:4200bdd0
[    7.617000] [ EMERG] riscv_registerdump: A0:ffffffff A1:00000010 A2:3fc9a95c A3:00000031 A4:00000009 A5:00000002 A6:00000001 A7:00000074
...
...
[    7.617000] [ EMERG] riscv_showtasks: Tasks status:
[    7.617000] [ EMERG] riscv_taskdump: Idle Task: PID=0
[    7.617000] [ EMERG] riscv_taskdump: Stack Used=596 of 976
[    7.617000] [  INFO] [BackTrace| 0|0]:  0x4200787e 0x3fc94ff0
[    7.617000] [ EMERG] riscv_registerdump: EPC:4200787e
[    7.617000] [ EMERG] riscv_registerdump: A0:00000032 A1:3c1008fa A2:3fc94fa8 A3:00000000 A4:00000101 A5:00000032 A6:00000001 A7:00000074
...
[    7.617000] [ EMERG] riscv_taskdump:
[    7.617000] [ EMERG] riscv_taskdump: hpwork: PID=1
[    7.617000] [ EMERG] riscv_taskdump: Stack Used=292 of 2016
[    7.617000] [  INFO] [BackTrace| 1|0]:  0x420082a6 0x4200328c 0x42001ab4 0x42001a42
[    7.617000] [ EMERG] riscv_registerdump: EPC:420082a6
[    7.617000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fc98718 A2:3fc8307c A3:00000002 A4:00000000 A5:00000000 A6:00000000 A7:00000000
...

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-21 14:58:21 +08:00
chao.an
333191becd riscv/backtrace: add up_backtrace support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-21 14:56:34 +08:00
Abdelatif Guettouche
2925d4956b xtensa/esp32: Use up_cpu_index instead of this_cpu. 
this_cpu requires sched.h to be included.
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
5d626f7267 xtensa/esp32_irq.c: Hard code special IRQs in the IRQ map. These IRQs 
are do not go through the regular process where we attache the CPU
interrupt to a peripheral and update our map, also, they are fixed and a
have reserved CPU interrupt, thus hard code their values at startup.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
56a7f3b651 arch/xtensa/esp32: Update the drivers regarding the API change in IRQ 
handling.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
5be9f24fe5 arch/xtensa/esp32: Disable the CPU interrupt right when it's alloacted. 
At this point we are in a critical section and have all the necessary
information to disable the interrupt properly (CPU, and CPU interrupt).
Leaving it to the drivers will complicate things as converting from IRQs
to CPU interrupts could be tricky in SMP mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
97dca8fe10 arch/xtensa/esp32: Use the same g_intenable shadows in cpuint.c and 
irq.c

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
633cdf8e27 arch/xtensa/esp32: Map NuttX's IRQs to ESP32 CPU interrupts. 
This map also keeps track of the CPU that attached the IRQ.  This will
be used to properly disable the interrupt in the correct CPU in SMP
mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Sara Souza
e092c457e6 xtensa/lx7: Fix the CROSSDEV variable 2021-08-20 16:48:20 +02:00
Xiang Xiao
af72376773 fs: Remove magic field from partition_info_s 
since it is wrong and impossible to return file
system magic number from the block or mtd layer.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-20 09:19:52 -03:00
Antti Vähälummukka
6eb73ced51 arch/risc-v/src/mpfs: Add CorePWM driver 
Add a driver for CorePWM block, which can be instantiated on PolarFire SOC FPGA

This supports 2 CorePWM blocks on the FPGA. One CorePWM block provides 8 PWM output signals
 2021-08-20 08:56:30 -03:00
Xiang Xiao
4b41579ccf arch/armv8-m: Add SAU support 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-20 10:22:43 +09:00
raiden00pl
78962165d8 arch/stm32: add 3-phase Hall effect sensor lower half 2021-08-19 08:19:38 -07:00
chao.an
1060953567 sched/backtrace: add sched_backtrace support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-19 01:30:50 -07:00
chao.an
0a8d951837 arch/arm: correct the frame pointer register declare 
In AArch32, the frame pointer is stored in register R11 for ARM code or register R7 for Thumb code.
In AArch64, the frame pointer is stored in register X29.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-19 01:26:07 -07:00
Abdelatif Guettouche
cd0f64d779 xtensa/irq.h: Add a macro to convert to an IRQ from a peripheral ID. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-18 10:49:58 -03:00
raiden00pl
532ec126e9 stm32/stm32_serial.c fix compile error when CONFIG_STM32_SERIALBRK_BSDCOMPAT=y. 
Fix for https://github.com/apache/incubator-nuttx/issues/4353
 2021-08-18 04:43:32 -07:00
Abdelatif Guettouche
a220766d57 xtensa.h: Remove unused function prototype. 
ESP32 uses a different function to start the app CPU and no other xtensa
CPU uses this __cpu1_start function.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-18 04:41:40 -07:00
chao.an
e37d8da074 riscv/common: add CURRENT_REGS declare in RV32 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-18 04:40:38 -07:00
Juha Niskanen
e02e1c25f6 arch/arm/src/stm32l4/Kconfig: add new STM32L4+ chip types 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
Change-Id: I74050913643db23b4d03abaf516989ff3cdac142
 2021-08-17 06:27:18 -07:00
Alin Jerpelea
4b20cf30c0 arch: misoc: update licenses to Apache 
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-08-16 07:11:32 -07:00
Alin Jerpelea
351091ed75 author: Pierre-noel Bouteville: update licenses to Apache 
Gregory Nutt has submitted the SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-08-16 07:11:32 -07:00
Xiang Xiao
71269811ca mtd: Implement BIOC_PARTINFO for all drivers 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-16 10:08:26 -03:00
Virus.V
5a1de89370 riscv/bl602: Fix that AP cannot be start when STA have been started. 2021-08-16 02:06:59 -07:00
Xiang Xiao
f63d1cfbbb arch/arm: Add NVIC_FPCCR_XXX macro to avoid the hard code value 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-15 10:50:52 +02:00
Xiang Xiao
fad0c3b38b arch/arm: Add NVIC_CPACR_CP_XXX(n) macro to avoid the hard code value 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-14 11:41:59 -07:00
Xiang Xiao
33666832c5 arch/arm: Add NVIC_AIRCR_VECTKEY macro to avoid the hard code value 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-14 11:41:59 -07:00
Abdelatif Guettouche
5b350f3a0f arch/*_reprioritizertr.c: Fix typos in comments. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-14 11:19:34 -07:00
Gustavo Henrique Nihei
1dfcc6ab49 xtensa/esp32: Enable boot from Espressif's port of MCUboot 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-08-13 08:44:20 -03:00
zhuyanlin
1a1b1cc2b4 arch:xtensa: replace include file from src/chip_xxx to chip.h 
Use chip.h as a standard include file, replace chip_xxx in src dir
 2021-08-12 16:18:35 +02:00
zhuyanlin
30a2338e92 arch:esp: create chip.h header for chip src code. 
Create chip.h header for esp src code.
 2021-08-12 16:18:35 +02:00
zhuyanlin
6d592256fb arch:xtensa: add __ASSEMBLY__ for espxxx_soc.h 
Those header contain syntax not be recognize by gnu assembler.
 2021-08-12 16:18:35 +02:00
Alexander Vasiljev
4229099944 arch/arm/stm32h7: dma and serial: add TRBUFF flag. It is obligatory for uart. 2021-08-12 08:07:18 -03:00
Xiang Xiao
6b6c11f0ad mtd: Replace MTDIOC_XIPBASE with BIOC_XIPBASE 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-12 08:01:29 -03:00
Xiang Xiao
d1687418db mtd: Remove the empty MTDIOC_XIPBASE implmentation 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-11 09:50:51 -03:00
zhuyanlin
e333733053 xtensa:coproc: fix XTENSA_CP_ALLSET error in some case 
Consider follow coprocessor configuration case:

\#define XCHAL_CP_NUM                    1       /* number of coprocessors */
\#define XCHAL_CP_MAX                    2       /* max CP ID + 1 (0 if none) */
\#define XCHAL_CP_MASK                   0x02    /* bitmask of all CPs by ID */
\#define XCHAL_CP_PORT_MASK              0x00    /* bitmask of only port CPs */
\
\#define XCHAL_CP1_NAME                  "AudioEngineLX"
\#define XCHAL_CP1_IDENT                 AudioEngineLX
\#define XCHAL_CP1_SA_SIZE               208     /* size of state save area */
\#define XCHAL_CP1_SA_ALIGN              8       /* min alignment of save area */
\#define XCHAL_CP_ID_AUDIOENGINELX       1       /* coprocessor ID (0..7) */

In this case, XTENSA_CP_ALLSET is 0x1, but valid coprocessors
bitmap is 0x2, use marco XCHAL_CP_MASK instead, it is bitmap of all
vaild coprocs.

Change-Id: I63ec01e4bd0cbafc62d56636cc11bdc4a2f7857f
 2021-08-10 19:44:55 -07:00