Commit Graph

22236 Commits

Author SHA1 Message Date
Ville Juven
fa71bc3d74 riscv/syscall: Add dependency to RISCV_PERCPU_SCRATCH when LIB_SYSCALL=y
The per CPU scratch register is needed by system calls -> enable it by
default.
2024-08-07 02:41:14 +08:00
Julian Oes
75c65c7ce9 arch/stm32h7: add defines for USART clock selection
This adds the necessary defines to set the USARTs' kernel clock source
selection.

This is required for a configuration where the bootloader (running
before NuttX) changes the USARTs' clock selection, so they need to be
restored on board init.

This is according to the reference manual RM0399 page 448.
2024-08-06 14:31:21 +08:00
Filipe Cavalcanti
65e989e063 arch/risc-v: add support for motor control on ESP32|C6|H2 2024-08-05 15:35:19 -03:00
Yanfeng Liu
a36c168e54 riscv/nsbi: fix up_udelay for rv32
This fixes riscv_sbi_get_time for rv32 and NuttSBI is used.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-05 16:21:49 +08:00
chao an
4ef3eeb305 arch/x86_64: fix build break if disable CONFIG_SPINLOCK
Create version.h
chip/intel64_irq.c:78:34: error: conflicting type qualifiers for ‘g_irq_spin’
   78 | static spinlock_t                g_irq_spin;
      |                                  ^~~~~~~~~~
In file included from chip/intel64_irq.c:40:
include/nuttx/spinlock.h:168:28: note: previous declaration of ‘g_irq_spin’ with type ‘spinlock_t’ {aka ‘volatile unsigned char’}
  168 | extern volatile spinlock_t g_irq_spin;
      |                            ^~~~~~~~~~
chip/intel64_cpu.c: In function ‘x86_64_cpu_ready_set’:
chip/intel64_cpu.c:314:3: warning: implicit declaration of function ‘spin_lock’ [-Wimplicit-function-declaration]
  314 |   spin_lock(&g_ap_boot);
      |   ^~~~~~~~~
chip/intel64_cpu.c:322:3: warning: implicit declaration of function ‘spin_unlock’; did you mean ‘sched_unlock’? [-Wimplicit-function-declaration]
  322 |   spin_unlock(&g_ap_boot);
      |   ^~~~~~~~~~~

Signed-off-by: chao an <anchao@lixiang.com>
2024-08-05 16:20:47 +08:00
Yanfeng Liu
5848a8e77c riscv/qemu-rv: revise PROTECTED mode
This revises PROTECTED build for qemu-rv mainly to avoid hard-coded
addresses in linker scripts. It also added rv32 support, cleaned up
config `pnsh64` and added config `pnsh`.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-04 11:09:26 +08:00
Yanfeng Liu
cafee0e086 mm/mm.h: add mm_free_delaylist interface
This adds explicit `void mm_free_delaylist(heap)` interface so that
to force freeing the heap's delaylist.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-03 01:30:04 +08:00
Ville Juven
1f928b2338 qemu-rv: Add test target pnsh64 for BUILD_PROTECTED
This adds BUILD_PROTECTED target for rv-virt (rv-virt:pnsh64).
2024-08-02 20:29:11 +08:00
adriendesp
6ef8a73614 arch/xmc4 : fixed critical section in i2c_transfer
The critical section was declared at the wrong place.
The critical section wasn't left if error returned.
2024-08-02 20:28:25 +08:00
Lwazi Dube
a50dc7746c arm: Make ARMv5 boards work again
Fix some bugs found while trying run modern NuttX on an old board.
2024-08-02 13:39:40 +08:00
Yanfeng Liu
918ad10859 riscv/qemu: add NuttSBI support
This adds NuttSBI support for rv-virt device so that to enable CI
checks for NuttSBI later. It allows using `-bios nuttx` option to
run NuttX with QEMU v6.2 w/o OpenSBI.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-01 23:32:01 +08:00
Yanfeng Liu
ab7bc90ebb riscv/nsbi: halt upon sbi_mexception
This avoids endless restart if NuttSBI fails to enter S-mode.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-01 23:32:01 +08:00
Yanfeng Liu
5e551632dd riscv/nsbi: prefer PMP settings in device hook
This adjusts sbi_start behavior so that if SBI late initialization hook
is defined, PMP setting is assumed to be fully done in the hook, because
the default PMP operation may fail for various reasons such as lacking
free entries or the default setting doesn't work on devices like QEMU
v6.2.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-01 23:32:01 +08:00
Huang Qi
f9cc33468f riscv/espressif: Mark private data as static in esp_spi.c
These symbols only used in esp_spi.c and too simple
to conflict with others, so mark them as static:
- cfg
- ctx
- dev_cfg
- timing_param

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-08-01 23:28:53 +08:00
Ville Juven
cbb07a595e k230_start.c: Fix condition for k230_copy_init_data()
Fixes regression from https://github.com/apache/nuttx/pull/12220

Error: chip/k230_start.c:80:13: error: 'k230_copy_init_data' defined but not used [-Werror=unused-function]
   80 | static void k230_copy_init_data(void)
      |             ^~~~~~~~~~~~~~~~~~~
2024-08-01 23:27:30 +08:00
p-szafonimateusz
3c05da536a arch/intel64: add support for HPET as system clock
HPET can be used as system clock for x86_64

to set HPET as system clock you have to enable:
  CONFIG_ONESHOT=y
  CONFIG_ALARM_ARCH=y
  CONFIG_INTEL64_ONESHOT=y
  CONFIG_ARCH_INTEL64_HPET_ALARM=y

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-08-01 17:49:41 +08:00
Tiago Medicci
24954800a7 espressif: Update HAL version for all Espressif SoCs
Provides the most update libraries to support the drivers for the
Espressif SoCs.
2024-08-01 16:04:53 +08:00
Tiago Medicci
54b27c3d32 esp32s3/kconfig: Add more ESP32-S3 modules and fix comments
Other ESP32-S3 modules (with embedded flash and PSRAM) were added.
Also, the `help` section of the Kconfig was updated to better
describe the modules' flash and PSRAM sizes.
2024-08-01 16:04:53 +08:00
Huang Qi
6ea3bc1217 riscv/debug: Add support for steppoint
Steppoint can be implemented by icount(instruction count)
from RISC-V debug extension, but it may not implemented in all RISC-V cores.

Unfortunately, the currently supported RISC-V cores do not implement it.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-08-01 13:57:51 +08:00
Eren Terzioglu
00ff9ef15c esp32[c3|c6|h2]: Add SPI slave DMA support 2024-08-01 01:26:29 +08:00
Eren Terzioglu
f5b63cea18 esp32[c3|c6|h2]: Add SPI master DMA support 2024-08-01 01:26:29 +08:00
Inochi Amaoto
b35f7aed48 arch/risc-v: qemu: add AIA support
Implement AIA support for qemu rv-virt.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-31 12:43:04 -03:00
Inochi Amaoto
5f70307111 arch/risc-v: introduce AIA support
Advanced Interrupt Architecture (AIA) introduces flexiable interrupt
controll for RISC-V. It includes three parts: AIA CSRs, Incoming Message
Signaled Interrupt Controller (IMSIC) and  Advanced Platform-Level
Interrupt Controller (APLIC).

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-31 12:43:04 -03:00
Tiago Medicci
c99c3ceec2 up_copy_section: Improve function description
Add "Input Parameters" section to already existing definitions
and declarations of `up_copy_section` function.
2024-07-31 02:33:12 +08:00
Tiago Medicci Serrano
016bc47a63 esp32s3/elf: Enable ELF loader for ESP32-S3
Provide `up_copy_section` function that enables copying data using
the data bus. If the memory destination address is accessible
through the instruction bus, the data is copied using the
correspondent address accessible through the data bus.
2024-07-31 02:33:12 +08:00
zouboan
d74a612a6e zynq-mpsoc/zcu111: independent JTAG configs from normal nsh configs 2024-07-30 12:41:30 -03:00
p-szafonimateusz
07c1f5db92 arch/intel64/irq.h: rename rdtsc macros
rename _rdtsc macro to rdtsc to avoid conflict with external code
rename rdtsc macro to rdtscp to be the same as asm instruction used

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-07-30 21:53:08 +08:00
p-szafonimateusz
90e47bf1f5 arch/x86_64/src/intel64/intel64_cpu.c: remove workaround for spin_lock
remove workaround for spin_lock which is no longer needed after inline splinlock change
2024-07-30 21:40:53 +08:00
adriendesp
cd4fdf27c5 arch/xmc4 : i2c driver
Added lower half i2c driver
2024-07-30 18:23:19 +08:00
Yanfeng Liu
a6c7e68b5d riscv/qemu-rv: skip reloading mhartid
As a0 already has mhartid passed by SBI  or ZSBL, no need to load it
again here.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-30 18:20:22 +08:00
Tiago Medicci Serrano
c91599d34c esp32s3/i2s: Fix faulty initialization when SMP is enabled
The buffer initialization function (`i2s_buf_initialize`) calls
`i2s_buf_free`, which performs buffer initialization within a
critical section (`spin_lock_irqsave`). If this function is called
under the same critical section (same spinlock), initialization
will hang.
2024-07-30 01:44:57 +08:00
Tiago Medicci Serrano
1ab1a905b8 esp32s3/i2s: Add CONFIG_ESP32S3_I2S_MAXINFLIGHT to Kconfig
Enable setting the number of in-flight buffers to be used by the
I2S peripheral on ESP32-S3 using Kconfig.
2024-07-30 01:44:57 +08:00
anjiahao
bc1083ac33 arm_backtrace_unwind:Make the backtrace search the entire stack as much as possible
also fixbacktrace crash when idle thread lr is random

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-07-29 22:19:56 +08:00
Eren Terzioglu
98f5d6adc5 esp32[s2|s3]: Add temperature sensor support 2024-07-27 14:12:44 -03:00
Eren Terzioglu
e467a16abe esp32[c3|c6|h2]: Add temperature sensor support 2024-07-27 14:12:44 -03:00
Henry Rovner
23bc78a5b7 bl808_wdt: Expand function headers 2024-07-27 22:59:23 +08:00
Henry Rovner
42eafcdfa5 risc-v/bl808: Add watchdog driver
This change implements a driver for the two watchdog timers on the BL808, and enables it as part of the timer config. The driver is based on the GP timer driver.
2024-07-27 22:59:23 +08:00
Filipe Cavalcanti
91dfd20eaf arch/xtensa: add support for brushed DC motor control
arch/xtensa: add support for capture driver on ESP32 and ESP32|S3|

Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed

Basic bring up ready. New Kconfig options for motor.

Good motor registration

Working on enabling pwm generators

Working on enabling pwm generators

Added fops functions

Success on PWM 50%

stable pwm operation for bdc

Added loopback option for testing

Improved rules on fsm

Working motor direction control

Testing new ISR for fault handling

Issues on fault ISR

Removed fault implementation (not working)

Added support for esp32s3

Documentation improvements

Added default motor spin direction

Added parameter change while running

Review fixes

arch/xtensa: add support for fault signal on motor control

Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed

Basic bring up ready. New Kconfig options for motor.

Good motor registration

Working on enabling pwm generators

Working on enabling pwm generators

Added fops functions

Success on PWM 50%

stable pwm operation for bdc

Added loopback option for testing

Improved rules on fsm

Working motor direction control

Testing new ISR for fault handling

Issues on fault ISR

Removed fault implementation (not working)

Added support for esp32s3

Documentation improvements

Added default motor spin direction

Added parameter change while running

Got responsive fault indicator

Working brakes - still need to work on starting isr

Fixed single-time ISR initializiation

Working soft brake on fault

Improved KConfig for BDC and BLDC

Kconfig fixed at board level
2024-07-27 12:08:51 +08:00
Huang Qi
d7f82fb14c Correct comment blocks
Fix wrong comment blocks in the following files:
- arch/arm/src/stm32f0l0g0/stm32_pwr.c
- include/nuttx/mtd/nand_config.h

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-27 03:11:39 +08:00
Huang Qi
3b70bf7ff0 samv7: Fix comment block in sam_rstc.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-27 03:11:39 +08:00
raiden00pl
e75c19ce58 arch/arm/{nrf53|nrf91}: enable fpu if CONFIG_ARCH_FPU=y
enable fpu if CONFIG_ARCH_FPU=y, the previous condition depended on CONFIG_ARCH_HAVE_FPU=y
2024-07-26 23:46:34 +08:00
buxiasen
f5021021ae up_backtrace: fix maybe backtrace the exiting thread
when the thread to backtrace is exiting, get_tcb and up_backtrace in
different critical section may cause try to dump invalid pointer, have
to ensure the nxsched_get_tcb and up_backtrace inside same critical
section procedure.

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-07-26 12:03:43 +08:00
Yanfeng Liu
9e59b0b43b riscv/qemu: guard u16550 uses
This guards the uses for u16550 serial initialization, just in case
that no u16550 is configured.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-26 12:01:29 +08:00
Henry Rovner
049a6da098 risc-v/bl808: Add timer driver
This change implements a driver for the hardware timer blocks on the BL808, as well as a config with the timer example enabled.
2024-07-24 10:06:54 +08:00
nuttxs
a83a569652 arch/xtensa/esp32s3: Add qspi/spi_slave/lcd DMA request return value.
Optimize DMA initialization for duplicate calls.
2024-07-23 22:48:24 +08:00
Yanfeng Liu
3b9a346fe7 riscv/nsbi: unblock up_udelay
This fixes the always zero time in NuttSBI case as the `error` field
contains the correct timestamp. This in turn also fixes the block of
`up_udelay()` which further leads to boot failure of `canmv230:master`
config.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-22 23:46:43 +08:00
Inochi Amaoto
0ddcbe62ec arch/risc-v: does not clear IPI address in S mode
According to the riscv-aclint doc, writing 0 to SSWI address
has no effect. Remove this unnecessary write for S mode.

Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-18 22:59:29 +08:00
YAMAMOTO Takashi
985d395b02 esp32s3_textheap.c: fix a build error w/o CONFIG_ESP32S3_SPIRAM 2024-07-18 16:42:52 +08:00
nuttxs
de3737cd90 arch/xtensa/esp32s3: Deinitialize ESP32-S3 QSPI GDMA engine.
Correctly releasing channels after using QSPI is crucial
to prevent issues caused by multiple requests that may lead
to DMA channel resource conflicts.
2024-07-18 13:41:04 +08:00
chao an
7780cfc5a6 tricore/cmake: add support of cmake build for tricore
Toolchain Upstream:
https://github.com/EEESlab/tricore-gcc-toolchain-11.3.0

CMake command:
$ cmake -B build -DBOARD_CONFIG=tc397/nsh -GNinja
$ cmake --build build

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-18 13:40:49 +08:00
Inochi Amaoto
000b0ec4a1 arch/risc-v: make common up_allocate_heap weak symbol
The common `up_allocate_heap` is a strong symbol, which leads to
error when building with CONFIG_DEBUG_LINK_WHOLE_ARCHIVE. Make
`up_allocate_heap` weak function to mitigate this problem.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-18 13:40:37 +08:00
Lup Yuen Lee
bdf60d7966 risc-v/bl808, sg2000: Configure MMU to cache Kernel Text, Data and Heap (T-Head C906)
This PR configures the BL808 and SG2000 MMU (inside T-Head C906) to cache the the Kernel Text, Data and Heap.  We set the MMU Flags (Shareable, Bufferable and Cacheable) as explained in this article: https://lupyuen.github.io/articles/plic3#appendix-mmu-caching-for-t-head-c906

This PR fixes the Slow Memory Access for NuttX Kernel in BL808 and SG2000: https://github.com/apache/nuttx/issues/12696

In the next PR, we will fix the Slow Memory Access for NuttX Apps, by caching the User Text and Data.

arch/risc-v/src/bl808/bl808_mm_init.c: Added MMU Flags (Shareable, Bufferable and Cacheable) for BL808 Kernel Text, Data and Heap

arch/risc-v/src/sg2000/sg2000_mm_init.c: Added MMU Flags (Shareable, Bufferable and Cacheable) for SG2000 Kernel Text, Data and Heap
2024-07-17 12:08:04 -03:00
Yanfeng Liu
d6c67c555f riscv/trap: fix sp restore logic
This fixes stack pointer restore logic to avoid parent stack corruption
by forked child in PROTECTED build.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-17 17:20:00 +08:00
Yanfeng Liu
08c4686f47 riscv/fork: fix tp for PROTECTED
This fixes `tp` value of forked child in PROTECTED build to support
vfork. Why? the optimized `dispatch_syscall` requires `tp` to hold
the task TCB since commit e6973c764c.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-17 17:20:00 +08:00
chao an
4db1169e6f arch/tricore: fix compiler warning on GCC toolchain
tc3xx/tc3xx_timerisr.c: In function ‘up_timer_initialize’:
tc3xx/tc3xx_timerisr.c:58:39: warning: passing argument 1 of ‘tricore_systimer_initialize’ discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
   58 |   lower = tricore_systimer_initialize(&MODULE_STM0, 192, SCU_FREQUENCY);
In file included from tc3xx/tc3xx_timerisr.c:31:
nuttx/arch/tricore/src/common/tricore_internal.h:252:35: note: expected ‘void *’ but argument is of type ‘volatile Ifx_STM *’ {aka ‘volatile struct _Ifx_STM *’}
  252 | tricore_systimer_initialize(void *tbase, int irq, uint64_t freq);
      |                             ~~~~~~^~~~~
tc3xx/tc3xx_serial.c:177:16: warning: initialization discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
  177 |   .uartbase  = &MODULE_ASCLIN0,
      |                ^
tc3xx/tc3xx_serial.c:178:16: warning: initialization discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
  178 |   .pins      = &g_uart0_pins,
      |                ^
common/tricore_trapcall.c: In function ‘tricore_trapcall’:
common/tricore_trapcall.c:66:3: warning: passing argument 4 of ‘_assert’ discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
   66 |   PANIC_WITH_REGS("Trap", CURRENT_REGS);
      |   ^~~~~~~~~~~~~~~
In file included from common/tricore_trapcall.c:29:
nuttx/include/assert.h:189:45: note: expected ‘void *’ but argument is of type ‘volatile uintptr_t *’ {aka ‘volatile long unsigned int *’}
  189 |              FAR const char *msg, FAR void *regs);

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-17 17:18:02 +08:00
chao an
8e20b8d862 arch/tricore: add support of tricore gcc toolchain
Toolchain Upstream:
https://github.com/EEESlab/tricore-gcc-toolchain-11.3.0

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-17 17:18:02 +08:00
zouboan
b817db86b8 zynq-mpsoc: add support for mio/emio 2024-07-16 18:50:52 -03:00
chao an
bc7791e079 arch/tricore: synchronize instruction/data following MTCR/MFCR
Some barrier are necessary to avoid compiler optimizations

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-16 21:13:13 +08:00
GC2020
8f243d3eb7 /rp2040 Rename the RP2040-specific PWM_MULTICHAN definition to avoid confusion with the global PWM_MULTICHAN 2024-07-16 20:09:10 +08:00
shizhenghui
fea727a050 arch/sim/Makefile: add openh264 & x264 include path
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
347864152d sim codec: add dependence to Kconfig
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
61f79757f7 v4l2m2m/sim encoder: move hostencoder to x264encoder
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
7248ba0293 sim decoder: update CMakeLists.txt
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
3675cfe585 v4l2m2m/sim decoder: rename hostdecoder to openh264dec
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
Eren Terzioglu
0df037855a esp32[c3]: Add mcuboot build script for esp32c3-legacy 2024-07-16 10:30:56 +08:00
Eren Terzioglu
a9082e0882 esp32[s2]: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
Eren Terzioglu
c9f5ae5fa4 esp32[s3]: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
Eren Terzioglu
024e95875a esp32: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
Eren Terzioglu
553b1f5f5e esp32[c3|c6|h2]: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
adriendesp
baf52268cc arch/xmc4: Added pwm driver 2024-07-15 16:14:55 -03:00
Peter van der Perk
622b6d234a s32k1xx: FlexIO I2C master driver 2024-07-15 10:06:55 -03:00
Raman Gopalan
ef271b8fe2 at32uc3a0: Initial work for SimpleMachines' Mizar32-A 2024-07-15 20:46:41 +08:00
Yanfeng Liu
8bdc975abb riscv/cmake: fix Toolchain.cmake issue
This fixes the following issue when configuring canmv230:master
with Ubuntu stock toolchain and cmake 3.22:

```
CMake Error at .../arch/risc-v/src/cmake/Toolchain.cmake:218 (if):
  if given arguments:
    "STREQUAL" "GNU_RVG"
  Unknown arguments specified
```

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-15 19:41:03 +08:00
hujun5
a4fece3450 spin_lock: inline spin_lock
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
2024-07-15 02:29:30 +08:00
zouboan
ae8ce535f3 arm64/arm64_boot.c: Fix exception caused by accesses to ICC_SRE_EL3 when GICv3 was not implemented 2024-07-15 02:26:40 +08:00
Huang Qi
e047ab9c70 riscv: Initial support for debug trigger module
Implement up_debugpoint_add/up_debugpoint_remove for riscv.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-14 20:32:19 +08:00
Eren Terzioglu
c15c0d1a78 esp32[h2]: Add MCUBoot support 2024-07-14 11:38:29 +08:00
Eren Terzioglu
0f0c258fa2 esp32[c6]: Add MCUBoot support 2024-07-14 11:38:29 +08:00
zouboan
ea532cb11a arch/arm64: add initial support for ZYNQ MPSOC
arch/arm64: add initial support for ZYNQ MPSOC

arch/arm64: add initial support for ZYNQ MPSOC
2024-07-13 20:51:39 -03:00
Yanfeng Liu
211e2cd8b9 riscv/k230: revise canmv230:pnsh
This revises canm230:pnsh in a few ways:

- adjusting linker scripts structure,
- asserting PMP setting results,
- adjusting configs for both k230d and k230 devices.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-13 07:21:22 -03:00
Michal Lenc
5c48944e0b samv7: fix compile warning in PWM and UART drivers
The following warnings is fixed:

chip/sam_pwm.c:961:12: warning: unused variable 'regval' [-Wunused-variable]
  961 |   uint32_t regval;

chip/sam_serial.c: In function 'sam_dma_txavailable':
chip/sam_serial.c:2264:7: warning: unused variable 'rv' [-Wunused-variable]
 2264 |   int rv;

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-07-13 11:37:06 +02:00
simbit18
f12c4e05cc Fix Kconfig style
Remove spaces from Kconfig files
Add TABs
Replace help => ---help---
Remove extra TABs
2024-07-12 06:37:59 +08:00
chao an
d4024c8388 arch/armv8-r: update g_running_tasks before context switch
fix invalid running_task() in assertion logic

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-12 00:39:37 +08:00
simbit18
2f8560e838 tools/ci: enable avr32dev1 build
removed in the tools/ci/testlist/other.dat file the entries
 -avr32dev1:nsh
 -avr32dev1:ostest

avr32_bringup.c
Fix  Error: ./avr32_bringup.c:54:4: error: #warning "Not Implemented"

comment out directive '#warning'
/* #warning "Not Implemented" */

avr_doirq.c

fix avr32/avr_doirq.c:117: error: assignment discards qualifiers from pointer target type
  regs = g_current_regs; -> regs = (uint32_t *)g_current_regs;
2024-07-12 00:39:21 +08:00
chao an
95a9facf3a arch/armv8-r: new config to set SPIs Configuration to edge-triggered
Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-11 15:35:41 +08:00
Henry Rovner
091372069c risc-v/bl808: Add SPI driver
This commit implements a driver for SPI0 and SPI1 on the BL808 and introduces an accompanying example configuration.
2024-07-11 11:32:24 +08:00
chao an
b191153cdc arch/armv8-r: fix typos in config
replace ARMV7R to ARMV8R

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-10 18:41:13 -03:00
Michal Lenc
a91d40e0e8 samv7: fix CAN FD configuration
Larger RX/TX buffers might be required for both FD and FD_BSW modes.
Default bit timing values are also changed since the original ones
did not provide correct results for default SAMv7 board clock selection
(150 MHz clock frequency). The current values provide correct bit timing
with sample point as close to 87.5 %.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-07-10 11:33:03 -03:00
Michal Lenc
e16ee4dba3 can: enhance bit timing ioctl to set both nominal and data bit timing
This adds field type to canioc_bittiming_s structure that allows
to set/obtain bit timing for both CAN CC and CAN FD.
CANIOC_GET_BITTIMING is now bidirectional: user specifies type field
and gets other fields from the controller.

The commit also updates current CAN FD capable controllers using the
ioctl. The type is not checked for classical CAN only controllers
and nominal bit timing is returned regardless of type value.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-07-10 11:33:03 -03:00
Eero Nurkkala
48cf91a7be arm64/imx9: ccm: add default clk init
This adds enablers for setting various clocks to some default
values. Also, this provides helpers to grant nonsecure access
to a number of clocks. Bootloader may utilize these to make
the system boot in a deterministic manner.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-07-09 21:14:11 -03:00
xuxingliang
848eca04ca arch/arm64: allow to use custom idle
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-07-09 19:36:48 +08:00
xuxingliang
94387630c9 arch/arm64: remove not used idle trace
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-07-09 19:36:48 +08:00
Lwazi Dube
b881868f19 arch/arm/sama5: Fix typos in ohci driver comments. 2024-07-09 09:20:13 +08:00
Huang Qi
d0210c1174 riscv_tcbinfo: Fix register ordering for PC
X0 is always 0 but still should be transfered to the client, but it don't existed in thread context, use any other register for it, and its value will be omitted by gdb client.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-08 21:13:25 +08:00
chao an
cef9addbbb sim/cmake: enable garbage collection of unused input sections
enable --gc-sections for linker
enable -ffunction-sections -fdata-sections for compiler

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-06 11:31:40 +08:00
chao an
9915b80e30 arch/sim: add custom data section support
The link script of NuttX Simulator is generated through compilation
options. This PR will support configure special data sections in
kconfig to meet the support of 3rd party applications.

we need to follow the syntax of linker script. In 3rd-party applications, some data will be labeled as section:

| a.c:
| struct task_s a __attribute__((section(".data.custom.taska")));
| b.c:
| struct task_s b __attribute__((section(".data.custom.taskb")));

Data of the same type struct can be placed in a fixed location to reduce the overhead caused by searching:

|   .data           :
|   {
|     _custom_data_table_start = .;
|     KEEP(*(.data.custom.*))
|     _custom_data_table_end = .;
|   }

Such section declare can be configured via Kconfig in the PR:

| CONFIG_SIM_CUSTOM_DATA_SECTION=" .data : { _custom_data_table_start = .; KEEP(*(.data.custom.*)) _custom_data_table_end = .; } "

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-05 16:45:36 -03:00
Jukka Laitinen
b008653ac0 arch/arm64/src/imx9/imx9_lowputc.c: Fix an arithmetic sign error in divisor calculation
In the algorithm there is a subtraction (int - unsigned), which results (potentially overflowed)
unsigned.

Passing this to macro ABS and the assigning to int doesn't work ( unsigned is always >= 0 ).

Fix this by replacing (dangerous) ABS macro with stdlib's standard "int abs(int)"
and change the substraction to (int - int).

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-07-05 21:47:07 +08:00
Jukka Laitinen
31644ec0f5 arch/arm64/src/imx9: Add an mtd driver for NOR flash on FlexSPI interface
This is an initial FlexSPI SPI NOR MTD driver for IMX9

This supprts M25P SPI NOR on FlexSPI for now, and can later be extended to other
SPINOR devices if needed. The following configurations are needed to use this driver:
  CONFIG_IMX9_FLEXSPI_NOR=y
  CONFIG_MTD_M25P=y

In addition, board initialization logic needs to call the imx9_flexspi_nor_initialize
to receive a pointer to the mtd device.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Co-authored-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-07-05 21:46:47 +08:00
Jouni Ukkonen
31a6a4f5d0 imx9: Add flexspi support, ported from imxrt
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-07-05 21:46:47 +08:00
Henry Rovner
a83e7ced77 ox64: Add adc example config 2024-07-05 13:17:02 +08:00