The FAT was not coherent. Resulting in a write failed
with errno:28 No space left on device.
It is unclear how the memory is acesses prior to the DMA
completion. But this restructuring ensures the data
is coherent.
This issue was not detected on the stm32h7
Gregory Nutt has submitted the SGA
Haltian Ltd has submitted the SGA
Uros Platise has submitted the ICLA
as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
When enable DEBUG_TCBINFO config, a global struct will
provide, then debuggers can aware nuttx task infomation.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
This commit adds microcontroller support for Analog Front End driver to
samv7 MCUs. Only software trigger via IOCTL is currently supported,
averaging can be set by configuration option CONFIG_SAMV7_AFECn_RES.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Strongly-Ordered requires aligned access unless
caching is enabled.
Normal memory
Accesses to normal memory region are idempotent...
- unaligned accesses can be supported
With CONFIG_ARMV7M_DCACHE the cache maintenance operation
are not present. Or if CONFIG_ARMV7M_DCACHE_WRITETHROUGH
is on then buffering operations are no-ops.
This change enables MPU_RASR_C and MPU_RASR_B if
CONFIG_ARMV7M_DCACHE is only set.
if CONFIG_ARMV7M_DCACHE_WRITETHROUGH is set then only
MPU_RASR_C is enabled.
N.B When caching is disalbed unaligned access may cause hard faults
so add -mno-unaligned-access
It is always safe to enable Buffering in FLASH to achive unaligned
access leniency, as it is not written to.
the SDIO clock is not enabled when the bus goes to the idle state, that, in turn, breaks
IRQ delivering mechanism over DAT[1]/IRQ SDIO line to the host.
This reverts commit d9a5b92c1a306a70df52d50a02a80dc8ef20bf0d.
Revert "arch/arm: Remove -march and -mtune"
This reverts commit b8e99cf12f3a287311a2d341f285c71a5da3e4d4.
This commit adds new files that support functionality of QSPI driver in
SPI Master Mode. This functionality is included in new files sam_qspi_spi.x
to avoid too much mess in the source code. QSPI in SPI mode can be turn
on by config option SAMV7_QSPI_SPI_MODE.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
When NuttX is booted from a foreign (non NuttX)
bootloader. There as a possibility that the
bootloader configured the MPU, in an
incompatible way for the NuttX memory usage.
The option to reset the MPU before it is initialized
may not succeed if the bss and data initialization
code violated the previous MPU configurations.
Added herein are ARM_MPU_RESET and
ARM_MPU_EARLY_RESET. The former can be used
If the system is capable of booting and running
NuttX MPU configuration code without an MPU
violation. The latter is used if the system can
not run the bss and data initialization code.
These are options so that a NuttX may be configured to
not clobber a bootloader MPU configuration in a system
that is architected to share the MPU configuration task.
This commit adds header file imxrt_adc_etc.h for external ADC trigger
module. This contains only definitions of ADC_ETC registers and separate
bits, implementation of ADC_ETC driver is yet to be done.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
If we repeatedly call up_cpu_pause and up_cpu_resume, there would be
cases where the next call to up_cpu_pause happens while the other CPU is
still responding to the previous resume request. In this case the
DEBUGASSERT will trigger. We should allow the first CPU to wait until the
other CPU has finished responding to the resume request.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
