sergiotarxz/nuttx
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18333 Commits

Author SHA1 Message Date
Eero Nurkkala
e57f3f7a3a mpfs: emmcsd: provide proper internal emmc settings 
So far the SD-card functionality has been tested with
the driver. Now, also the internal eMMC has been tested
working with this patch. This patch applies IOMUX and
clock settings that have been tested working with the
internal eMMC in the Polarfire Icicle kit.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-10-21 22:41:08 -05:00
Eero Nurkkala
c34b9620db mpfs: clockconfig: add clock initialiation sequence 
Add clock initialization sequence especially for systems
containing no bootloader.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-10-21 22:40:26 -05:00
Eero Nurkkala
bc72ccdf6a mpfs: Kconfig/Make: add DDR support flag 
This adds the proper flag for introducing the DDR
support. Also call the mpfs_ddr_init() at the
proper location.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-10-21 22:40:26 -05:00
Eero Nurkkala
3b330089d5 mpfs: ddr: add DDR training 
This adds DDR training. The training has a small chance of failing,
and then the training is restarted.

DDR training cannot be done meaningfully while the software is
in DDR. If the system is intended to run from eNVM, like a
bootloader, the linker script should be tuned to utilize the envm
region as follows:

  envm (rx)   : ORIGIN = 0x20220100, LENGTH = 128K - 256
  l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k

256 bytes are reserved for the system; The fixed block may be
installed from the 'hart-software-services' -repository:
https://github.com/polarfire-soc/hart-software-services.git

For example, the 256-byte image: hss-envm-wrapper-bm1-dummySbic.bin
may be prepended on the nuttx bootloader image in the following
manner:

 cat hss-envm-wrapper-bm1-dummySbic.bin > nuttx_bootloader.bin
 cat nuttx.bin >> nuttx_bootloader.bin
 riscv64-unknown-elf-objcopy -I binary -O ihex --change-section-lma
  *+0x20220000 nuttx_bootloader.bin flashable_image.hex

This provides an image 'flashable_image.hex' that may be flashed on
the eNVM region via Microsemi Libero tool.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-10-21 22:40:26 -05:00
Jukka Laitinen
c5b11f42b6 mpfs_head.S: Support for booting on different harts and from eNVM 
- Fix the FPU enabling code
- If booting from eNVM, all harts start booting. With CONFIG_MPFS_BOOTLOADER,
  one can allow just one hart booting and rest are stuck in wfi.
- Check that mtvec is actually updated before continuing the boot
- Create 5 IRQ stacks, one for each hart

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-10-21 22:40:26 -05:00
Jukka Laitinen
37761c293d mpfs_head.S: Fixes for booting on different harts 
- Jump to mpfs_start with mhartid in a0 as the comment says
- Don't invalidate mmu tlb on e51 (it doesn't have mmu)
- Fix FPU initialization flags on e54 (it fires IRQ5 and crashes)

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-10-21 22:40:26 -05:00
Jukka Laitinen
e5843db282 mpfs: Add configuration flags to configure NuttX booting on single hart 
The bootloader hart also configures the needed clocks and peripherals.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-10-21 22:40:26 -05:00
Eero Nurkkala
d909b0f635 mpfs: hardware/memorymap: add more base addresses 
Add a number of missing base addresses.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-10-21 22:40:26 -05:00
chao.an
bd7cb1aae5 sim/bluetooth: remove the WIRELESS_BLUETOOTH depends if native host is in use 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-10-21 11:24:46 -05:00
Abdelatif Guettouche
018aa8eb8d esp32c3_serial.c: Remove the stub implementations of the early serial 
functions as they are only called when the configuration is enabled.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-20 10:22:10 -03:00
Xiang Xiao
1efc9fbac6 sim/rptun: Trigger the callback only the sequnece number change 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-10-20 10:21:54 -03:00
Abdelatif Guettouche
c83c1071cc esp32c3_bignum.c & esp32c3_sha.c: Fix some trivial nxstyle complaints. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
e424241d09 arch/risc-v/esp32c3: Remove the bignum test from the driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
91cb9dafaf arch/risc-v/esp32c3: Remove the RSA test from the driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
652d77efd2 arch/risc-v/esp32c3: Remove the SHA test from the driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
5d1c01aea7 arch/risc-v/esp32c3: Remove the AES test from the driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
8288a04a0b arch/xtensa/esp32: Remove the AES test from the driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
zhuyanlin
b5134565fa arch:xtens:mpu: modify acc and memtype to uint32_t 
The uint8_t and uint16_t will overflow in MPU_ENTRY_AR marco.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-10-19 00:24:31 -05:00
Xiang Xiao
91398e73eb arch/xtensa/Kconfig: add quotes in source to clean warnings from setconfig 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-10-19 00:33:51 +02:00
Michal Lenc
3e1ce5f770 arch/arm/src/imxrt/hardware: add header file for ADC_ETC module 
This commit adds header file imxrt_adc_etc.h for external ADC trigger
module. This contains only definitions of ADC_ETC registers and separate
bits, implementation of ADC_ETC driver is yet to be done.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-10-17 16:50:59 +02:00
Abdelatif Guettouche
7549de49b4 arch/*_cpupause:Allow a spin before taking the g_cpu_wait spinlock. 
If we repeatedly call up_cpu_pause and up_cpu_resume, there would be
cases where the next call to up_cpu_pause happens while the other CPU is
still responding to the previous resume request. In this case the
DEBUGASSERT will trigger. We should allow the first CPU to wait until the
other CPU has finished responding to the resume request.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-17 21:10:23 +09:00
Abdelatif Guettouche
7b43d11435 esp32_spiflash.c: Allocate only one variable to hold the cache state in 
single CPU mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
f54a929001 esp32_spiflash.c: Keep the index of the other CPU between SPI Flash 
operations.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
eeb68bda3d xtensa_testset.c: Simplify the test-set function and remove some old 
comments.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
dfe1637864 esp32_spiflash.c: Pause the other CPU during flash operation. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
f2c2323642 esp32_intercpu_interrupt.c: Force the functions to internal SRAM. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
d2bc011719 arch/xtensa/xtensa_cpupause.c: Allow a spin before taking the g_cpu_wait 
spinlock.

If we repeatedly call up_cpu_pause and up_cpu_resume, there would be
cases where the next call to up_cpu_pause happens while the other CPU is
still responding to the previous resume request.  In this case the
DEBUGASSERT will trigger.  We should allow the first CPU to wait until the
other CPU has finished responding to the resume request.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 09:46:23 -07:00
Abdelatif Guettouche
591c1563b8 esp32_oneshot_lowerhalf.c: Use the same alignment as the rest of the 
code base.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
9e1d2ca95e esp32_rt_timer.c: Group static variables into a struct and fix naming 
standard

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
0dff3f2762 esp32_wifi_adapter.c: Use the specified spin lock when 
enabling/disabling interrupts.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
a50d673df7 esp32_wifi_adapter.c: Don't hold another spinlock when calling 
enter_critical_section, we already hold the global IRQ spinlock.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
11216257cf esp32_rt_timer.c: Don't nest calls to spin_lock_irqsave with a device 
specific spinlock, this will lead to deadlocks.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
e847c61801 esp32_wifi_adapter.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
32f7471f9e esp32_wlan.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
4ae1285124 esp32_emac.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
e64390d5e9 esp32_rt_timer.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
c61009c2cf esp32/esp32_spi_slave.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
2273684cb1 esp32/esp32_spi.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
0123243f9a esp32/esp32_i2c.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
0af9a49d9c esp32/esp32_oneshot_lowerhalf.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
698af43d78 esp32/esp32_freerun.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
04bd27400a xtensa/esp32_wdt_lowerhalf.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
19a096cdfe arch/xtensa/esp32_tim_lowerhalf.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Gustavo Henrique Nihei
ff705586bb xtensa/esp32s2: Provide SPI Flash parameters to MCUboot build 
Also unify bootloader config creation to reduce duplication.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei
4d5e0f8fe1 xtensa/esp32: Provide SPI Flash parameters to MCUboot build 
Also unify bootloader config creation to reduce duplication.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei
99ac065d0a risc-v/esp32c3: Provide SPI Flash parameters to MCUboot build 
Also unify bootloader config creation to reduce duplication.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei
cc78541966 risc-v/esp32c3: Add esp-nuttx-bootloader folder to gitignore list 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei
ae25ebce4c risc-v/esp32c3: Fix wrong arch in the path to chip folder 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Abdelatif Guettouche
a7d8d9dd98 esp32s2/tie.h: Run the file though detab. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-14 07:39:54 -03:00
Abdelatif Guettouche
6d246eb18f esp32s2/tie.h: The old tie.h file was from ESP32 which doesn't apply to 
ESP32-S2.  This commit gets the correct S2 tie.h file

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-14 07:39:54 -03:00
Abdelatif Guettouche
217fd97fd3 xtensa_coproc.S: Correctly save/restore coprocessor0 state. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-14 07:39:54 -03:00
Abdelatif Guettouche
7420f245bc xtensa_context.S: Save and restore SCOMPARE1 when necessary. 
SCOMPARE1 is used by some atomic instructions and need to be preserved
during a context switch.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-14 06:32:17 -03:00
Alin Jerpelea
b9986ca016 arch: arm: update licenses to Apache 
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-10-11 10:13:07 +02:00
jsun
c58fddb915 Open ble controller adaptation code 
N/A

Signed-off-by: jsun <jsun@bouffalolab.com>
 2021-10-08 02:30:27 -07:00
Jari van Ewijk
e4752fbaee S32K1xx arch: Add (optional) support for SPI native/hardware chip select 2021-10-05 06:07:18 -07:00
Gustavo Henrique Nihei
47e804b167 risc-v/esp32c3: Make BLE adapter code compliant to nxstyle 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-05 08:45:40 -03:00
Alan C. Assis
867c6d0636 esp32: Add initial support to Bluetooth Low Energy 
Co-authored-by: saramonteiro <saramonteirosouza44@gmail.com>
Co-authored-by: Gustavo Henrique Nihei <gustavonihei@gmail.com>
 2021-10-04 15:10:37 -03:00
Abdelatif Guettouche
d22b4ec539 espxx_rng.c: Add "/" at the beginning of paths for consistency. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
Abdelatif Guettouche
c811cefa2d esp32c3_rng.c: Remove unused functions. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
Abdelatif Guettouche
5c6a30c00b esp32_rng.c: Remove the initialization guard. The init function is 
called only once during startup.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
Abdelatif Guettouche
6a262c5203 esp32_rng.c: Remove unused functions. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
liuhuan
ee6138e9ba power: Open CONFIG_PM compilation failed 
include debug.h

Signed-off-by: liuhuan <liuhuan16@xiaomi.com>
 2021-09-30 07:16:07 -07:00
Jari van Ewijk
cf6dcbc6fd S32K1XX arch: gpioread may also be used for output pins 2021-09-30 04:30:50 -07:00
Xiang Xiao
77bc1d1bdf power/battery: Move the enumurate to the common place 
so the userspace program can handle the different battery driver equally

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-30 14:58:42 +09:00
P.Brier
b9d1fcb232 Use ethernet MAC programmed in imxrt OCOTP MAC0/MAC1 (teemsy board has this) 2021-09-29 20:45:14 -07:00
Sara Souza
8a142f474e xtensa/esp32-s2/rttimer: Disable alarm before setting a new value and enabling it 2021-09-28 21:02:57 -03:00
Sara Souza
33f2d46bff risc-v/esp32-c3/rttimer: Disable alarm before setting a new value and enabling it 2021-09-28 21:02:57 -03:00
Alin Jerpelea
15a37c5a5a arch: Omni Hoverboards: update licenses to Apache 
Gregory Nutt has submitted the SGA
Omni Hoverboards has submitted the SGA
David Sidrane has submitted the ICLA
Mateusz Szafoni has submitted the ICLA
Sebastien Lorquet has submitted the ICLA
Paul Alexander Patience has submitted the ICLA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-09-28 04:37:38 -07:00
Gustavo Henrique Nihei
20341e6f17 risc-v/esp32c3: Enable support for "make bootloader" target 
This enables the provisioning of the bootloader binaries through the
build system.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-27 18:22:29 -07:00
Gustavo Henrique Nihei
3c63cb522c risc-v/esp32c3: Enable booting from MCUboot bootloader 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-27 18:22:29 -07:00
Gustavo Henrique Nihei
a5f9e29d78 xtensa/esp32s2: Enable support for "make bootloader" target 
This enables the provisioning of the bootloader binaries through the
build system.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-27 18:21:53 -07:00
Gustavo Henrique Nihei
800678ca78 xtensa/esp32s2: Enable booting from MCUboot bootloader 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-27 18:21:53 -07:00
Jari van Ewijk
62c41a723b s32k1xx_eeeprom.c - fix compiler warnings 2021-09-27 06:02:59 -07:00
Abdelatif Guettouche
5336704c77 esp32_start.c: Initialize the SPI RAM before enabling its cache. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-27 05:13:51 -07:00
Gustavo Henrique Nihei
c23986ec63 xtensa/esp32: Select ARCH_HAVE_BOOTLOADER for ESP32 chips 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-24 10:48:19 -07:00
Gustavo Henrique Nihei
86518bdf25 tools: Trigger clean_bootloader on distclean for supported chips 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-24 10:48:19 -07:00
Gustavo Henrique Nihei
4ac3044cc3 xtensa/esp32: Enable build system to download or build bins from source 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-23 20:52:25 -07:00
Sara Souza
9c2c5d3919 risc-v/esp32-c3: fix pid initiatialization on esp32c3_rt_timer.c 
pid variable was initialized to -EINVAL to prevent rt_timer_deinit
from delete an invalid kthread. But priv->pid was being overwritten in the
rt_timer_init, so in case of failure to create a kthread, it would
call rt_timer_deinit with a non expected initialization value.
 2021-09-23 19:01:27 -07:00
Sara Souza
d0e7d7b77f risc-v/esp32-c3: Remove _s of non static variables from esp32c3_rt_timer.c 2021-09-23 19:01:27 -07:00
Abdelatif Guettouche
f2f2040c44 esp32_spiram/psram/himem: Add and fix the files' sections. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-23 02:49:11 -07:00
Abdelatif Guettouche
3d8a6fb676 esp32_spiram.c: Remove esp_himem_reserved_area_size from esp32_spiram.c 
file.  This function is already defined in esp_himem and is used only
when that file is built.  We don't need another weak function.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-23 02:49:11 -07:00
Abdelatif Guettouche
2834d2a46f esp32_spiflash.c/esp32_spiram.c: Remove some unused macros/functions/variables. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-23 02:49:11 -07:00
Xiang Xiao
47c60b2de8 arch/arm: Remove -march and -mtune 
since -mcpu is enough https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58869

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-23 11:48:11 +02:00
Jari van Ewijk
bbb2f1f8c7 S32K1XX: Add LPI2C slave support 2021-09-22 19:36:34 -07:00
Sara Souza
962059f843 xtensa/esp32-s2: Adds oneshot device driver support 2021-09-22 22:53:54 -03:00
David Sidrane
6d299ce802 stm32h7:DMA_TRBUFF is DMA_SCR_TRBUFF 2021-09-22 22:48:10 -03:00
Sara Souza
fba6fa2dc1 xtensa/esp32-s2: Adds support to rt_timer and systimer to ESP32-S2. 2021-09-22 17:18:24 -03:00
Sara Souza
2cd4f4af79 xtensa/esp32-s2: Adds freerun timer wrapper 2021-09-22 09:38:10 -03:00
Gustavo Henrique Nihei
e651ef0969 arch/risc-v: Remove CODE qualifier for RISC-V-specific files 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei
06f4ee850a arch/risc-v: Remove FAR qualifier for RISC-V-specific files 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei
e9c17c9332 risc-v/rv32m1: Fix wrong position for ++ operator on serial driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei
eca1f86294 arch/xtensa: Remove CODE qualifier for Xtensa-specific files 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei
e13dd7dab9 arch/xtensa: Remove FAR qualifier for Xtensa-specific files 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei
58f87ef443 xtensa/esp32: Fix wrong position for ++ operator on I2C driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Jari van Ewijk
e5f17f6604 S32K1XX: Add FlexIO registers 2021-09-22 03:15:42 -07:00
David Sidrane
a9ff808dd1 stm32xx:sdmmc/sdio remove redundant GPIO config 
The stm32_gpiosetevent calls stm32_configgpio. So
   the pin is infact restored to the SDMMC/SDIO D0.

   The seconday init, dropped interrupts in a debug
   build with HW stack checking on after the GPIO glich
   fixes and that was how it was detected.
 2021-09-21 18:25:16 -07:00
David Sidrane
a8d5f21f81 stm32H7:Etablish device before enabling outputs 
This prevents gliches on changing to an output mode.
   If not the ALT mux can be selecting a IP block that
   is drving the line to say 0. Then the output is connected
   to that source, then swithced to the correct source.
 2021-09-21 18:25:16 -07:00
David Sidrane
5e19ebb818 stm32F7:Etablish device before enabling outputs 
This prevents gliches on changing to an output mode.
   If not the ALT mux can be selecting a IP block that
   is drving the line to say 0. Then the output is connected
   to that source, then swithced to the correct source.
 2021-09-21 18:25:16 -07:00
David Sidrane
d5e306e6f3 stm32:Etablish device before enabling outputs 
This prevents gliches on changing to an output mode.
   If not the ALT mux can be selecting a IP block that
   is drving the line to say 0. Then the output is connected
   to that source, then swithced to the correct source. This
   produced a 430 nS glich on a F4 @168 Mhz. It was a enough
   to corrupt an I2C device with a bus monitor.
 2021-09-21 18:25:16 -07:00
Sara Souza
fc12d6888b risc-v/esp32-c3: Group static variables into a struct and prevent an unitialized thread to be deleted 2021-09-21 15:45:59 +02:00
P.Brier
35824b449a Added CONFIG_ETH0_PHY_DP83825I to imxrt_enet: make driver compile for teensy 4.1 (link detection needs more checks to see if it works as expected) 2021-09-21 10:27:33 -03:00
P.Brier
f9850cf433 Fixed imxrt flexcan driver compilation error due to incorrect scope of variable 2021-09-21 10:00:12 -03:00
Abdelatif Guettouche
9f4d7e4767 xtensa_dumpstate.c: Fix the name of the TCB variable when dumping the 
backtrace.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-21 09:22:28 -03:00
Eero Nurkkala
812f504c16 mpfs: emmcsd: add Kconfig/Makefile and board files 
Add necessary Kconfig, Make.defs, Makefile and board
file changes.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-09-18 12:18:09 -03:00
Eero Nurkkala
772432e7c3 mpfs: add emmcsd driver 
This adds the emmcsd driver for the Polarfire Icicle kit.
The driver has been tested with several SD-cards, such as:

 - Kingston 32 GB SDS2 Canvas Select Plus
 - Kingston MicroSD Canvas Select Plus
 - Sandisk Extreme PRO 32 GB
 - Transcend 8 GB MicroSD

The internal eMMC hasn't been tested comprehensively.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-09-18 12:18:09 -03:00
Xiang Xiao
75a119ac1c arch: Compile up_puts in all Make.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-18 07:33:44 -03:00
Xiang Xiao
71c61b11d9 arch/riscv: Rename riscv_puts to up_puts 
since it's a common API defined in include/nuttx/arch.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-18 07:33:44 -03:00
Xiang Xiao
0625f9888c arch/z16: Implement up_puts function 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-18 07:33:44 -03:00
Xiang Xiao
5b75df2203 arch/sim: Implement up_puts function 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-18 07:33:44 -03:00
jsun
f4b6bb281c Update bl602 MTU_SIZE and TX_BUF_SIZE 
N/A

Signed-off-by: jsun <jsun@bouffalolab.com>
 2021-09-17 22:11:30 -05:00
jsun
d489392d08 Add bl602 os adapter layer 
N/A

Signed-off-by: jsun <jsun@bouffalolab.com>
 2021-09-17 22:11:30 -05:00
Abdelatif Guettouche
15b68b9abb esp32_spiflash.c: Correctly disable APP's CPU cache. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-17 17:43:45 -03:00
Masayuki Ishikawa
204d88bcf3 arch: cxd56xx: Replace the critical section with spinlock in cxd56_serial.c 
Summary:
- This commit replaces the critical section with spinlock in cxd56_serial.c

Impact:
- None

Testing:
- Tested with spresense:rndis_smp, spresense:rndis
  and spresense:rndis_wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-09-16 21:56:40 -05:00
Alin Jerpelea
48f92e6f1d author: Bill Gatliff : update licenses to Apache 
Gregory Nutt has submitted the SGA
Bill Gatliff has submitted the ICLA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-09-16 21:56:08 -05:00
Gustavo Henrique Nihei
52cea558af risc-v/esp32c3: Make the semaphore timeout on I2C configurable 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-16 14:07:26 -03:00
Gustavo Henrique Nihei
b33ccd01cf xtensa/esp32: Make the semaphore timeout on I2C configurable 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-16 14:07:26 -03:00
zhuyanlin
7947e50f06 xtensa:backtrace: flush to stack when in interrupt 
The registers may be in window during interrupt.
Flush window stack to stack first.
And fix warning in build.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-16 10:53:35 -05:00
Peter Bee
2a8b076b38 risc-v/esp32c3: fix pwm driver bug 
Wrong offset sign and pwm multichan fix

Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
 2021-09-16 08:38:49 -03:00
zhuyanlin
cdb441cc3f arch:xtensa:dumpstate: use sched_dumpstack 
Use sched_dumpstack instead. The backtrace infomation like

xtensa_user_panic: User Exception: EXCCAUSE=0009 task: hello
xtensa_registerdump:    PC: 202b32b8    PS: 00060030
xtensa_registerdump:    A0: a02acb87    A1: 20998d10    A2: ffffaaaa    A3: 12345678
xtensa_registerdump:    A4: a02ba26c    A5: 209949c0    A6: 20990994    A7: 00000258
xtensa_registerdump:    A8: a02b32af    A9: 20998cb0   A10: 0000000f   A11: 209949a0
xtensa_registerdump:   A12: a02be95c   A13: 20994980   A14: 00000003   A15: 209949d0
xtensa_registerdump:   SAR: 00000000 CAUSE: 00000009 VADDR: ffffaaaa
xtensa_registerdump:  LBEG: 00000000  LEND: 00000000  LCNT: 00000000
xtensa_registerdump:  TMP0: 202b1512  TMP1: 20998af0
sched_dumpstack: [BackTrace| 3|0]:  0x202acbae 0x202b232e 0x202b1912 0x202b19f5 0x202b24f1 0x202b152f    0x40023 0x202b32b0
sched_dumpstack: [BackTrace| 3|1]:  0x202acb87 0x202a86a4

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-16 10:32:38 +08:00
zhuyanlin
6e0f84dc88 arch:xtensa: add up_backtrace support 
Up_backtrace can be backtrace from task or interrupt.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-16 10:32:38 +08:00
zhuyanlin
3acdbef60d xtensa:arch: force up_getsp to inline 
Up_getsp may be not inline in gcc, thus get the sp
is up_getsp function's sp, not the caller function.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-16 10:32:38 +08:00
zhuyanlin
583dce0b98 arch:xtensa: remove WSBITS/WBBITS to core.h 
Remove WSBITS/WBBITS macro to core.h as may be used by
arch common code.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-16 10:32:38 +08:00
Cis van Mierlo
b316c679c1 S32K1xx: added PM support 2021-09-15 12:20:23 -03:00
SPRESENSE
74df4b70b3 drivers: video: Rearchitect video driver 
Rearchitect video driver:
- Define two video I/F(struct imgsensor_ops_s and struct imgdata_ops_s),
  and support them.
- CISIF driver supports new video I/F struct imgdata_ops_s.
- ISX012 driver supports new video I/F struct imgsensor_ops_s.
- Move ISX012 driver to general driver directory.
 2021-09-15 07:06:35 +02:00
Juha Niskanen
4487b352c0 arch/arm/src/stm32l4: fix baud rate setting for LPUART 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2021-09-14 08:57:25 -07:00
Harri Luhtala
7e3c813346 arch/arm/src/stm32l4: LPUART1 support 
Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>
 2021-09-14 08:57:25 -07:00
Abdelatif Guettouche
198c30eaa6 stm32*7/stm32_serial.c: Don't fake an interrupt when interrupts are not 
suppressed.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-14 22:50:43 +08:00
chao.an
ba9b829372 arch/arm: correct the function name from arm_getsp() to up_getsp() 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-09-14 22:48:47 +08:00
Cis van Mierlo
91c945a2e8 s32k1xx: added way to get the reset cause in proc fs 2021-09-14 08:35:41 +02:00
Sara Souza
83a9c2b24b xtensa/irq.h: Fixes the routine that clears the processor interrupt 2021-09-13 17:01:49 -03:00
Alin Jerpelea
bb54ed4227 author: OffCode Ltd : update licenses to Apache 
OffCode Ltd has submitted the SGA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-09-13 22:43:36 +08:00
zhuyanlin
8e6fbe700e xtensa:dcache_clean: use DCACHE_LINZESIZE instead of DCACHE_SIZE 
Clean_dcache use DCACHE_LINZESIZE instead of DCACHE_SIZE in addr loop

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-13 14:38:57 +08:00
Xiang Xiao
850367d5bb arch/arm: Add ARCH_CORTEXM55 Kconfig for cortex-m55 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-12 09:09:42 -03:00
Jukka Laitinen
3654db3517 mpfs: Modify IRQ handling to support also HART0 on PF 
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-09-11 23:33:01 +08:00
Janne Rosberg
8b560e7894 mpfs/i2c: fix bus initialize for i2c1 2021-09-11 23:33:01 +08:00
Janne Rosberg
1e3919e55a mpfs/corepwm: remove wrong header include 2021-09-11 23:33:01 +08:00
Janne Rosberg
7db3456824 risc-v/mpfs: serial: add termios support and init device clocks 2021-09-11 23:33:01 +08:00
Janne Rosberg
aa057e25f2 mpfs/i2c: adapt to sysreg define changes 2021-09-11 23:33:01 +08:00
Janne Rosberg
dc54ba924e mpfs/spi: adapt to sysreg define changes 2021-09-11 23:33:01 +08:00
Janne Rosberg
3e6b19dfc5 risc-v/mpfs: add more sysreg defines and fix clock and reset defines 2021-09-11 23:33:01 +08:00
Abdelatif Guettouche
31aa616bf2 stm32_serial.c: Don't fake a TX interrupt when interrupts are not 
suppressed.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-10 15:15:44 -07:00
David Sidrane
41e1696b27 stm32f4:USB otgdev Ensure proper EP state 
Repeated automated sercon, serdis on VBUS proved to fail
   for CDCACM DATA IN (device Serial TX). The root cause was
   that the EP was left active after disconnect. This resulted
   in the first serial write falling to kick-off the EP IN request.
   That should restart the EP ISR.
 2021-09-09 14:27:41 -04:00
David Sidrane
e488f0047d stm32h7:USB otgdev Ensure proper EP state 
Repeated automated sercon, serdis on VBUS proved to fail
   for CDCACM DATA IN (device Serial TX). The root cause was
   that the EP was left active after disconnect. This resulted
   in the first serial write falling to kick-off the EP IN request.
   That should restart the EP ISR.
 2021-09-09 14:27:41 -04:00
David Sidrane
21f049b43a stm32f7:USB otgdev Ensure proper EP state 
Repeated automated sercon, serdis on VBUS proved to fail
   for CDCACM DATA IN (device Serial TX). The root cause was
   that the EP was left active after disconnect. This resulted
   in the first serial write falling to kick-off the EP IN request.
   That should restart the EP ISR.
 2021-09-09 14:27:41 -04:00
Sara Souza
acf18bd82d risc-v/esp32-c3: refactor the Wi-Fi board logic. 
This commit moves the Wi-Fi initialization to
Wi-Fi specific file and to spiflash initialization.

It also reserves one partition for Wi-Fi use and for general use,
and makes it possible to me mounted by several FS.
 2021-09-09 20:14:04 +08:00
Sara Souza
11068fad1b risc-v/esp32-c3: Enable the allocation of multiple MTD SPI Flash partitions 2021-09-09 20:14:04 +08:00
Harri Luhtala
d4e59b7e8d arch/arm/src/stm32l4: add control for Vddio2 independent I/Os supply valid 
Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>
 2021-09-09 08:26:08 -03:00
Abdelatif Guettouche
4ef859924b esp32_serial.c: Release the spinlock before calling uart_xmitchars, this 
functions will call esp32_txint again which leads to deadlock since
esp32_txint has already locked the spinlock.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-09 19:35:17 +09:00
Abdelatif Guettouche
b5bb1fb8a3 esp32_serial.c: Replace critical section by a device specific spin lock. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-09 19:35:17 +09:00
Abdelatif Guettouche
f47d28c108 esp32_serial.c: Don't fake an interrupt when interrupts are not 
suppressed.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-08 09:27:08 -03:00