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12486 Commits

Author SHA1 Message Date
Gregory Nutt
ed8377af72 Xtensa: More interrupt-related logic 2016-10-20 14:28:14 -06:00
Gregory Nutt
9e1600b7d3 Xtensa: Trivial interrupt-related changes 2016-10-20 12:56:35 -06:00
Gregory Nutt
30c4a41332 Fix a few compile-related issues 2016-10-20 11:33:53 -06:00
Gregory Nutt
5c3afd088e Xtensa: A little more interrupt handling logic 2016-10-20 11:44:14 -06:00
Gregory Nutt
d75fb34b62 Xtensa: Fix some xtensa_context.S assemble issues 2016-10-20 08:58:33 -06:00
Gregory Nutt
11af1fc24c Xtensa: Separate context save/restore from coprocessor functions. Making to changes to interrupt handling to support NuttX. 2016-10-20 08:51:15 -06:00
Gregory Nutt
d2d60a59bf ESP32: Refresh configuration; fix some compile issues 2016-10-19 13:58:50 -06:00
Gregory Nutt
dda7f4cd75 Trivial corrections to spacing 2016-10-19 14:01:51 -06:00
Gregory Nutt
d1562a18e6 Add vectors for interrupt levels 2-6 2016-10-19 13:58:51 -06:00
Gregory Nutt
291c49afc3 Xtensa/ESP32: Move some ESP32-specific macros from xtensa_macros.h to chip_macros.h 2016-10-19 11:28:42 -06:00
Gregory Nutt
48fb97e7b5 More of the same cloned typo 2016-10-19 10:11:45 -06:00
Gregory Nutt
31d5acc8a7 Forgot to add a file before the last commit 2016-10-19 10:06:07 -06:00
Gregory Nutt
5d56172f82 Merged in w8jcik/nuttx (pull request #152) 
add tim8 to stm32f103v pinmap
 2016-10-19 16:03:34 +00:00
Gregory Nutt
29c3acdc4e Add xtensa_testset.c 2016-10-19 09:58:12 -06:00
Gregory Nutt
fb7b545637 Merge remote-tracking branch 'origin/master' into esp32 2016-10-19 09:17:07 -06:00
Gregory Nutt
841e1aa77f Fix a cloned typo 2016-10-19 09:14:21 -06:00
Maciej Wójcik
c719a32a40 add tim8 to stm32f103v pinmap 2016-10-19 16:34:07 +02:00
Gregory Nutt
20fc02569f Merged in david_s5/nuttx/upstream_kinetis_to_greg (pull request #151) 
Upstream kinetis to greg
 2016-10-18 22:12:08 +00:00
David Sidrane
c3543cf402 Kinetis:BugFix:i2c driver offset swapped for value in kinetis_i2c_putreg 2016-10-18 12:00:01 -10:00
David Sidrane
b29b2874fe Kinetis Allow CONFIG_ARMV7M_CMNVECTOR, CONFIG_STACK_COLORATION, CONFIG_ARCH_FPU 2016-10-18 12:00:01 -10:00
David Sidrane
bce382da52 Kinetis Support ARMV7 Common Vector and FPU 2016-10-18 12:00:01 -10:00
David Sidrane
4de46c848d Broke out DMA to use the modern Nuttx chip inclusion - still STUBS 2016-10-18 12:00:01 -10:00
David Sidrane
42ac6ecebd Kinetis broke out SPI to kinetis/kinetis_spi.h 2016-10-18 12:00:01 -10:00
David Sidrane
70d5c7753e Kinetis - Added missing headers 2016-10-18 12:00:01 -10:00
Gregory Nutt
8c606c4878 ESP32: Add more missing infrastructure 2016-10-18 13:18:59 -06:00
Gregory Nutt
6357970c5f Xtensa: Fix some compilation issues 2016-10-18 12:38:57 -06:00
Gregory Nutt
503a2472e7 Xtensa: Add assertion logic 2016-10-18 12:42:57 -06:00
Gregory Nutt
054a1a8231 ESP32 Core: Refresh configuration 2016-10-18 09:41:16 -06:00
Gregory Nutt
ac97a81fb0 ESP32 core: Add linker script 2016-10-18 09:43:56 -06:00
Gregory Nutt
c5d14f9496 Xtensa: A few changes to get esp32_start.c to compile 2016-10-17 10:45:21 -06:00
Gregory Nutt
51fc3de40b Xtensa: Add CPU1 start logic 2016-10-17 09:13:12 -06:00
Gregory Nutt
c1334048c5 Xtensa: Add initial CPU0 start-up logic 2016-10-17 08:15:36 -06:00
Gregory Nutt
0591b67c15 Xtensa: A few fixes for clean compile 2016-10-16 10:27:52 -06:00
Gregory Nutt
e7d791dd95 XTensa: Add an initial implementation of up_initialstate. Need to think through co-processor support. 2016-10-16 10:36:03 -06:00
Gregory Nutt
29ccdf350a Merge remote-tracking branch 'origin/master' into esp32 2016-10-16 09:53:03 -06:00
Ken Pettit
201a32cf8c Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it. 2016-10-16 09:47:07 -06:00
Gregory Nutt
8c3c78f24a Xtensa: Fix register usage in up_strackframe 2016-10-16 09:26:33 -06:00
Gregory Nutt
a8662c70db Xtensa: Keep task state in TCB (unless you want to redesign signal handling). Lots of cosmetic clean-up. 2016-10-16 07:57:16 -06:00
Gregory Nutt
275120a6d1 XTENSA: Add some context switching definitions (incomplete); ESP32: Add some dummy LED definitions 2016-10-15 14:57:06 -06:00
Gregory Nutt
eada2bf8d8 XTENSA: Add function prototypes 2016-10-15 12:23:36 -06:00
Gregory Nutt
8ffbf6d95e XTENSA: Hook xtensa_irq.S into build 2016-10-15 11:46:21 -06:00
Gregory Nutt
4621784617 Add xtensa.h (which is call up_internal.h in other architectures. 2016-10-15 11:45:15 -06:00
Gregory Nutt
0a0278a3ca XTENSA: Add and architecture Makefile. Initial verion is just the MIPS Makefile. 2016-10-15 11:36:48 -06:00
Gregory Nutt
43d08db1a0 XTENSA: Add some interrupt controls 2016-10-15 11:29:50 -06:00
Gregory Nutt
0be3d12ba0 ESP32: Add option for interrupt support 2016-10-15 10:11:35 -06:00
Gregory Nutt
30598c005f Cosmetic changes from review of last PR 2016-10-15 08:56:11 -06:00
Gregory Nutt
6f35ced002 ESP32: Add peripheral interrupt IRQ numbers 2016-10-15 08:39:15 -06:00
David Sidrane
909ea5e8ef F4 Support versampling by 8 2016-10-15 03:56:07 -10:00
Gregory Nutt
5b46ce4889 Cosmetic changes from review of last PR 2016-10-14 17:39:21 -06:00
Gregory Nutt
f2ebb6d2a0 Merged in neilh20/anuttx/pr_K64_uid (pull request #147) 
Add Kinetis freedom-k64f uid
 2016-10-14 23:29:19 +00:00
Gregory Nutt
e3ead1db69 Xtensa: Add an initial guess at the form of struct xcpcontext 2016-10-14 13:17:48 -06:00
Gregory Nutt
ad6856c931 Trivial stylistic changes from review of last PR 2016-10-14 11:12:49 -06:00
Sebastien Lorquet
fb1f424e12 Support Complementary PWM outputs on STM32L4 2016-10-14 18:06:11 +02:00
Sebastien Lorquet
f7e0a36f55 Multiple stm32l4 timer fixes: 
- too many parentheses when calculating max chan count (???)
- channel 4 does not have a complementary output
 2016-10-14 12:50:45 +02:00
neilh10
6dca9a4390 Add UID Unique ID 2016-10-13 19:50:35 -07:00
neilh10
64b020f1a8 Add UID Unique ID 2016-10-13 19:42:39 -07:00
Gregory Nutt
c078573677 Add some .gitignore files 2016-10-13 16:29:50 -06:00
Gregory Nutt
04940840b6 ESP32 Core: Correct tool-related prefix and path 2016-10-13 14:48:29 -06:00
Gregory Nutt
43c46fd34c ESP32 Core: Add a dummy Toolchain.defs. Fix some cloning errors left in the NSH configuration. 2016-10-13 14:40:43 -06:00
Gregory Nutt
25331aeb63 ESP32 Core: Add an NSH configuration for build testing 2016-10-13 14:37:28 -06:00
Gregory Nutt
52b1ca8747 configs/esp32-core: Add basic directory to support the ESP32 Core board V2 2016-10-12 15:27:34 -06:00
Gregory Nutt
852330876b arch/xtensa: A little more ESP32 configuration logic 2016-10-12 14:50:28 -06:00
Gregory Nutt
55523f5771 arch/xtensa: Add a few basic XTENSA/LX6 files. Not yet enough to do anything with 2016-10-12 13:11:05 -06:00
Gregory Nutt
0bc19a63bb Merged in david_s5/nuttx-5/david_s5/kinetish-edited-online-with-bitbucket-1476115086140 (pull request #144) 
kinetis.h edited online with Bitbucket
 2016-10-10 10:04:04 -06:00
David Sidrane
0476c43748 kinetis.h edited online with Bitbucket 2016-10-10 15:58:21 +00:00
David Sidrane
4703a23171 kinetis.h edited online with Bitbucket 2016-10-10 15:56:02 +00:00
Lok Tep
9e3479555d usb set value typo 2016-10-07 15:47:30 +02:00
Lok Tep
fd92f01f55 exact values for i2c clock 2016-10-07 15:12:46 +02:00
Lok Tep
a2e4c0e898 i2s rcc typo fix 2016-10-07 15:12:34 +02:00
Jens Gräf
1d3abd17cc dma2d: fix an error in up_dma2dcreatelayer where an invalid pointer was returned when a certain underlying function failed. 2016-10-07 13:42:24 +02:00
Gregory Nutt
d61239e38f stm32_modifycr2 should be available on all platforms is DMA is enabled. 2016-10-06 08:50:52 -06:00
David Sidrane
d4a8585d6f Fixed L4 USB Driver by avoiding SETUPDONE and EPOUT_SETUP 2016-10-04 16:52:12 -10:00
David Sidrane
a416b304a3 Code Cleanup and conform to upstrem debug config 2016-10-04 16:51:47 -10:00
David Sidrane
e54a0cd3d0 Header cleanup 2016-10-04 16:51:32 -10:00
Sebastien Lorquet
9dcecd4b15 Add support for qencoders on various nucleo boards 2016-10-03 16:07:20 +02:00
Gregory Nutt
06c70129ed STM32L4: Remove dependencies on STM32 F3 from Kconfig 2016-10-02 16:05:13 -06:00
Sebastien Lorquet
d5ef349d9a Add support for quadrature encoders on STM32L4 2016-10-02 23:26:16 +02:00
Lok Tep
33cea5038f memory corruption, typo addr-value 2016-10-01 19:38:43 +02:00
Neil Hancock
ef475eb6a9 STM32 Ethernet: Correct typo in conditional logic 2016-10-01 07:32:41 -06:00
Vytautas Lukenskas
fd1de92016 There are some small problems in LPC43xx RS485 mode configuration. In particular: 1. UART0,2,3 do not have DTR pins (different from UART1), so, Kconfig needs to be adjusted. 2. lpc43_uart.c in RS485 mode only configures DIR pin, but doesn't enable pin output for UART0,2,3. 3. should be option to reverse DIR control pin output polarity. 4. lpc43xx/chip/lpc43_uart.h doesn't have USART3 definitions. NOTE: I didn't modified and didn't tested USART1, as it has different hardware. From Vytautas Lukenskas. 2016-09-30 08:51:49 -06:00
Lok Tep
1cbd7a0e59 CONFIG_ARCH_IRQPRIO check 2016-09-30 16:00:18 +02:00
Lok Tep
7d7354f961 merge 2016-09-27 16:05:57 +02:00
Young
7f32019a76 Add a new ioctl command (set MAXPOS) for tiva QEI 2016-09-26 18:10:06 +08:00
Gregory Nutt
2da3da7fd6 Costmetic changes from review of last commit 2016-09-25 17:24:39 -06:00
Mateusz Szafoni
9742757f26 Remove GPIO_ETH_RMII_TX_CLK. TX_CLK is not present in RMII 2016-09-22 10:05:45 +02:00
Gregory Nutt
d2e03daeb1 Fix some strange spacing apparently introduced by tools/indent.sh 2016-09-21 16:06:05 -06:00
Gregory Nutt
54eee5b303 Review of PR 135 2016-09-21 09:36:39 -06:00
Young
cf99e50b7a Add QEI lower-half driver impl. for Tiva series chip 2016-09-21 17:08:31 +08:00
Gregory Nutt
1c20376e39 SAM GPIO: Apply Wolfgang's change for SAM3/4 to SAMA5 and SAMV7 2016-09-20 15:33:31 -06:00
Wolfgang Reißnegger
3f22b63321 SAM3/4: Fix GPIO pull-up/down code. 
Enabling the pull-down resistor while the pull-up resistor is still enabled
is not possible. In this case, the write of PIO_PPDER for the relevant I/O
line is discarded. Likewise, enabling the pull-up resistor while the
pull-down resistor is still enabled is not possible. In this case, the
write of PIO_PUER for the relevant I/O line is discarded.
 2016-09-20 13:32:04 -07:00
Gregory Nutt
ed22c93d7a Tiva Ethernet: Needs support for CONFIG_NET_MULTIBUFFER=y 2016-09-20 13:02:24 -06:00
Gregory Nutt
4dc3521743 All SAM Ethernet Drivers: Add support so that the drivers can be built with CONFIG_NET_MULTIBUFFER=y 2016-09-20 08:56:36 -06:00
Gregory Nutt
7f1a88e243 Pierre's assertion-avoidance change should also be applied to STM32 F7 and L4 2016-09-15 08:41:49 -06:00
Pierre-noel Bouteville
829de7d5bd Set USB address to avoid a failed assertion 2016-09-15 08:36:45 -06:00
Jim Wylder
5d73f114b5 STM32L4: Add support for USART3-USART5 
For STM32L4 parts, the higher number USART ports supported
varies.  Add the HAVE_USARTx definitions to the configuration
to allow enabling the higher numbered USART ports.

Signed-off-by: Jim Wylder <jwylder@motorola.com>
 2016-09-14 15:20:18 -05:00
Sebastien Lorquet
50dd745e23 restore stm32l4 name 2016-09-07 14:17:38 +02:00
Sebastien Lorquet
87d2f86968 Register renames to allow stm32l4 usb device compilation 2016-09-05 08:50:09 +02:00
David Sidrane
944902a24d F7 Usb Fix for FIFO loosing first word 2016-09-02 07:14:16 -10:00
David Sidrane
81ba54b650 Using uinfo 2016-09-02 03:50:26 -10:00
Sebastien Lorquet
e4a713477a Apply stm32 fix to stm32l4 2016-08-31 13:12:49 +02:00
Gregory Nutt
bef7f5be23 STM32 F7: Remove duplicate call to pkt_input from Ethernet driver. 2016-08-30 08:04:18 -06:00
Gregory Nutt
9c3bade7b4 net/tcp: tcp_ipvX_bind() not actually using the ported selected with port==0. Also removes duplicate call to pkt_input(). Issues noted by Pascal Speck. 2016-08-30 07:59:57 -06:00
David Sidrane
f2809d52d3 stm32_otgfsdev.c edited online with Bitbucket 
dup SOF removed as noted by Sébastien Lorquet
 2016-08-26 17:20:38 +00:00
David Sidrane
87f4a8033a BugFix:Lost first word from FIFO 
1) Do not overwrite Reserved Bits in GINTSTS (per ref manual)*
    2) Acknowledge all pending int on entry to ISR that are Only rc_w1*
    3) Do not disable RXFVL*
    4) Loop until RXFVL is cleared*
    5) Only clear the NAK on the endpoint on the OTGFS_GRXSTSD_PKTSTS_SETUPDONE to
       not loose the first WORD of FIFO all the data  (Bug Fix)

Changed marked *are just driver clean up and ensure ints are not lost.
The bug fix is #5

Test case open putty and observer the Set/Get LineCoding
Without this fix #5 the Get will not match the Set, and
infact the data might be skewed by 4 bytes, that are lost
from the FIFO if the OTGFS_DOEPCTL0_CNAK bit is set in the
OTGFS_GRXSTSD_PKTSTS_SETUPRECVD as opposed to the OTGFS_GRXSTSD_PKTSTS_SETUPDONE

Set Line Coding DATA1: 4B | 00 c2 01 00 00 00 08 | c8 1B
Get Line Coding DATA1: 4B | .. .. .. .. 00 00 08   c8 .. 00 00 07 | 7a 72
 2016-08-25 06:51:52 -10:00
Gregory Nutt
4ebace37a9 Fix typos in LPC43 serial driver. Found by Vytautas Lukenskas 2016-08-24 10:34:56 -06:00
Aleksandr Vyhovanec
6bc952a2cc STM32: Add IAR-style STM32F1xx vectors. Tested on STM32F103RB and STM32F107RC. 2016-08-24 10:10:33 -06:00
Gregory Nutt
300361539a sched/sched_cpuload_oneshot: Use the oneshot timer with optional entropy to measuer cPU load if so configured. 2016-08-20 12:47:07 -06:00
Gregory Nutt
ae37c9859f Cosmetic changes from review of PR 120 2016-08-19 06:32:28 -06:00
Michał Łyszczek
0f175039ad Fix compilation warnings for stm32 eth with certain configs 2016-08-19 09:18:18 +02:00
Gregory Nutt
c0074fd6b8 Merged in mlyszczek/nuttx/stm32butterfly2_board (pull request #118) 
add stm32butterfly2 development board
 2016-08-18 11:14:10 -06:00
Alan Carvalho de Assis
a3e1bdde14 STM32 SPI: Fix STM32F3XXX SPI driver to read 8-bit correctly. 2016-08-18 08:38:49 -06:00
Gregory Nutt
3c58e8e9b4 SAMA5: Add oneshot max_delay method 2016-08-18 08:11:40 -06:00
Gregory Nutt
d369eeec95 Remove a misleading comment 2016-08-18 07:13:04 -06:00
Gregory Nutt
01ae660c6c Merged in K-man23/nuttx/stm32_adc_fix (pull request #117) 
Change stm32 adc dma callback to send channel number instead of index
 2016-08-17 14:05:37 -06:00
Konstantin Berezenko
9b3bbc0f09 Change stm32 adc dma callback to send channel number instead of index 2016-08-17 13:02:36 -07:00
Gregory Nutt
319ad528cd Revert "sam_tc_clockselect() reworked to calculate frequency error using smallest possible divisor minimizing the frequency error rather than largest possible divisor which maximized the error." 
This reverts commit 5d5851a5cd.
 2016-08-17 12:34:54 -06:00
Michał Łyszczek
a05d9c18da Add connectivity line stm32 to be able to compile SYSCFG, add definitions for 
usb clock divs
 2016-08-17 20:11:15 +02:00
Konstantin Berezenko
42ee88fe89 STM32F411 and STM32F446 map i2c2_sda_4 to different alternate function numbers 2016-08-17 11:01:44 -07:00
Piotr Mienkowski
5d5851a5cd sam_tc_clockselect() reworked to calculate frequency error using smallest possible divisor minimizing the frequency error rather than largest possible divisor which maximized the error. 2016-08-17 09:51:54 -06:00
Gregory Nutt
17e5da96ea SAMV7: DAC1 not available GMAC is enabled 2016-08-17 07:14:59 -06:00
Gregory Nutt
e57891b41f Kinetis I2C: Review and extend I2C register definitions for K40 and K60 2016-08-16 12:17:23 -06:00
Gregory Nutt
a337494221 Kinetis I2C: Remove literal hex register values. Replace with symbolic definitions from kinetis_i2c.h 2016-08-16 11:44:04 -06:00
Gregory Nutt
7f4488dc80 Review I2C register definitions and add support for the K64 2016-08-16 10:18:52 -06:00
Gregory Nutt
a3b061e54f Kinetis: Add support for I2C2 2016-08-16 10:02:28 -06:00
Gregory Nutt
be83e73957 Kinetis I2C: Add comments, DEBUGASSERTions, and some I2C debug output. 2016-08-16 08:42:30 -06:00
Gregory Nutt
32c1189f51 Re-order some fields so that the structure packs better and so is smaller. 2016-08-16 08:20:55 -06:00
Gregory Nutt
f40bb14495 Kinetis: Add support for I2C1 2016-08-16 07:21:03 -06:00
Gregory Nutt
b2be0be3a6 Simulated oneshot max_delay() method should not return a failure. 2016-08-15 11:43:55 -06:00
Gregory Nutt
3f48392974 Add defaults in SAMV7 configuration for all DAC settings 2016-08-15 10:22:12 -06:00
Gregory Nutt
e53118ffc2 SAMV7 DAC configuration needs some conditional logic 2016-08-15 08:55:11 -06:00
Gregory Nutt
c367e4985f Add configuration logic for the SAMV7 DAC module 2016-08-15 08:21:46 -06:00
Piotr Mienkowski
053aea552f Add support for SAMV7 DACC module 2016-08-15 08:00:36 -06:00
Gregory Nutt
f84780f36e Changes from review of PR 114 2016-08-14 13:38:47 -06:00
Gregory Nutt
2b32869b49 Merged in v01d/nuttx/kinetis-i2c-norestart (pull request #114) 
support NORESTART on kinetis i2c
 2016-08-14 13:27:39 -06:00
v01d
239c56f3b9 support NORESTART 2016-08-14 16:25:18 -03:00
Gregory Nutt
014b8268cc Minor stylistic corrections 2016-08-14 10:14:28 -06:00
Gregory Nutt
45e71a140a Fix some alignment and long line issues 2016-08-13 18:04:09 -06:00
Gregory Nutt
3023724cf2 Changes from review of PR 113 2016-08-13 17:32:35 -06:00
Gregory Nutt
8315b051ca Merged in v01d/nuttx/kinetis_i2c (pull request #113) 
I2C and RTC support for Kinetis
 2016-08-13 16:54:14 -06:00
Gregory Nutt
8052dc4955 STM32 SPI: nbits should be unsigned. Valid range is 4-16 for F3 and L4. 8 or 16 for others. 2016-08-13 16:01:50 -06:00
v01d
5a97def131 kinetis k20 i2c fixed 2016-08-13 18:48:45 -03:00
Gregory Nutt
1a10518dae Update ChangeLog 2016-08-13 12:03:12 -06:00
Gregory Nutt
eed5e41626 Add some comments 2016-08-13 10:24:40 -06:00
Gregory Nutt
172761163b STM32F3 SPI: Cannot write 16-bit value to DR register because of how the F3 implements data packing. 2016-08-13 10:11:23 -06:00
Gregory Nutt
51fcd89b98 Add and fix some SPI debug output 2016-08-13 08:31:37 -06:00
Gregory Nutt
42202c6365 STM32 and STM32L4: Enabling DMA loses other bits in CR2 2016-08-13 08:01:41 -06:00
Gregory Nutt
efc9f674d2 Trivial changes to comments and spacing 2016-08-13 07:50:54 -06:00
Alan Carvalho de Assis
805cb5c752 STM32F3 SPI: Fix a typo 2016-08-13 07:23:48 -06:00
Gregory Nutt
da5563c0e7 STM32: Add conditional logic for STM32F37xx 2016-08-13 06:43:13 -06:00
Gregory Nutt
10f90a1738 STM32 F3: Fix more SPI issues 2016-08-12 19:00:34 -06:00
Gregory Nutt
3383a25c38 Some logic missing from last commit 2016-08-12 18:40:25 -06:00
Gregory Nutt
afb02b56d4 STM32F3 SPI: Fix the number of bit setting for the F3. It works differently than for other parts. 2016-08-12 18:32:37 -06:00
Gregory Nutt
ab16ad7530 Fix some bugs in the oneshot driver logic 2016-08-12 14:19:11 -06:00
Gregory Nutt
046acf6b54 Add a simulated oneshot lowerhalf driver 2016-08-12 13:14:03 -06:00
Gregory Nutt
b4e8876b09 Correct some spacing 2016-08-12 12:41:49 -06:00
Gregory Nutt
82b86cdcf3 oneshot interface: max_delay method should return time in a standard struct timespec form. 2016-08-12 11:33:10 -06:00
Gregory Nutt
89135c55e4 drivers/timer: Add an upper-half, oneshot timer character driver. 2016-08-12 10:40:07 -06:00
Gregory Nutt
61b0ac06bf Missed a dependency in last set of commits 2016-08-11 17:20:12 -06:00
Gregory Nutt
1965e25da4 STM32L4: Add oneshot lower half driver. 2016-08-11 17:14:41 -06:00
Gregory Nutt
a5a776e223 SAM4CM: Add option to support oneshot timer without free-running timer. Add oneshot lower half driver. 2016-08-11 17:04:19 -06:00
Gregory Nutt
fa6866b046 SAMA5: Add option to support oneshot timer without free-running timer. Add oneshot lower half driver. 2016-08-11 16:47:17 -06:00
Gregory Nutt
b4d4a74059 SAMV7: Add option to support oneshot timer without free-running timer. Add oneshot lower half driver. 2016-08-11 16:27:01 -06:00
Gregory Nutt
d0ce5b1d1e Cosmetic changes to comments and function prototypes 2016-08-11 15:15:37 -06:00
Gregory Nutt
fb349508fd STM32 oneshot lower-half: Missed some data initialization. 2016-08-11 14:57:17 -06:00
Gregory Nutt
eb3a565153 STM32: Add oneshot lower half to build system. Fix some build problems. 2016-08-11 14:53:39 -06:00
Gregory Nutt
1bb93021df STM32: Add a experimental oneshot, lower-half driver for STM32 2016-08-11 14:07:43 -06:00
Gregory Nutt
0e35bad987 Update some comments 2016-08-11 10:12:04 -06:00
Gregory Nutt
accbccd78a Merged in mlyszczek/nuttx/stm32f1connline_pllfix (pull request #111) 
Fix bad pllmul values for stm32f1xx connectivity line.
 2016-08-11 06:44:19 -06:00
Michał Łyszczek
81df56086a Fix bad pllmul values for stm32f1xx connectivity line. 
stm32f1xx connectivity line supports only x4, x5, x6, x7, x8, x9 and x6.5 values
 2016-08-11 10:49:57 +02:00
Young
e30a3b780c Fix two bugs of tiva pwm lower-half driver impl. 2016-08-10 13:25:43 +08:00
Gregory Nutt
7823a1680e Update a comment 2016-08-09 17:08:03 -06:00
Gregory Nutt
698d6d1294 SAM3/4: Extend clocking logic to enable clocking on ports D-F 2016-08-09 17:05:11 -06:00
Gregory Nutt
0918dd98ab Merged in gnagflow/nuttx (pull request #109) 
SAM3/4 GPIO: Enable peripheral clock for GPIO port when GPIO is configured as input.
 2016-08-09 16:40:48 -06:00
Gregory Nutt
fdcf0f7e5f Correct some comments 2016-08-09 15:15:21 -06:00
Wolfgang Reissnegger
cf35bb0b18 SAM3/4 GPIO: Enable peripheral clock for GPIO port when GPIO is configured as input. 
The value of a GPIO input is only sampled when the peripheral clock for
the port controller the GPIO resides in is enabled. Therefore we need
to enable the clock even when polling a GPIO.
 2016-08-09 13:23:05 -07:00
Gregory Nutt
b5b7a21bb6 Make reference count a uin16_t and save a couple of bytes. 2016-08-09 13:54:57 -06:00
Gregory Nutt
8b5833f7fe A consequence of Max's change to the logic to enable access to the backup domain is that every call to enabledbkp(true) must be followed by a matching call to enablebkp(false). There was one cse in both RTCC drivers where that may not always be true. 2016-08-09 11:33:47 -06:00
v01d
f715e9b787 RTC working, I2C in progress 2016-08-09 14:01:27 -03:00
Gregory Nutt
5d91b8cabb With last change, stm32_pwr_enablebkp() no longer returns a value 2016-08-09 07:50:31 -06:00
Max Neklyudov
1e3ccbac12 Make stm32_pwr_enablebkp thread safe 2016-08-09 07:36:13 -06:00
Alan Carvalho de Assis
8499f42bf9 Add STM32F37XX DMA channel configuration 2016-08-08 13:29:53 -06:00
Alan Carvalho de Assis
fcf1ae7e05 stm32f37xx: Fix SYSCFG_EXTICR_PORTE defined twice 2016-08-08 12:59:29 -06:00
Alan Carvalho de Assis
834f058573 I'm using NuttX on STM32F373 and saw the config was missing SPI2 and 
SPI3, see datasheet:
www.st.com/resource/en/datasheet/stm32f373cc.pdf

I searched for other members of STM32F37XX family and they also have 3 SPIs:
http://www.st.com/content/st_com/en/search.html#q=STM32F37-t=keywords-page=1
 2016-08-08 12:25:15 -06:00
Gregory Nutt
caea59b340 SPI bit order: Add configuration setting to indicate if an architecture-specif SPI implementation does or does not support LSB bit order. 2016-08-08 12:21:20 -06:00
Gregory Nutt
6df28bc74e Make bit-order SPI H/W feature configurable for better error detection 2016-08-08 11:54:13 -06:00
Gregory Nutt
c3cfd37791 Fix cloned variable error in all SPI drivers 2016-08-08 11:04:01 -06:00
Gregory Nutt
2ae3953f9e STM32/EFM32: If any hardware feature other and LSBFIRST is selected, return -ENOSYS. 2016-08-08 10:37:28 -06:00
Gregory Nutt
7d4cb73bd6 STM32 and EFM32 SPI drivers adopted an incompatible conventions somewhere along the line. The set the number of bits to negative when calling SPI_SETBITS which had the magical side-effect of setting LSB first order of bit transmission. This is not only a hokey way to pass control information but is supported by no other SPI drivers. 
This change three things:  (1) It adds HWFEAT_LSBFIRST as a new H/W feature.  (2) It changes the implementations of SPI_SETBITS in the STM32 and EFM32 derivers so that negated bit numbers are simply errors and it adds the SPI_HWFEATURES method that can set the LSB bit order, and (3) It changes all calls with negative number of bits from all drivers: The number of bits is now always positive and SPI_HWFEATUREs is called with HWFEAT_LSBFIRST to set the bit order.
 2016-08-08 08:28:13 -06:00
v01d
d483f7939f I2C0 support for kinetis/teensy-3.x (to be tested) 2016-08-06 22:23:59 -03:00
Gregory Nutt
56f2454c86 Fix names of pre-processor variables used in header file idempotence 2016-08-06 18:48:45 -06:00
Gregory Nutt
d41008e220 Update some header commments 2016-08-06 18:16:31 -06:00
Gregory Nutt
2b23d4b0e7 Correct some comments 2016-08-06 16:25:02 -06:00
Gregory Nutt
5aaba42b0d Update Renesas REAMDE files 2016-08-06 15:43:27 -06:00
Gregory Nutt
f43ded46e6 Rename arch/sh to arch/renesas, cont'd 2016-08-06 14:03:38 -06:00
Gregory Nutt
8ee155da3d Rename arch/sh to arch/renesas 2016-08-06 13:33:41 -06:00
Gregory Nutt
f5ae207516 Changes from Review of last PR adding Tiva PWM driver 2016-08-05 07:17:42 -06:00
Young
2994decd3c Add tiva PWM lower-half driver implementation 2016-08-05 18:53:25 +08:00
Gregory Nutt
3d5df2e5af Extend I/O Expander interrupt controls; Add test of level sensitve interrupt to Simulated I/O expander 2016-08-04 16:19:52 -06:00
Gregory Nutt
1f9799b68d I/O Expanders: Interrupt detection logic should not ignore the no-change case. Still need to handle level interrupts even with no change. 2016-08-03 13:10:20 -06:00
Gregory Nutt
803b540e8a Fix various issues with I/O expander and GPIO lower half drivers from testing with simulated I/O expander 2016-08-03 12:46:54 -06:00
Gregory Nutt
c11473657c SIM I/O Expander: Add logic to simulate inverted pins and to generate toggle values on interrupt input pins 2016-08-03 11:19:16 -06:00
Gregory Nutt
778a8131bf SIM: Add a simulated I/O Expander driver 2016-08-03 09:44:48 -06:00
Gregory Nutt
b7c1544f0f Sim build: Add sigaddset to nuttx-names.dat 2016-08-01 17:32:55 -06:00
Gregory Nutt
d9314c1034 LPC43xx ADC: board.h should be included last; Also, unreleated, update tools/README.txt 2016-07-30 07:05:10 -06:00
Gregory Nutt
309480d0f9 Merge branch 'timekeeping' of bitbucket.org:nuttx/nuttx 2016-07-28 09:34:00 -06:00
Gregory Nutt
59f626313d Changes from review of last PR 2016-07-25 15:16:51 -06:00
Gregory Nutt
250b9d5597 Merged in JordanMacIntyre/nuttx/PWM_driver (pull request #106) 
Pwm_driver
 2016-07-25 14:59:45 -06:00
jmacintyre
f5ea811c97 create PWM driver, still having issues with building 2016-07-25 14:17:07 -05:00
Stefan Kolb
899a8aa2f0 SAMV7 TRNG: Missing endif. 2016-07-25 12:30:39 -06:00
Gregory Nutt
e895e19b9f Minor changes from review of last PR 2016-07-24 07:45:46 -06:00
Wolfgang Reissnegger
c0fa319f2b SAM3/4 UDP: Fix handling of endpoint RX FIFO banks. 
This fixes a race condition where the HW fills a FIFO bank while the SW is
busy, resulting in out of sequence USB packets.
 2016-07-23 20:11:04 -07:00
Wolfgang Reissnegger
cc191a977d SAM3/4 UDP: Remove redundant EP state assignment. 2016-07-23 20:11:03 -07:00
Wolfgang Reissnegger
f3a6a40f62 SAM3/4 Serial: Fix warning when CONFIG_SUPPRESS_UART_CONFIG is set. 2016-07-23 16:23:49 -07:00
Gregory Nutt
9b9b721406 Rename alarm_enable to rtc_alarm_enabled; mark inline 2016-07-23 12:01:57 -06:00
Gregory Nutt
5a0f9fcb7d Fix STM32 RTC Alarm interrupts. They were being enabled BEFORE the interrupt system was being initialized. 2016-07-23 10:36:06 -06:00
Gregory Nutt
14de4b99f8 Simplify some computations 2016-07-23 08:13:25 -06:00
Gregory Nutt
0984fcda44 Back out last RTC alarm changes. I am mistaken, the interrupts are enabled by stm32[l4]_exti_alarm(). 2016-07-23 07:53:08 -06:00
Gregory Nutt
65ac11692d STM32L4 RTC is cloned from F4; needs same fix. 2016-07-23 07:33:44 -06:00
Gregory Nutt
829c5610da STM32 F4 RTC ALARM: Was not enabling interrupts. 2016-07-23 07:19:14 -06:00
Gregory Nutt
e77872057d Fix up a few remaining incorrect CONFIG_GPIO_IRQ 2016-07-22 15:01:00 -06:00
Gregory Nutt
e897ccb940 Rename x86 QEMU version of CONFIG_GPIO_IRQ to CONFIG_QEMU_GPIOIRQ 2016-07-22 14:54:00 -06:00
Gregory Nutt
5a9519d636 Rename HCS12 version of CONFIG_GPIO_IRQ to CONFIG_HCS12_GPIOIRQ 2016-07-22 14:53:17 -06:00
Gregory Nutt
c00ad93165 Rename HC version of CONFIG_GPIO_IRQ to CONFIG_HCS12_GPIOIRQ 2016-07-22 14:46:54 -06:00
Gregory Nutt
e6137ff129 Rename SAMD/L version of CONFIG_GPIO_IRQ to CONFIG_SAMDL_GPIOIRQ 2016-07-22 14:38:33 -06:00
Gregory Nutt
3aea9b8bf3 Rename KL version of CONFIG_GPIO_IRQ to CONFIG_KL_GPIOIRQ 2016-07-22 14:34:21 -06:00
Gregory Nutt
5386403476 Rename Kinetis version of CONFIG_GPIO_IRQ to CONFIG_KINETIS_GPIOIRQ 2016-07-22 14:30:37 -06:00
Gregory Nutt
264578135d Rename LP11xx version of CONFIG_GPIO_IRQ to CONFIG_LPC11_GPIOIRQ 2016-07-22 14:23:31 -06:00
Gregory Nutt
360efe03c1 Rename LP17xx version of CONFIG_GPIO_IRQ to CONFIG_LPC17_GPIOIRQ 2016-07-22 14:18:30 -06:00
Gregory Nutt
369c942605 uint8_t is big enough for global. Range of values only 2-10 2016-07-21 15:18:27 -06:00
Gregory Nutt
67900beaaa LP43 Heap: REALLY eliminate the warning this time 2016-07-21 15:15:56 -06:00
Gregory Nutt
d5acc120a4 Kinetis K60: Fix some bad conditional compilation 2016-07-21 14:22:00 -06:00
Gregory Nutt
a2035f7efd Move include/nuttx/1wire.h to include/nuttx/drivers/1wire.h 2016-07-21 13:51:28 -06:00
Gregory Nutt
96d5b734a8 Add missing TWI definitions 2016-07-21 08:01:59 -06:00
Gregory Nutt
0d98507af1 Eliminate a warning 2016-07-20 16:47:23 -06:00
Gregory Nutt
ee9c66186c ramdisk.h moved from include/fs/nuttx/ to include/nuttx/drivers. 2016-07-20 14:02:18 -06:00
Gregory Nutt
1b9b3a7b47 pwm.h moved from include/nuttx/ to include/nuttx/drivers. 2016-07-20 13:48:24 -06:00
Gregory Nutt
ddcaa3d425 can.h moved from include/nuttx/ to include/nuttx/drivers. 2016-07-20 13:38:36 -06:00
Gregory Nutt
4b4dbc79a2 Move driver related prototypes out of include/nuttx/fs/fs.h and into new include/drivers/drivers.h 2016-07-20 13:15:37 -06:00
Sagitta Li
e07bd757ba STM32 F107: TIM8 not supported in F105/F107 2016-07-20 08:51:03 -06:00
Ken Pettit
b926334a19 Add file was not included in the original commit 2016-07-19 10:39:43 -06:00
Vytautas Lukenskas
ac2a5e079c Add change missing in Make.defs for last LPC43xx change 2016-07-19 09:28:15 -06:00
Gregory Nutt
8eeecff79d Replace some C99 comnents with C89 comments 2016-07-19 08:19:53 -06:00
Ken Pettit
148cf1ac22 Adds the simulated QSPI (N25Q) flash to the simulation and modify sim up_spiflash.c to enable it to run with different MTD drivers based on config options (currently m25p, sst26 and w25). 2016-07-19 07:33:44 -06:00
Vytautas Lukenskas
f222d37aa7 Extend LPC43xx EMC code to support SDRAM on a dynamic memory interface. 2016-07-19 07:11:04 -06:00
Gregory Nutt
2119c5ce19 Fix another function naming error 2016-07-18 12:40:27 -06:00
Gregory Nutt
d36da2b560 Fix bad dev[u]random_register() function return value. 2016-07-18 12:25:05 -06:00
Gregory Nutt
d5388eca05 devrandom_register() must be called before devurandom_register() 2016-07-18 11:24:04 -06:00
Gregory Nutt
078bbe5e5c All H/W RNG Drivers: Can now be configured to register as /dev/random and/or /dev/urandom 2016-07-18 11:10:37 -06:00
Gregory Nutt
1660329d06 Rename up_rnginitialize to devrandom_register 2016-07-18 10:55:37 -06:00
Gregory Nutt
fe315f867a Costmetic 2016-07-17 17:01:35 -06:00