sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
41,576 Commits 1 Branch 0 Tags 291 MiB
08aa9ce540
Commit Graph

106 Commits

Author SHA1 Message Date
Xiang Xiao
001e7c3e76 sched: Don't include nuttx/sched.h inside sched.h 
But let nuttx/sched.h include sched.h instead to
avoid expose nuttx kernel API to userspace.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-05-24 12:11:53 +09:00
Alan C. Assis
1a84314f5d xtensa: #ifdef SYMBOL is always true if SYMBOL defined as 0 2021-05-22 08:35:12 -05:00
Alan C. Assis
0a0a034a3f esp32: replace EPS32 typo with ESP32 2021-04-29 18:03:05 -03:00
Alin Jerpelea
cb2ecefbf1 arch: xtensa: fix nxstyle errors 
Fix for errors reported by nxstyle tool

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-07 21:21:51 -05:00
Alin Jerpelea
778f050102 arch: xtensa: Author Gregory Nutt: update licenses to Apache 
Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-02 03:14:31 -05:00
Abdelatif Guettouche
27d5c9340a esp32_allocateheap.c: Don't allocate the ROM CPU regions the same way in 
QEMU, the image is different.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-18 11:28:36 +09:00
Dong Heng
b2f5031e96 xtensa/esp32: Refactor ESP32 WiFi driver to support station and softAP coexistence 2021-03-16 10:20:59 -03:00
Abdelatif Guettouche
28160823b6 arch/xtensa/esp32: ~6KB of memory at address 0x3ffae6f0 is not used by 
the ROM bootloader, add that to the heap as well.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-16 16:22:08 +09:00
Abdelatif Guettouche
8389e83742 esp32/memory_layout.h: Update the layout taking under consideration the 
changes to the heap regions and to the internal heap.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-16 16:22:08 +09:00
Abdelatif Guettouche
9cfc30fa85 memory_layout.h: Fix the start of region2 when a QEMU image generation 
is enabled.

That region is technically part of the PRO CPU and we should be able to
allocate it early.  However, QEMU uses a slightly different bootloader
image that uses the same part for both CPU.  So, when APP CPU starts
during the SMP bring up it will corrupt some data.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-16 16:22:08 +09:00
Abdelatif Guettouche
5c7d041b91 arch/xtensa/esp32: In SMP case move the internal memory to region 3. 
Region 2 is only 15KB in SMP, so we don't have enough memory to play
with.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-16 16:22:08 +09:00
Abdelatif Guettouche
cba44928d2 arch/xtensa/esp32: Part of the ROM regions in middle of DRAM are not 
used, retrieve them as heap.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-16 16:22:08 +09:00
Abdelatif Guettouche
a68a39c785 xtensa/esp32: Move internal heap to the beginning of region 2. 
Internal heap was occupying the region straight after .data up to
HEAP_REGION1.  The issue with this is if static allocation is large,
we'll end up with too little memory left for the internal heap.
Moving it to the beginning of region 2 gives us more room to play with.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-16 16:22:08 +09:00
Gustavo Henrique Nihei
330eff36d7 sourcefiles: Fix relative path in file header 2021-03-09 23:18:28 +08:00
YAMAMOTO Takashi
e05762c488 esp32/memory_layout.h: Replace Gregory Nutt's copyright notice 
The old copyright notice was inherited from esp32_allocateheap.c.
The new copyright notice was copy-and-pasted from sched_getcpu.c.
 2021-03-05 10:15:52 +00:00
YAMAMOTO Takashi
3857d7491f esp32: Extract memory layout definitions to a separate header 2021-03-05 10:15:52 +00:00
chenwen
19627095e4 esp32/esp32_allocateheap.c: Support the maximum available internal heap configuration 2021-03-02 18:27:20 -08:00
chenwen
516c553b97 esp32/esp32_wifi_adapter.c: Fix the issue of WiFi internal malloc from PSRAM 2021-03-02 18:27:20 -08:00
Alan C. Assis
6a87b85285 xtensa/esp32: Add efuse driver 2021-01-26 18:23:43 -08:00
Abdelatif Guettouche
1f96f42f1e arch/xtensa/include/irq.h: Reserve some space for interptee's BSA. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-12-09 09:44:04 -03:00
YAMAMOTO Takashi
b8e559bb2e xtensa: Add _intmax_t and _uintmax_t 2020-11-19 00:49:56 -08:00
YAMAMOTO Takashi
c18f074830 xtensa: Change _int32_t from long to int to match the compiler 
PRIx32 etc is already "x" etc.
 2020-11-19 00:49:56 -08:00
YAMAMOTO Takashi
6bc93b87b0 xtensa inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
Abdelatif Guettouche
9b98f20969 arch/xtensa: Fix the naming of the internal heap functions. They should 
be prefixed by xtensa_ instead of up_.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-10-25 20:20:01 -03:00
Abdelatif Guettouche
7ac5f7a35b arch/xtensa/src/esp32: Add a PROCFS entry for the internal memory 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-10-25 20:20:01 -03:00
Abdelatif Guettouche
a1318926b4 arch/xtensa/esp32: Allow internal drivers and tasks' stack to be 
allocated in an internal heap.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-10-25 20:20:01 -03:00
Abdelatif Guettouche
286d947caf arch/xtensa: Fix some alingments and typos in assembly code. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-10-11 00:53:38 +08:00
Sara Souza
0faf861256 xtensa/esp32: Added Timer Support 2020-10-07 14:12:22 -03:00
Abdelatif Guettouche
62732dd6b8 arch/xtensa/src/esp32/esp32_gpio.c: ESP32_NIRQ_GPIO was used instead of 
ESP32_NGPIOS

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-10-02 11:42:49 -03:00
Abdelatif Guettouche
769d68a762 arch/xtensa: Fix some typos and correct some comments. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-09-30 13:55:28 -03:00
chenwen
64e2f102ac xtensa/esp32: Add power management of force-sleep 2020-09-20 17:23:07 +01:00
Ouss4
8d32930d29 arch&boards/xtensa: Fix some typos, references to STM/ARM code and 
change file headers where Gregory Nutt is the only author.
 2020-08-27 05:48:55 -07:00
Alan C. Assis
7a1342f503 Fix coding style and other small issues 2020-08-23 08:26:10 -06:00
Alan C. Assis
4ded03a673 ESP32: Add support to RNG HW Driver 2020-08-23 08:26:10 -06:00
Alan C. Assis
79a3fd1932 ESP32: Add driver support to SPI Master and Slave 
This driver was implemented by Dong Heng <dongheng@espressif.com>
and modified to fix coding style by Alan Carvalho de Assis.
 2020-07-19 21:26:58 +01:00
Xiang Xiao
05f6445493 arch: Move *_getsp to the common place arch/arch.h 
so other place can get the stack pointer easily

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-07-09 13:51:09 +01:00
Xiang Xiao
4fbbd2e3bf arch: Move PRIxMAX and SCNxMAX definition to include/stdint.h 
like other related macro(e.g. INTMAX_MIN, INTMAX_MAX...)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I8863599960b1a9b1c22ae9c35735a379a4c745b0
 2020-06-10 08:24:47 +02:00
Xiang Xiao
7758eb8658 arch: Define INTx_C and UINTx_C macro 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia50ea8764880fabd3d878c95328632c761be6b43
 2020-06-10 08:24:47 +02:00
Gregory Nutt
c2244a2382 Remove CONFIG_TLS 
A first step in implementing the user-space error is force TLS to be enabled at all times.  It is no longer optional
 2020-05-07 12:04:16 -06:00
Ouss4
a4dd967440 arch/: Implement up_tls_info() for the rest of the architectures. 2020-05-06 21:56:40 -06:00
Nathan Hartman
679b4fbee2 arch: Fix included directed -> included directly 
This typo had been copied and pasted into numerous irq and syscall
headers.
 2020-04-05 22:31:15 +01:00
YAMAMOTO Takashi
f4e7845b85 esp32: emulate byte access for module text 
Tested on ESP-EYE.
 2020-03-16 07:54:49 -06:00
YAMAMOTO Takashi
e135c938d2 xtensa: Implement a few relocations 2020-03-16 07:54:49 -06:00
YAMAMOTO Takashi
8657305883 arch/xtensa/include/elf.h: Initial version 2020-03-16 07:54:49 -06:00
YAMAMOTO Takashi
c18d7dc434 xtensa: Implement simcall 2020-03-12 09:03:31 -05:00
YAMAMOTO Takashi
7774cdd7aa Appease many of nxstyle errors for esp32 related files 
I skipped the following files because they were not simple.
I'll create separate PRs.

    arch/xtensa/src/esp32/esp32_cpustart.c
    arch/xtensa/src/common/xtensa_abi.h
    boards/xtensa/esp32/esp32-core/include/board.h

Also, I skipped the following files and directories because
they looked too huge and/or foreign.

    arch/xtensa/include/esp32/tie.h
    arch/xtensa/include/xtensa/xtensa_corebits.h
    arch/xtensa/src/esp32/hardware/
    arch/xtensa/include/esp32/tie-asm.h
    arch/xtensa/include/esp32/core-isa.h
    arch/xtensa/include/xtensa/core.h

I also fixed a few "is is" style typos when unwrapping long lines.
 2020-03-12 07:45:44 -06:00
Xiang Xiao
cde88cabcc Run codespell -w with the latest dictonary again 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-02-23 22:27:46 +01:00
Xiang Xiao
bd4e8e19d3 Run codespell -w against all files 
and fix the wrong correction
 2020-02-22 14:45:07 -06:00
Xiang Xiao
e7d9260014 arch: Customize the typedef of size_t instead of intptr_t 
To ensure size_t same as toolchain definition in the first place and rename CXX_NEWLONG to ARCH_SIZET_LONG.  The change also check whether __SIZE_TYPE__ exist before CONFIG_ARCH_SIZET_LONG so our definition can align with toolchain(gcc/clang) definition automatically.
 2020-02-18 07:15:19 -06:00
Xiang Xiao
68951e8d72 Remove exra whitespace from files (#189) 
* Remove multiple newlines at the end of files
* Remove the whitespace from the end of lines
 2020-01-31 09:24:49 -06:00