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Author SHA1 Message Date
Barry Xu
099980efb5 Support different hardware version of Wi-Fi add-on board (iS110B) 
Signed-off-by: Barry Xu <barry.xu@sony.com>
 2021-04-14 16:10:51 +09:00
raiden00pl
f467a741fb nucleo-g431rb: add PWM example 2021-04-13 13:07:38 -07:00
raiden00pl
beebb57445 stm32g4xx: add support for FOC 2021-04-13 14:38:28 -05:00
raiden00pl
835b129c94 stm32g4xx: add DBGMCU definitions 2021-04-13 14:38:28 -05:00
Michal Lenc
0719976722 Documentation: added documentation for i.MX RT series and Teensy 4.x board 
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-04-13 13:18:47 -05:00
Anthony Merlino
9c8c2b0db2 Separate CLOCK_TIMEKEEPING and SCHED_TICKLESS. 2021-04-13 11:42:31 -05:00
Masayuki Ishikawa
fa5daea3d9 drivers: wireless: Fix to receive a UDP packet partially in gs2200m.c 
Summary:
- When receiving a UDP packet partially, the rest of the packet
  must be discarded.

Impact:
- None

Testing:
- Tested with a UDP sample program

Reported-by: Masatoshi Ueno <Masatoshi.Ueno@sony.com>
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-04-13 10:37:15 -05:00
raiden00pl
c90a6bdf2b stm32/Kconfig: enable ADCx DMA support if DMAMUX enabled 2021-04-13 12:08:17 -03:00
raiden00pl
bf04ef9a3c stm32g4: add support for DMA (DMAMUX) 2021-04-13 12:08:17 -03:00
Abdelatif Guettouche
ad43d9e8f3 boards/esp32c3-devkit: Add an OSTest defconfig. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-04-13 12:07:56 -03:00
raiden00pl
fbb7e95ebf stm32g4xxxx_dmamux.h: rename defs to match other chips and add DMAMAP defs 2021-04-13 09:20:18 -05:00
raiden00pl
a735252d78 stm32h7,stm32g0: fix typos in DMAMUX 2021-04-13 09:20:18 -05:00
raiden00pl
62001bff3b stm32g4xx: add support for PWM 2021-04-13 09:19:52 -05:00
raiden00pl
4c741bc9a5 stm32/Kconfig: G4 chips use TIMERS_V2 2021-04-13 09:19:52 -05:00
raiden00pl
ff2ae3e894 stm32g4xx: add support for ADC 2021-04-13 09:29:09 -03:00
raiden00pl
fd754f88b7 nucleo-g431rb: add button support 2021-04-13 05:29:32 -05:00
raiden00pl
5dd19f8072 nucleo-g431rb: refactor bringup logic for consistency with other boards 2021-04-13 05:29:32 -05:00
Alin Jerpelea
325446044d NuttX: Add AUTHORS file 
Add AUTHORS file for contributors that have sumbitted ICLA, CCLA or SGA

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-13 05:28:28 -05:00
Alin Jerpelea
20d315abfe NuttX: Falker Atomacao Agrícola Ltda: update licenses to Apache 
Falker Atomacao Agrícola Ltda has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-13 05:28:28 -05:00
Anthony Merlino
1a5a7a1b63 stm32h7: Allow OTGHS to use internal FS PHY 2021-04-12 23:21:34 -05:00
Jukka Laitinen
3f6bb76e01 arch/arm/src/stm32f7/stm32_allocateheap.c: Fix MPU alignments 
Change the logic for allocating user heap for PROTECTED_BUILD:
- Don't rely on SRAM1_END alignment
- Make better use of MPU subregions when allocating the heap
- Don't duplicate the calculation of user heap start in kernel heap
  allocation; use the previous calculation directly

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-04-12 23:20:18 -05:00
Jukka Laitinen
ea36c2c7ea Remove MPU_RASR_S bit from stm32f7 MPU user mode intsram configration 
For some reason, setting the "shareable" bit makes the SRAM not writable

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-04-12 23:20:18 -05:00
Masayuki Ishikawa
0d1d42ec5f boards: spresense: Update defconfigs for rndis and rndis_smp 
Summary:
- Update spresense:rndis_smp
  - Remove CONFIG_MAX_TASKS=16
  - Enable CONFIG_RTC_ALARM and CONFIG_RTC_HIRES
- Update spresense:rndis
  - Follow rndis_smp configuration except for SMP

Impact:
- spresense:rndis and spresense:rndis_smp

Testing:
- Tested with nxplayer

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-04-12 23:19:30 -05:00
Xiang Xiao
3f9908f7d1 Remove the unnecessary math.h inclusion 
or move from header file to source file since math.h doesn't always exist

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-12 22:58:23 -04:00
Anthony Merlino
2b46a0fdde stm32h7: Adds guards around stm32_iocompensation. 2021-04-12 15:08:52 -07:00
Anthony Merlino
a45b8cc17c stm32h7: Add support for IO compensation. 2021-04-12 15:08:52 -07:00
jturnsek
bbe875876d Modified FlexSPI driver 2021-04-12 17:22:14 -03:00
jturnsek
f57ff30545 Removing FLexSPI NOR driver 2021-04-12 17:22:14 -03:00
jturnsek
177ff946b8 Missing nl 2021-04-12 11:35:44 -03:00
jturnsek
7453e76d98 FlexSPI NOR driver 2021-04-12 11:35:44 -03:00
Jukka Laitinen
8334843bad Make noreturn proxies and stubs actually not return 
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-04-12 03:57:35 -05:00
Jukka Laitinen
82a75122b0 Revert "mksyscall: Suppress "'noreturn' function does return" warnings" 
This reverts commit f01953d364.
 2021-04-12 03:57:35 -05:00
Dong Heng
31854ca135 riscv/esp32c3: Fix heap end address 2021-04-12 01:36:11 -05:00
Masayuki Ishikawa
7ce1033aa2 arch: k210: Fix interrupt stack corruption in SMP mode 
Summary:
- I noticed that stack corruption happens due to recent refactoring
- This commit fixes this issue

Impact:
- SMP only

Testing:
- Tested with maix-bit:smp (QMU and dev board)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-04-11 13:00:40 -05:00
Gregory Nutt
2882551299 Correct a comment 
Fix comment in libs/libc/tls/tls_getinfo.c:  The TLS data must lie at the beginning of the allocated stack memory for both push-up and push-down stacks.
 2021-04-11 12:32:41 -05:00
Alan Carvalho
ac5fb7d701 esp32: Fix GPIO Pull-Up/Pull-Down using RTC GPIO 
Some ESP32 GPIO pins (2, 4, 12, 13, 25, 27, 32) weren't accepting
pull-up/pull-down resistors. These pins are RTC GPIO pins and need
to have pull-up/pull-down configured in the RTC registers.

Co-authored-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-04-11 14:36:02 +01:00
raiden00pl
4972153ee6 nucleo-f103rb: add FOC example based on IHM07M1 expansion board (only fixed16) 2021-04-11 03:52:21 -05:00
raiden00pl
cf645fc9ba arch/arm/src/stm32/stm32_foc.c: add modifications to support STM32F1 
- generalize DBGMCU for PWM timer
- use ADC common data only if coupled ADC present
- rename some ADC definitions that collide with stm32_adc.h
 2021-04-11 03:52:21 -05:00
raiden00pl
021a89569d arch/arm/src/stm32: introduce DBGMCU IP core versions 2021-04-11 03:52:21 -05:00
raiden00pl
3caf26fe3e arch/arm/src/stm32/stm32_adc.c: support adc_inj_startconv also for STM32F1 2021-04-11 03:52:21 -05:00
raiden00pl
ad6c4ff0cd nucleo-f103rb: refactor bringup logic for consistency with other boards 2021-04-11 03:52:21 -05:00
Brennan Ashton
e945f2da86 Add define for _POSIX_TIMEOUTS 2021-04-11 01:50:34 -05:00
Anthony Merlino
2aa2b7669f stm32f7 tickless: Fix handling of overflow for different width timers. 2021-04-10 23:38:16 -05:00
Anthony Merlino
f979dd72c1 stm32/stm32f7 tickless: Fix clearing and checking of interrupts. 2021-04-10 23:38:16 -05:00
Anthony Merlino
dd00c6427e stm32 tickless: Fixes printf warnings 2021-04-10 23:38:16 -05:00
Abdelatif Guettouche
3ac2bde85b pthread_mutexattr_setprotocol.c: Return EINVAL instead of ENOSYS. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-04-10 22:55:03 -05:00
raiden00pl
5eadd8b3a9 nucleo-f446re: add ADC example 2021-04-10 15:48:06 -05:00
raiden00pl
155770b1e7 nucleo-f446re: fix compilation error when ADC is enabled and FOC is disabled 2021-04-10 15:48:06 -05:00
Xiang Xiao
3f67c67aaf arch: Fix the stack boundary calculation and check 
All supported arch uses a push-down stack:
The stack grows toward lower addresses in memory. The stack pointer
register points to the lowest, valid working address (the "top" of
the stack). Items on the stack are referenced as positive(include zero)
word offsets from sp.
Which means that for stack in the [begin, begin + size):
1.The initial SP point to begin + size
2.push equals sub and then store
3.pop equals load and then add

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-10 08:39:54 -07:00
Christian Clauss
15932fa9ea Lint Python code with flake8 and isort 2021-04-10 08:36:29 -07:00