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19169 Commits

Author SHA1 Message Date
Ville Juven
e674d5cb86 RISC-V: Add crt0 file 
Contains the code for the user process signal trampoline.
 2022-04-29 02:02:15 +08:00
Ville Juven
0ccda05a82 RISC-V: Move wipe_page to pgalloc.h and rename it riscv_pgwipe 2022-04-29 02:02:15 +08:00
Ville Juven
3d8ba496a2 RISC-V: Add pgpool to vaddr utility function 
The only mapping that is supported now is vaddr=paddr, but the function
DOES check that the address is within the page pool, so it is not
useless.
 2022-04-29 02:02:15 +08:00
Ville Juven
1322f82802 RISC-V: Copy kernel memory mappings to userspace addrenv 
Copy the kernel mappings to the new (user) address environment. The
copyuing is done exactly once. This relies on the fact that the kernel
L1/L2 mappings will never change, as all of the kernel memory is mapped
upon boot.
 2022-04-29 02:02:15 +08:00
Ville Juven
57127b9429 RISC-V: Initial support for CONFIG_BUILD_KERNEL 
This implements initial support for kernel build (address environments,
page allocator) for RISC-V.

This is done a bit differently compared to the ARMV7 implementation:

- Support implemented for Sv39 MMU, however the implementation should be
  extensible for other MMU types also.
- Instead of preserving and moving the L1 references around, a canonical
  approach is used instead, where the page table base address register
  is switched upon context switch.
- To preserve a bit of memory, only a single L1/L2 table is supported,
  this gives access to 1GiB of virtual memory for each process, which
  should be more than enough.

Some things worth noting:
- Assumes page pool is mapped with vaddr=paddr mappings
- The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are
  ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used
  for ARCH_DATA_RESERVE
- ARCH_DATA_RESERVE is placed at the beginning of the userspace task's
  address environment
 2022-04-29 02:02:15 +08:00
Xiang Xiao
2dbf826c19 config: It's enough to let LTO_FULL depend on ARCH_TOOLCHAIN_GNU only 
since ARCH_TOOLCHAIN_CLANG automatically select ARCH_TOOLCHAIN_GNU

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-28 11:25:00 +09:00
Gustavo Henrique Nihei
ffab2dc628 risc-v: Restrict Fence instruction for chips that support S-mode 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-04-28 01:18:46 +08:00
Gustavo Henrique Nihei
1967805b91 risc-v: Fix format specifier in debug log 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-04-28 01:18:46 +08:00
chao.an
042640abbf arch/arm: add support for GCC LTO 
1. Enable GCC link-time optimizer
2. Enable use of a linker plugin during link-time optimization

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-27 23:42:54 +08:00
chao.an
cbef8681fe arch/risc-v: add support for GCC LTO 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-27 23:42:37 +08:00
Ville Juven
216574bba8 OpenSBI: Add riscv_hardfp.S to compilation 
It will just become an empty object if FPU support is not included.
 2022-04-27 23:20:51 +08:00
dytang
d7cc3f9275 RISC-V: workaround for the RV64 SoC which does not has mem mapped MTIMER currten value regs. 2022-04-27 22:48:54 +08:00
Abdelatif Guettouche
98d8d2a1ff arch/xtensa: Group all the macros in one file. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-27 08:57:53 -03:00
Abdelatif Guettouche
541eabb535 xtensa_int_handlers.S: Refactor the calls to ps_setup. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-27 08:57:53 -03:00
chao.an
db54b0b836 arm/assert: fix build warning on clang 
common/arm_assert.c:80:14: warning: format specifies type 'unsigned int' but the argument has type 'uint32_t' (aka 'unsigned long') [-Wformat]
             stack, ptr[0], ptr[1], ptr[2], ptr[3],
             ^~~~~
include/debug.h:119:59: note: expanded from macro '_alert'
   __arch_syslog(LOG_EMERG, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
                                      ~~~~~~              ^~~~~~~~~~~

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-27 14:18:42 +08:00
Abdelatif Guettouche
587145a881 riscv/Makefile: Delete old target used for debugging. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-27 12:58:57 +08:00
Xiang Xiao
fc16cfaefe Correct the code alignment found in review 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-26 11:34:28 +03:00
Abdelatif Guettouche
aaa5316235 arch/xtensa: Simply use xtensa_createstack for CPU1 idle task. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-26 01:36:54 +08:00
Ville Juven
6546789b7e RISC-V: Add syscall support for vfork 
If vfork is called via syscall (PROTECTED/KERNEL build) need to set up
return parameters for syscall. Otherwise the SW will get lost.
 2022-04-25 16:23:17 +03:00
Xiang Xiao
8f8ee25a9c boards: Move -g from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-25 16:23:03 +03:00
Xiang Xiao
e9f5eb0823 boards: Move "-fno-exceptions -fcheck-new" from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-25 16:22:46 +03:00
Ville Juven
a014daf44f RISC-V: Add implementation for vfork 2022-04-25 15:44:32 +08:00
Ville Juven
2580520828 RISC-V: Fix system crash when FPU is in use 
FPU registers need to be written prior to updating CSR_STATUS
 2022-04-25 15:44:06 +08:00
Xiang Xiao
75326e563d boards: Move -fno-common from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-25 07:57:29 +03:00
Abdelatif Guettouche
3942f4d133 arch/xtensa: No need to save SP in EXCSAVE_1 when linking the interrupt 
frame with the previous frame.  The SP is already saved in A12.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-23 10:19:23 +08:00
Abdelatif Guettouche
f130d8c143 xtensa_user_handler.S: Fix backtrace. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-23 10:19:23 +08:00
Abdelatif Guettouche
7a3ad4b224 xtensa_user_handler.S: Use the ps_setup macro when dealing with an 
exception.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-23 10:19:23 +08:00
Xiang Xiao
5a565e753c pm: Move pm_initialize call from driver_initialize to xxx_pminitialize 
since it's too late with the below commit:
ommit a594a5d7a8
Author: chao.an <anchao@xiaomi.com>
Date:   Mon Apr 11 19:44:26 2022 +0800

    sched/init: drivers_initialize() should be late than up_initialize()

    up_initialize
    |
     ->up_serialinit
       |
        ->uart_register  /* ("/dev/console", &CONSOLE_DEV); */

    drivers_initialize
    |
     ->syslog_console_init
       |
        ->register_driver /* ("/dev/console", &g_consoleops, 0666, NULL); */

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-22 14:36:27 +03:00
Masayuki Ishikawa
04f81ecddb arch: risc-v: Do not enable FPU for K210 with QEMU 
Summary:
- I noticed that maix-bit:smp does not work with QEMU.
- Actually, QEMU supports sifive_u (not K210) but it works
  if FPU is disabled.
- This commit fixes this issue.

Impact:
- K210 with QEMU only

Testing:
- Tested with qemu-5.2

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-04-22 14:52:04 +08:00
Huang Qi
06c7a3ca59 arch/risc-v/riscv_misaligned: Implement float load/store support 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-22 12:23:10 +08:00
Huang Qi
be95e76910 arch/risc-v: Enable FPU for K210 
K210 support rv64gc ISA, now we enable F/D extension for it.

Note: QEMU for K210 don't support FPU now.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-21 21:47:29 +03:00
chao.an
1c8e12406e compile/opt: add config DEBUG_LINK_MAP 
Selecting this option will pass "-Map=$(TOPDIR)$(DELIM)nuttx.map" to ld
when linking NuttX ELF. That file can be useful for verifying
and debugging magic section games, and for seeing which
pieces of code get eliminated with DEBUG_OPT_UNUSED_SECTIONS.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-22 01:37:23 +08:00
chao.an
64d7326ed5 compile/opt: add config DEBUG_OPT_UNUSED_SECTIONS 
Enable this option to optimization the unused input sections with the
linker by compiling with " -ffunction-sections -fdata-sections ", and
linking with " --gc-sections ".

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-22 01:37:23 +08:00
Abdelatif Guettouche
56ecd44f63 arch/xtensa: Color the other CPUs task when they are created. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-22 01:12:55 +08:00
Xiang Xiao
1320e5add4 arch/arm: Move the duplicated assembly code to common folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-21 12:56:34 +03:00
Xiang Xiao
ebf1093cff arch/arm: Switch the context of save and restore from assembler to c 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-21 12:56:34 +03:00
Huang Qi
0332b78f99 arch/risc-v: Don't clear reserved bits in fcsr in riscv_fpuconfig 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-21 15:26:05 +08:00
chao.an
875c5dac75 arm/armv[7|8]m: compare of hardware fp registers should skip REG_FP_RESERVED 
Fix fpu test break

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-21 14:55:54 +09:00
Abdelatif Guettouche
64e4c9ca02 arch/xtensa: Move xtensa_save_context to up_saveusercontext for 
consistency with other archs.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-21 01:59:34 +08:00
Abdelatif Guettouche
6db910a1aa arch/xtensa: Use syscall interface for xtensa_save/restore_context. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-21 01:59:34 +08:00
chao.an
0315283c21 arch/clang: add support for Clang LTO 
add support of Clang's Link Time Optimization (LTO) on NuttX build system

Reference:
https://gcc.gnu.org/onlinedocs/gccint/LTO-Overview.html
https://llvm.org/docs/LinkTimeOptimization.html

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-21 01:21:54 +08:00
chao.an
67fbfda974 arch/armv6-m: add support of LLVM Clang 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-21 01:21:54 +08:00
Huang Qi
48b81bda09 arch/risc-v: Change riscv_savefpu/riscv_loadfpu to macro 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-20 16:08:17 +03:00
Alin Jerpelea
dda675779a arch: arm: mor1kx: remove empty files 
during contribution empty files have been pushed.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Alin Jerpelea
af98967439 arch: arm: stm32l4: remove empty files 
during contribution empty files have been pushed.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Alin Jerpelea
73cd86dad7 arch: arm: phy62xx: Add Apache license to files 
In the initial contribution those files were missing the license

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Alin Jerpelea
22ceda26bb arch: arm: lpc43xx: Add Apache license to files 
In the initial contribution those files were missing the license

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Alin Jerpelea
4e19a97916 arch: arm: imxrt: Add Apache license to files 
In the initial contribution those files were missing the license

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Alin Jerpelea
208b892efe arch: arm: cxd56xx: Add Apache license to files 
In the initial contribution those files were missing the license

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Huang Qi
95ab7b973b arch/sparc,xtensa: Control output by $(Q) as other arch 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-20 12:04:17 +02:00
zhuyanlin
8d756a75a2 armv7/r:cp15_cache_all: fix error in LineSize 'r5' mask 
r5 = r3 & r1

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-04-20 08:06:58 +09:00
chao.an
fc3565e9eb arch/z80: Unify the toolchain definition of SDCC for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
0cf8088406 arch/misoc: Unify the toolchain definition of GNU for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
e066d5d1e0 arch/risc-v: Unify the toolchain definition of RVG for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
2df591b3bb arch/armv7-a/r: Unify the toolchain definition of eabi for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
4a085e1cdb arch/arm/armv6-m: Unify the toolchain definition of eabi for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
2246afcdd8 arch/armv7-m: Unify the toolchain definition of eabi/clang/iar for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
a79bf8c9eb arch/armv8-m: Unify the toolchain definition of eabi/clang for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
Ville Juven
5b6dd876b8 risc-v/riscv_assert.c Fix dumping of status from ISR 
The status dump did not work if the first fault triggers before
the first context switch (during nx_start()).
 2022-04-19 15:28:09 +03:00
Ville Juven
5c951d8c4a arm/arm_assert.c Fix dumping of status from ISR 
The status dump did not work if the first fault triggers before
the first context switch (during nx_start()).
 2022-04-19 15:28:09 +03:00
chao.an
b110c984b1 arch/armv7-[a|r]: correct the handing of group env switch 
This PR resolved 2 issues:
1. CURRENT_REGS is not set correctly on swint handling
2. group env is not changed properly

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 12:10:25 +03:00
Xiang Xiao
96fa8be5f5 arch/armv[7|8]-m: Compare all FPU registers in up_fpucmp 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-19 11:09:36 +03:00
Xiang Xiao
d80c2d7419 arch/arm: Remove all lazy fpu related code 
since it is broken and inefficient, and then removed by:
commit dc961baaea
Author: chao.an <anchao@xiaomi.com>
Date:   Thu Apr 14 18:07:14 2022 +0800

    arm/armv7-[a|r]: move fpu save/restore to assembly handler

    Save/Restore FPU registers in C environment is dangerous practive,
    which cannot guarantee the compiler won't generate the assembly code
    with float point registers, especially in interrupt handling

    Signed-off-by: chao.an <anchao@xiaomi.com>

commit 8d66dbc068
Author: chao.an <anchao@xiaomi.com>
Date:   Thu Apr 7 13:48:04 2022 +0800

    arm/armv[7|8]-m: skip the fpu save/restore if stack frame is integer-only

    Signed-off-by: chao.an <anchao@xiaomi.com>

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-19 11:09:36 +03:00
Xiang Xiao
7c5b2e3305 arch/arm: Remove FAR and CODE from common/ and arm*/ folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-19 00:23:59 +03:00
Xiang Xiao
7a0fd8d10f arch/risc-v: Remove FAR from chip and board folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-19 00:22:45 +03:00
Xiang Xiao
84b0453ef3 arch/arm: Remove unneeded group_addrenv call which handled by arm_doirq 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-18 22:18:32 +03:00
Xiang Xiao
2e7b10356f arch/sparc: Remove unneeded group_addrenv call which handled by up_doirq 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-18 18:34:12 +03:00
Xiang Xiao
d28892e454 arch/xtensa: Remove unneeded group_addrenv call which handled by xtensa_irq_dispatch 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-18 18:34:12 +03:00
Xiang Xiao
ef62e1c970 arch/misoc: Remove unneeded group_addrenv call which handled by [lm32|minerva]_doirq 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-18 18:34:12 +03:00
Xiang Xiao
9fad9ed66b arch/mips: Remove unneeded group_addrenv call which handled by mips_doirq 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-18 18:34:12 +03:00
chao.an
29005bd79f board/arch_fpu*: move arch_[get|cmp]fpu to common arch 
rename the arch api:
arch_getfpu  -> up_saveusercontext
arch_cmpfpu  -> up_cmpfpu

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-18 22:22:16 +08:00
chao.an
5bdfae66ce arch/arm: export arm_saveusercontext() 
rename arm_saveusercontext() -> up_arm_saveusercontext()

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-18 22:22:16 +08:00
chao.an
bdbbdbe242 arm/a1x: fix compile break 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-18 10:02:17 +08:00
Xiang Xiao
ef1a98dd00 Remove the unneeded void cast 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 23:32:05 +03:00
Xiang Xiao
32ee2ae407 Remove the unneeded worker_t cast 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 23:32:05 +03:00
Xiang Xiao
373363d750 arch/arm: Move arm_signal_dispatch.c to common folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 23:30:41 +03:00
wangbowen6
91d02f5db8 arm/arch: using __builtin_frame_address(0) implement up_getsp(). 
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
 2022-04-18 00:49:15 +08:00
Xiang Xiao
6af167c086 arch/sparc: Remove FAR from chip and board folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
977fa987e2 arch/mips: Remove FAR from chip and board folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
1ce592e8b5 arch/misoc: Remove FAR from chip folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
3c82094156 arch/or1k: Remove FAR from chip folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
0bd9a66305 arch/x86_64: Remove FAR from chip folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
af00e016e9 arch/sim: Remove FAR from chip and board folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
e923875c1b arch/ceva: Remove FAR from chip folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
6bc61b5752 arch/xtensa: Remove FAR from chip and board folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
chao.an
c08d9047b2 arch/Toolchain.defs: replace all ${/$} with $(/$) 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-17 00:58:34 +08:00
chao.an
aed21ba0bc arch/armv[7|8]m: enhance the clang support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-17 00:58:34 +08:00
okayserh
3a015d56b0 Fixed a compile error, presumably caused by C&P error. 2022-04-16 19:21:10 +08:00
Jan Charvat
6ec86361a8 arch/riscv/esp32c3: ESP32C3 TWAI (CAN) controller included into Kconfig. 
Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
 2022-04-15 22:55:26 +08:00
Jan Charvat
e28584131d arch/riscv/esp32c3: ESP32C3 TWAI (CAN) controller driver. 
Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
 2022-04-15 22:55:26 +08:00
Jan Charvat
0fa1541a80 arch/riscv/esp32c3: esp32c3_twai.h TWAI (CAN) controller registers provided by Espressif. 
File provided by Abdelatif Guettouche

Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
 2022-04-15 22:55:26 +08:00
Huang Qi
a94c865791 arch/risc-v: Use fs status definition from csr.h 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-15 19:41:31 +08:00
Petro Karashchenko
09b3fb25ab drivers: remove unimplemented open/close/ioctl interfaces 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-04-15 16:56:25 +08:00
Richard Tucker
1b13d1b440 arch/arm/src/sam34/Kconfig: fix typo in device name 2022-04-15 02:22:01 +08:00
Richard Tucker
de66e18d6f arch/arm/src/sam34/sam_hsmci.c: SAM3X GPIO setup 2022-04-15 02:22:01 +08:00
Richard Tucker
929556d750 arch/arm/src/sam34/sam_hsmci: DMA also present on SAM3X chips 2022-04-15 02:22:01 +08:00
Richard Tucker
be0bcac91b arch/arm/src/sam34/sam_hsmci.c: DMA setup before write is required 2022-04-15 02:22:01 +08:00
Richard Tucker
bc7f4b2375 arch/arm/src/sam34/sam_hsmci.c: delay required after sending command 2022-04-15 02:22:01 +08:00
chao.an
dc961baaea arm/armv7-[a|r]: move fpu save/restore to assembly handler 
Save/Restore FPU registers in C environment is dangerous practive,
which cannot guarantee the compiler won't generate the assembly code
with float point registers, especially in interrupt handling

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-14 22:33:10 +08:00
Alan C. Assis
c232be541c Add SPIRAM to ESP32-S2 2022-04-14 22:10:23 +08:00