Dave Marples
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d0cda60442
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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Gregory Nutt
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83bc1c97c3
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Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore()
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2016-02-14 16:11:25 -06:00 |
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Gregory Nutt
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3855ce04e8
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Beginning of high priority nested interrupt support for the ARMv7-M family
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2013-12-21 11:03:38 -06:00 |
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patacongo
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9d829d72a7
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A few fixes for LPC1788 compilation (more needed)
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5649 42af7a65-404d-4744-a932-0658087f49c3
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2013-02-13 15:19:47 +00:00 |
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patacongo
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5ab31d456e
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Add option to use BASEPRI instead of PRIMASK to disable interrupts in all ARMv7-M architectures
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5546 42af7a65-404d-4744-a932-0658087f49c3
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2013-01-22 01:25:40 +00:00 |
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patacongo
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6cfa91d677
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Beginnings of definitions for the LPC1788; convert olimex-lpc1766stk to use kconfig-frontends
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5533 42af7a65-404d-4744-a932-0658087f49c3
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2013-01-18 16:37:37 +00:00 |
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