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880 Commits

Author SHA1 Message Date
Jukka Laitinen
7b8eec3fa4 arch/risc-v/src/common/riscv_exception_common.S: Add support for > 2 CPUs 
Add a new configuration for CONFIG_N_IRQ_STACKS, whcih defaults to
CONFIG_SMP_NCPUS or 1
- this allows configuring multiple IRQ stacks also in the case where SMP
  support is not needed
- this is specifically needed in mpfs target, where "bootloader" build boots
  only on one hart, but the startup code executes on all harts and handles SW IRQs

Also don't store/restore GP if RISCV_SAVE_GP is not defined. If the GP is not
stored in fork, it can't be restored for new tasks

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2022-01-20 01:37:34 +08:00
Petro Karashchenko
9551de7115 net: use HTONS, NTOHS, HTONL, NTOHL macro in kernel code 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-18 10:59:47 +01:00
Huang Qi
676d35f007 risc-v: Make exception_common 8 byte align 
Some SoC like bl602 require the exception entry 8 byte align, it should
be safe for other chips so we can apply it globally.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-17 11:44:50 +08:00
Huang Qi
e97ba17451 arch/risc-v: Refine riscv_cpupause.c 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-16 23:11:32 +08:00
Petro Karashchenko
8d3bf05fd2 include: fix double include pre-processor guards 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-16 11:11:14 -03:00
Huang Qi
3200c936cc arch/risc-v: Refine riscv_cpuindex.c 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-15 21:54:05 +08:00
Huang Qi
56a95ad0b5 risc-v: Remove ARCH_RV_ISA_[F|D] use ARCH_HAVE_FPU instead 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-15 11:42:01 +08:00
Huang Qi
5792d851e5 arch/risc-v/qemu-rv: Support both rv32/rv64 core 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-15 11:42:01 +08:00
Huang Qi
74cce59ac6 arch/risc-v: Make ISA configurable for qemu-rv32 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-15 11:42:01 +08:00
chao.an
3544fc1fd6 risc-v/assert: add CURRENT_REGS check to avoid null pointer reference 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-01-15 02:20:01 +08:00
Eero Nurkkala
09bf8a5f89 risc-v/mpfs: mpfs_opensbi: fix fw_size calculation 
fw_start and fw_size were miscalculated. What was needed
was the pointed values of the offsets __mpfs_nuttx_start
and __mpfs_nuttx_end, not the values they had in place.

Also add the next_arg1 initialization.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2022-01-14 10:10:24 +01:00
Jukka Laitinen
122b907b91 arch/risc-v/src/mpfs/mpfs_opensbi_utils.S: Remove unncessary mv 
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2022-01-14 10:10:24 +01:00
Huang Qi
6f1011a85e arch/risc-v: Rename bl602_entry.S to bl602_head.S 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-13 22:06:49 +01:00
Huang Qi
7c93e96908 arch/risc-v: Fix typo in riscv_assert.c 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-13 14:53:18 +01:00
Huang Qi
3c15ae23cf arch/risc-v: Make __tarp_vec 4 byte align 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-13 14:53:18 +01:00
Huang Qi
c6749fd6fd arch/risc-v: Refine exception_common 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-13 14:53:18 +01:00
Huang Qi
e47a915f4c arch/risc-v: Refine riscv_vectors.S 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-12 18:53:01 +08:00
Huang Qi
10bb48b9b4 arch/risc-v: Merge rv32im and rv64gc into common 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-11 23:24:33 +08:00
chao.an
8c35d31808 Kconfig: Remove CONFIG_ prefix from config definition 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-01-07 13:16:18 +08:00
Zeng Zhaoxiu
fb43fd73ed signal: signal handler may cause task's state error 
For example, task is blocked by nxsem_wait(sem1), use nxsem_wait(sem2)
in signal handler, and take sem2 successfully, after exit from signal
handler to task, nxsem_wait(sem1) returns OK, but the correct result
should be -EINTR.

Signed-off-by: Zeng Zhaoxiu <zhaoxiu.zeng@gmail.com>
 2022-01-05 21:36:44 +09:00
Jukka Laitinen
9aea5d5dbb arch/risc-v/src/mpfs/mpfs_serial.c: Correct setting of nbits 
Number of bits was set wrongly in TCSETS for mpfs

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2022-01-05 12:21:38 +08:00
Huang Qi
3a0e86c99b arch/risc-v: Replace __LP64__ with CONFIG_ARCH_RV64 
It can provide better auto complete experience for modern code editor,
since they use clang/gcc based parser to analyze code but lacks some
target dependent info such as __LP64__ for riscv64.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-04 23:22:43 +08:00
Eero Nurkkala
c87ae33459 risc-v/opensbi: update to version 1.0 
OpenSBI recently introduced version 1.0. Use the latest
version here as well.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2022-01-04 15:50:25 +08:00
Huang Qi
845168ce12 arch/risc-v: Refine riscv_assert.c 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-04 14:46:24 +08:00
Huang Qi
a6662c2887 arch/risc-v: Refine arch.h 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-04 14:46:24 +08:00
Gustavo Henrique Nihei
c04fbb0365 risc-v/esp32c3: Sort LIBC_ARCH_* configs alphabetically 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-01-03 10:37:04 -03:00
Petro Karashchenko
d23ad9b9b0 userspace: fix typos in comments 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-02 20:50:30 +01:00
Huang Qi
b11e90f384 arch/risc-v: Refine riscv_initialstate.c 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-02 01:21:48 +08:00
Gustavo Henrique Nihei
25f2dc2077 risc-v/esp32c3: Enable the creation of encrypted Flash partitions 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-01-01 20:37:44 +08:00
Gustavo Henrique Nihei
9e5e60ba48 esp32s2/esp32c3: Build MCUboot bootloader with Flash Encryption support 2022-01-01 20:37:44 +08:00
Norman Rasmussen
185de258bf Fix preprocessing directives for uart flow control 
commit 58bd873729 had a mix of
`#if defined(X)` and `#ifdef X`, but used `#if X` in its TCSETS ioctl
logic which causes compile warnings.
 2021-12-31 18:51:17 +08:00
Dong Heng
c56c58020a risc-v/esp32c3: SPI flash MTD device uses all flash space 2021-12-31 11:40:23 +08:00
Gustavo Henrique Nihei
74c02fbadb risc-v/esp32c3: Remove unavailable support for ROM Basic Console 
This feature is only available on ESP32 chips.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-12-31 00:56:08 +08:00
Huang Qi
33df35f003 arch/risc-v: Correct epc adjustment with C ISA 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-30 22:54:17 +09:00
chao.an
736add0fe8 arch/backtrace: correct the skip counter 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-30 16:57:40 +08:00
Jukka Laitinen
3beecbe905 risc-v/mpfs: Add MSSIO GPIO pinmap configuration 
Add a pinmap header for mpfs to be able to configure MSSIO GPIOs
This also adds Kconfigs for some different chip/package types of the PolarFire SOC

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-12-30 11:49:00 +08:00
Huang Qi
2de22980e5 arch/risc-v: Refine syscall interface 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-30 11:47:42 +08:00
Norman Rasmussen
091322ba4a Add backtrace to risc-v common sources 2021-12-30 01:30:08 +08:00
Huang Qi
c15195b126 arch/risc-v: Refine riscv_testset.S 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-29 06:06:01 -06:00
Huang Qi
901361be48 arch/risc-v: Move more files to common 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-29 01:19:30 -06:00
Huang Qi
22ae2e0121 arch/risc-v: Refine riscv_fpu.S 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-29 01:19:30 -06:00
chao.an
7ed0b97414 make/allsyms: skip the unnecessary link operation 
For incremental compilation, skip the stage 1 dummy link
operation if nuttx elf has been generated

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-28 23:47:10 -06:00
Xiang Xiao
dd942f0b04 sched/backtrace: Dump the complete stack regardless the depth 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-29 12:09:54 +08:00
Huang Qi
e75321e61c arch/risc-v: Move riscv_blocktask.c to common 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-28 11:32:15 -06:00
Norman Rasmussen
934a79736a Use userspace chosen channel numbers when starting bl602 pwm 
commit 2889315c20 added support for pwm
but didn't read the channel numbers provided by user-space. They should
be, otherwise it's not possible to start a sub-set of channels that are
not the first "n" channels.
 2021-12-28 06:27:51 -06:00
Huang Qi
d71cfc178a arch/risc-v: Remove unneeded kconfigs 
CONFIG_RV32IM_HW_MULDIV can be safely removed since this behavior is
controlled by M extension.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-28 05:02:42 -06:00
Norman Rasmussen
1e2f067181 pwm: add option to break the loops when using multiple PWM channels 
commit 7354ab187e added an option to break
the loops when using multiple PWM channels to arm pwm drivers. This adds
the same support to the risc-v pwm drivers.
 2021-12-28 03:01:27 -06:00
Huang Qi
c2e8c92b25 arch/risc-v: Refine Toolchain.defs 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-28 00:30:10 -06:00
chao.an
a42aa8415d compile/flags: add FRAME_POINTER into Toolchain.defs 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-27 22:31:27 -06:00
Petro Karashchenko
3ccb657dc2 nuttx: remove space befone newline in logs 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-27 21:01:19 -06:00
Eero Nurkkala
3394dca826 risc-v/opensbi: Make.defs: use a wildcard for file listing 
The source directory contents of the OpenSBI directory lib/sbi may be
listed with a one-line wildcard. This makes the Make.defs file look
simpler. The rest of the files need to be picked one at a time.

Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-12-23 02:42:09 -06:00
Eero Nurkkala
b128ce334f mpfs: introduce OpenSBI 
OpenSBI may be compiled as an external library. OpenSBI commit d249d65
(Dec. 11, 2021) needs to be reverted as it causes memcpy / memcmp to
end up in the wrong section. That issue has yet no known workaround.

OpenSBI may be lauched from the hart0 (e51). It will start the U-Boot
and eventually the Linux kernel on harts 1-4.

OpenSBI, once initialized properly, will trap and handle illegal
instructions (for example, CSR time) and unaligned address accesses
among other things.

Due to size size limitations for the mpfs eNVM area where the NuttX
is located, we actually set up the OpenSBI on its own section which
is in the bottom of the DDR memory. Special care must be taken so that
the kernel doesn't override the OpenSBI. For example, the Linux device
tree may reserve some space from the beginning:

  opensbi_reserved: opensbi@80000000 {
      reg = <0x80000000 0x200000>;
      label = "opensbi-reserved";
  };

The resulting nuttx.bin file is very large, but objcopy is used to
create the final binary images for the regions (eNVM and DDR) using
the nuttx elf file.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-12-22 20:48:12 -06:00
Eero Nurkkala
491ae6cc53 mpfs: cache: assign ways to L2 zero device 
Assign ways to L2 zerodevice. L2 zero device is used for
the scratchpad functionality. The area may be used for the
harts communicating to each other.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-12-22 20:48:12 -06:00
chao.an
362fe2c6f8 arch/risc-v: enhance the task dump 
add irq stack information
add cpu loading

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-22 11:46:02 -03:00
ChenWen
6d165506d5 risc-v/esp32c3: Initialize rtc and peripheral parameters by default when chip starts 2021-12-21 10:03:58 -03:00
Gustavo Henrique Nihei
c471f0fe96 risc-v/esp32c3: Remove deprecated note about Flash Detect feature 
Flash Detect option is already available on esptool.py installed via pip

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei
1c8e84b341 risc-v/esp32c3: Add Secure Boot support on top of MCUboot 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-12-21 07:02:40 -06:00
Petro Karashchenko
3e76c3266e assert: unify stack and register dump across platforms 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-20 00:02:12 -03:00
Petro Karashchenko
67d8a82393 Kconfig: fix non-string default values uniformity 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-20 00:10:57 +01:00
xiewenxiang
b1d051b651 riscv/esp32c3: Initialize the BLE Mac 2021-12-16 22:31:02 -03:00
chao.an
b11833cbba arch/assert: flush the syslog before stack dump 
flush the syslog before stack dump to avoid buffer overwrite

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-15 12:00:35 -06:00
Petro Karashchenko
51a2db6ffc Kconfig: improve uniformity 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-14 07:32:48 -06:00
Petro Karashchenko
af614ac77d tls: restore C89 compatibility for TLS 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-13 21:14:53 -06:00
chao.an
c2fd66bfab arch/arm/risc-v/xtensa: add support of all symbols for debugging 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-13 08:31:13 -06:00
chao.an
89e2f00dad arch/assert: fix the stack dump overflow 
[ EMERG] kasan_report: kasan detected a read access error, address at 0x3c24fca8, size is 4
[ EMERG] up_assert: Assertion failed at file:kasan/kasan.c line: 104 task: init
[ EMERG] backtrace|10:  0x2c334666 0x2c35f0d6 0x2c359ef6 0x2c35f830 0x2c360ed4 0x2c3615c0 0x2c324e0c 0x2c30a168
[ EMERG] up_registerdump: R0: ffffffff R1: 00000004 R2: ffffffff R3: ffffffff
[ EMERG] up_registerdump: R4: 3c20d4f0 R5: 2c35acd5 R6: 00000000 FP: 3c24fae8
[ EMERG] up_registerdump: R8: 3c20d504 SB: ffffffff SL: 2c413e7c R11: 2c411eb8
[ EMERG] up_registerdump: IP: 00000002 SP: 3c24fae8 LR: 00000003 PC: 2c35f0d6
[ EMERG] up_registerdump: xPSR: 61010000 BASEPRI: 000000e0 CONTROL: 00000004

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-13 01:43:18 -06:00
lupyuen
2a87b37a69 riscv/bl602: Swap SPI MISO and MOSI 2021-12-12 20:40:49 -06:00
Huang Qi
8ce3337e85 arch/risc-v: Implement TLS support 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-12 10:19:00 -06:00
Xiang Xiao
6357523892 arch: Add _wchar_t typedef like other basic types 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-09 16:57:23 +09:00
Huang Qi
63ab2f4308 arch/risc-v: Introduce basic support for qemu rv32 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-07 23:28:33 -06:00
chao.an
437a30d117 arch/tcbinfo: fix build break if task name disabled 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-06 00:47:58 -06:00
Dong Heng
698f1f76ff risc-v/esp32c3: Refactor SPI Flash to support umask interrupt when R/W/E SPI Flash 
This can fix BLE assert when erase SPI Flash.
 2021-12-06 13:13:11 +09:00
Xiang Xiao
a0990ee416 arch: Remove the duplicated up_tls_info implementation 
Define up_tls_info in arch/arch.h directly if the general one isn't suitable

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-05 20:59:53 -06:00
Xiang Xiao
19e5ee6ce0 arch: Remove FILE dump code from _up_dumponexit 
since the kernel build can't access the userspace memory
inside other process directly

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-06 11:23:58 +09:00
Xiang Xiao
b65c7c26cf arch: Dump task name through tcb_s::name instead of argv[0] 
since argv is defined in task_tcb_s not tcb_s

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-01 16:04:15 +01:00
Abdelatif Guettouche
251b8a3445 esp32xx_rtc: Include "clock/clock.h" to have a declaration of 
g_basetime.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-26 15:23:47 -03:00
Abdelatif Guettouche
af11cf6cd1 esp32xx_rtc.c: Fix a duplicated assignment. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-26 15:23:47 -03:00
Dong Heng
66023da10c risc-v/esp32c3: Refactor ADC calibration 
Use calibration parameters from efuse rather than self-calibration.
 2021-11-26 15:23:24 -03:00
Jani Paalijarvi
4dfd3c9160 arch/riscv: Add ARCH_HAVE_SPI_CS_CONTROL for mpfs 
Make it possible to override SPI CS function in board logic

Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-11-24 06:50:32 -06:00
Lee Lup Yuen
6e68d55f8a Fix GPIO output 2021-11-24 06:48:50 -06:00
Jani Paalijarvi
6dd4d5de15 risc-v/mpfs: Add support for Aries M100PFSMVP board 
- Add defconfig and board specific files
- Create mpfs/common for code which is shared between MPFS boards.
- Add support for GPIO driven EMMCSD mux.
- Move DDR Libero definitions from arch to boards.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
 2021-11-18 10:59:44 -03:00
Eero Nurkkala
6db480a7f9 mpfs: emmcsd: boost waitresponse perf 
When waiting for a response to a sent command, the command
complete bit (MPFS_EMMCSD_SRS12_CC) should always guarantee
the completion of that particular command. There's no need
to have some combinations skipping the check of the command
complete bit. Thus, remove the 'waitbits' parameter as it's
unnecessary.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-11-16 10:25:57 -06:00
Dong Heng
92eedd93a7 risc-v/esp32c3: Fix reset triggering crash nested when crash 2021-11-16 10:44:54 -03:00
Abdelatif Guettouche
5a41572fd0 esp32c3/esp32c3_usbserial.c: Initialize cpuint to ENOMEM, otherwise the 
first attempt to attaching an interrupt will trigger an assertion.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-15 12:11:45 -06:00
Xiang Xiao
2262ddfa6d arch: Remove fflush(stdout) from driver code 
it's wrong to call stdio function inside driver

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-11-15 00:04:12 +01:00
Abdelatif Guettouche
6cbcbd5481 arch/risc-v&xtensa/Kconfig: Don't select LIBC_ARCH_MEMCCMP. The Kconfig 
option doens't exist and we are not providing any external
implementation.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-13 11:54:42 -03:00
Abdelatif Guettouche
a01cb867ce esp32c3_rom.ld: Add some of the string.h functions to the linker 
script.

These functions are strongly declared and thus will be used instead of
any other implementation.  Furthermore, necessary Kconfig options are
selected to avoid building those function from NuttX's C library.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-13 11:54:42 -03:00
Dong Heng
fed7808d80 esp32 & esp32c3: Partition supports BIO cmd 2021-11-13 05:58:30 -06:00
Dong Heng
f5c5d77744 risc-v/esp32c3: Add hardware brownout check and reset 2021-11-12 16:50:19 -03:00
Eero Nurkkala
876b39914b mpfs: uart: add a way to configure uart3 and uart4 
Currently configuring the uart3/4 as the serial console
doesn't work. Apply proper changes in mpfs_config.h that
enables the following configuration options:

 - CONFIG_UART3_SERIAL_CONSOLE
 - CONFIG_UART4_SERIAL_CONSOLE

Also, fix a typo in mpfs_lowputc.c that gives a compile
error if defined.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-11-11 06:02:27 -06:00
zhuyanlin
012bd1494c arch:debug: add struct for task aware debug. 
When enable DEBUG_TCBINFO config, a global struct will
provide, then debuggers can aware nuttx task infomation.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-11-10 14:31:10 -03:00
Alan C. Assis
b8c33e585e esp32c3: Fix GPIO Output on pins 18 and 19 USB/JTAG 2021-11-09 20:54:34 -06:00
Abdelatif Guettouche
23039c92cf esp32c3/Make.defs: Alawys build esp32c3_serial.c 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-09 09:22:57 -03:00
Abdelatif Guettouche
ebd94961c7 arch/riscv/esp32c3: Add the USB-Serial Driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-09 09:22:57 -03:00
Abdelatif Guettouche
17cf3edf46 arch/risc-v/esp32c3: Add register definitions for the USB Serial/JTAG 
controller.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-09 09:22:57 -03:00
Dong Heng
a59aae6927 esp32/esp32c3: Fix MMU pages number calculation error 2021-11-07 21:59:54 -06:00
David Sidrane
040a04241e drivers/spi:Define SPI_~CS~_DELAY_CONTROL to support other delays 2021-11-06 05:14:05 -05:00
Eero Nurkkala
f8832f7d86 mpfs: emmcsd: fix uninitialized value 
cppcheck reports the following:

arch/risc-v/src/mpfs/mpfs_emmcsd.c:2375:22: error: Uninitialized variable: waitbits [uninitvar]
  while (!(status & (waitbits | MPFS_EMMCSD_SRS12_EINT))

The finding is positive and this patch initializes it to
zero properly.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-11-05 11:47:49 +01:00
ChenWen
440787c0c1 risc-v/esp32c3: Fix Wi-Fi & BLE coexist issue 
1. Wi-Fi and BLE use common PHY functions.
  2. Fix Wi-Fi & BLE coexist adapter error.
  3. Update esp-wireless-drivers-3rdparty, provide coexist protection for connection.
 2021-11-04 11:02:05 -03:00
ChenWen
65d7f4bfb3 riscv/esp32c3: Support more country codes 2021-11-04 11:02:05 -03:00
ChenWen
4fc2f6e28c riscv/esp32c3: Support debug log configuration for Wi-Fi library 2021-11-04 11:02:05 -03:00
ChenWen
02968cc124 risc-v/esp32c3: Improve Wi-Fi connection success rate 2021-11-04 11:02:05 -03:00
ChenWen
222ec556d5 riscv/esp32c3: Fix some Wi-Fi issues 
1. Fix the issue that Wi-Fi can't connect to some special routers occasionally.
  2. Support Wi-Fi 12/13 channel active scanning by default.
  3. Update Wi-Fi driver code to fix issue of failure to send pkt.
  4. Replace software random with hardware random
  5. Fix Wi-Fi mode start error
 2021-11-04 11:02:05 -03:00
chenwen
33031a2813 riscv/esp32c3: Fix the issue of Wi-Fi automatic disconnection 2021-11-04 11:02:05 -03:00
chenwen
afbad5ca9d riscv/esp32c3: Clear station configuration when connection fails or disconnect 2021-11-04 11:02:05 -03:00
Eero Nurkkala
8e43f39141 mpfs: cache: provide L1/L2 cache enablers 
E51 may configure the L1 and L2 caches. Once configured,
no reconfiguration is possible after hardware reset is
issued.

L2 is 16-way set associative with write-back policy. The
size 2 MB, from which 1 MB is utilized with the values
provided here. That's a total of 8 ways. The rest of the
L2 is left out for the bootloader usage.

mpfs_enable_cache() first checks the bootloader usage
doesn't overlap with the cache itself, thus providing a
set of functional values.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-11-04 11:00:55 -03:00
Jani Paalijarvi
a16a9f80e2 mpfs: i2c: Add support for adaptive I2C bus frequency 
Select the closest possible frequency which is smaller
than or equal to requested in I2C msg
 2021-11-02 04:10:08 -05:00
Abdelatif Guettouche
860370284e esp32c3_dma: Remove the DMA test included in the driver along with its 
defconfig.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-01 13:49:59 -05:00
Gustavo Henrique Nihei
06bb85d8a5 risc-v/esp32c3: Rename MTD-related configs to become more intuitive 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 21:45:20 -05:00
Gustavo Henrique Nihei
eb7ffd014e risc-v/esp32c3: Enable Partition Table allocation at custom offset 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei
211f899b62 risc-v/esp32c3: Refactor and reorganize Partition Table related configs 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei
793266d39e espressif: Fix spacing style in Kconfig files 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 08:01:44 -05:00
Gustavo Henrique Nihei
4ff754827c espressif: Fix prompt string of Wi-Fi FS mount point configs 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 08:01:44 -05:00
Gustavo Henrique Nihei
a1af605973 espressif: Fix references to Wi-Fi according to Wi-Fi Alliance 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 08:01:44 -05:00
Eero Nurkkala
e57f3f7a3a mpfs: emmcsd: provide proper internal emmc settings 
So far the SD-card functionality has been tested with
the driver. Now, also the internal eMMC has been tested
working with this patch. This patch applies IOMUX and
clock settings that have been tested working with the
internal eMMC in the Polarfire Icicle kit.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-10-21 22:41:08 -05:00
Eero Nurkkala
c34b9620db mpfs: clockconfig: add clock initialiation sequence 
Add clock initialization sequence especially for systems
containing no bootloader.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-10-21 22:40:26 -05:00
Eero Nurkkala
bc72ccdf6a mpfs: Kconfig/Make: add DDR support flag 
This adds the proper flag for introducing the DDR
support. Also call the mpfs_ddr_init() at the
proper location.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-10-21 22:40:26 -05:00
Eero Nurkkala
3b330089d5 mpfs: ddr: add DDR training 
This adds DDR training. The training has a small chance of failing,
and then the training is restarted.

DDR training cannot be done meaningfully while the software is
in DDR. If the system is intended to run from eNVM, like a
bootloader, the linker script should be tuned to utilize the envm
region as follows:

  envm (rx)   : ORIGIN = 0x20220100, LENGTH = 128K - 256
  l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k

256 bytes are reserved for the system; The fixed block may be
installed from the 'hart-software-services' -repository:
https://github.com/polarfire-soc/hart-software-services.git

For example, the 256-byte image: hss-envm-wrapper-bm1-dummySbic.bin
may be prepended on the nuttx bootloader image in the following
manner:

 cat hss-envm-wrapper-bm1-dummySbic.bin > nuttx_bootloader.bin
 cat nuttx.bin >> nuttx_bootloader.bin
 riscv64-unknown-elf-objcopy -I binary -O ihex --change-section-lma
  *+0x20220000 nuttx_bootloader.bin flashable_image.hex

This provides an image 'flashable_image.hex' that may be flashed on
the eNVM region via Microsemi Libero tool.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-10-21 22:40:26 -05:00
Jukka Laitinen
c5b11f42b6 mpfs_head.S: Support for booting on different harts and from eNVM 
- Fix the FPU enabling code
- If booting from eNVM, all harts start booting. With CONFIG_MPFS_BOOTLOADER,
  one can allow just one hart booting and rest are stuck in wfi.
- Check that mtvec is actually updated before continuing the boot
- Create 5 IRQ stacks, one for each hart

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-10-21 22:40:26 -05:00
Jukka Laitinen
37761c293d mpfs_head.S: Fixes for booting on different harts 
- Jump to mpfs_start with mhartid in a0 as the comment says
- Don't invalidate mmu tlb on e51 (it doesn't have mmu)
- Fix FPU initialization flags on e54 (it fires IRQ5 and crashes)

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-10-21 22:40:26 -05:00
Jukka Laitinen
e5843db282 mpfs: Add configuration flags to configure NuttX booting on single hart 
The bootloader hart also configures the needed clocks and peripherals.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-10-21 22:40:26 -05:00
Eero Nurkkala
d909b0f635 mpfs: hardware/memorymap: add more base addresses 
Add a number of missing base addresses.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-10-21 22:40:26 -05:00
Abdelatif Guettouche
018aa8eb8d esp32c3_serial.c: Remove the stub implementations of the early serial 
functions as they are only called when the configuration is enabled.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-20 10:22:10 -03:00
Abdelatif Guettouche
c83c1071cc esp32c3_bignum.c & esp32c3_sha.c: Fix some trivial nxstyle complaints. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
e424241d09 arch/risc-v/esp32c3: Remove the bignum test from the driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
91cb9dafaf arch/risc-v/esp32c3: Remove the RSA test from the driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
652d77efd2 arch/risc-v/esp32c3: Remove the SHA test from the driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
5d1c01aea7 arch/risc-v/esp32c3: Remove the AES test from the driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
7549de49b4 arch/*_cpupause:Allow a spin before taking the g_cpu_wait spinlock. 
If we repeatedly call up_cpu_pause and up_cpu_resume, there would be
cases where the next call to up_cpu_pause happens while the other CPU is
still responding to the previous resume request. In this case the
DEBUGASSERT will trigger. We should allow the first CPU to wait until the
other CPU has finished responding to the resume request.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-17 21:10:23 +09:00
Gustavo Henrique Nihei
99ac065d0a risc-v/esp32c3: Provide SPI Flash parameters to MCUboot build 
Also unify bootloader config creation to reduce duplication.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei
cc78541966 risc-v/esp32c3: Add esp-nuttx-bootloader folder to gitignore list 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei
ae25ebce4c risc-v/esp32c3: Fix wrong arch in the path to chip folder 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
jsun
c58fddb915 Open ble controller adaptation code 
N/A

Signed-off-by: jsun <jsun@bouffalolab.com>
 2021-10-08 02:30:27 -07:00
Gustavo Henrique Nihei
47e804b167 risc-v/esp32c3: Make BLE adapter code compliant to nxstyle 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-05 08:45:40 -03:00
Abdelatif Guettouche
d22b4ec539 espxx_rng.c: Add "/" at the beginning of paths for consistency. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
Abdelatif Guettouche
c811cefa2d esp32c3_rng.c: Remove unused functions. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
Sara Souza
33f2d46bff risc-v/esp32-c3/rttimer: Disable alarm before setting a new value and enabling it 2021-09-28 21:02:57 -03:00
Alin Jerpelea
15a37c5a5a arch: Omni Hoverboards: update licenses to Apache 
Gregory Nutt has submitted the SGA
Omni Hoverboards has submitted the SGA
David Sidrane has submitted the ICLA
Mateusz Szafoni has submitted the ICLA
Sebastien Lorquet has submitted the ICLA
Paul Alexander Patience has submitted the ICLA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-09-28 04:37:38 -07:00
Gustavo Henrique Nihei
20341e6f17 risc-v/esp32c3: Enable support for "make bootloader" target 
This enables the provisioning of the bootloader binaries through the
build system.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-27 18:22:29 -07:00
Gustavo Henrique Nihei
3c63cb522c risc-v/esp32c3: Enable booting from MCUboot bootloader 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-27 18:22:29 -07:00
Sara Souza
9c2c5d3919 risc-v/esp32-c3: fix pid initiatialization on esp32c3_rt_timer.c 
pid variable was initialized to -EINVAL to prevent rt_timer_deinit
from delete an invalid kthread. But priv->pid was being overwritten in the
rt_timer_init, so in case of failure to create a kthread, it would
call rt_timer_deinit with a non expected initialization value.
 2021-09-23 19:01:27 -07:00
Sara Souza
d0e7d7b77f risc-v/esp32-c3: Remove _s of non static variables from esp32c3_rt_timer.c 2021-09-23 19:01:27 -07:00
Gustavo Henrique Nihei
e651ef0969 arch/risc-v: Remove CODE qualifier for RISC-V-specific files 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei
06f4ee850a arch/risc-v: Remove FAR qualifier for RISC-V-specific files 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei
e9c17c9332 risc-v/rv32m1: Fix wrong position for ++ operator on serial driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Sara Souza
fc12d6888b risc-v/esp32-c3: Group static variables into a struct and prevent an unitialized thread to be deleted 2021-09-21 15:45:59 +02:00
Eero Nurkkala
812f504c16 mpfs: emmcsd: add Kconfig/Makefile and board files 
Add necessary Kconfig, Make.defs, Makefile and board
file changes.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-09-18 12:18:09 -03:00
Eero Nurkkala
772432e7c3 mpfs: add emmcsd driver 
This adds the emmcsd driver for the Polarfire Icicle kit.
The driver has been tested with several SD-cards, such as:

 - Kingston 32 GB SDS2 Canvas Select Plus
 - Kingston MicroSD Canvas Select Plus
 - Sandisk Extreme PRO 32 GB
 - Transcend 8 GB MicroSD

The internal eMMC hasn't been tested comprehensively.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-09-18 12:18:09 -03:00
Xiang Xiao
71c61b11d9 arch/riscv: Rename riscv_puts to up_puts 
since it's a common API defined in include/nuttx/arch.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-18 07:33:44 -03:00
jsun
f4b6bb281c Update bl602 MTU_SIZE and TX_BUF_SIZE 
N/A

Signed-off-by: jsun <jsun@bouffalolab.com>
 2021-09-17 22:11:30 -05:00
jsun
d489392d08 Add bl602 os adapter layer 
N/A

Signed-off-by: jsun <jsun@bouffalolab.com>
 2021-09-17 22:11:30 -05:00
Gustavo Henrique Nihei
52cea558af risc-v/esp32c3: Make the semaphore timeout on I2C configurable 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-16 14:07:26 -03:00
Peter Bee
2a8b076b38 risc-v/esp32c3: fix pwm driver bug 
Wrong offset sign and pwm multichan fix

Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
 2021-09-16 08:38:49 -03:00
Jukka Laitinen
3654db3517 mpfs: Modify IRQ handling to support also HART0 on PF 
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-09-11 23:33:01 +08:00
Janne Rosberg
8b560e7894 mpfs/i2c: fix bus initialize for i2c1 2021-09-11 23:33:01 +08:00
Janne Rosberg
1e3919e55a mpfs/corepwm: remove wrong header include 2021-09-11 23:33:01 +08:00
Janne Rosberg
7db3456824 risc-v/mpfs: serial: add termios support and init device clocks 2021-09-11 23:33:01 +08:00
Janne Rosberg
aa057e25f2 mpfs/i2c: adapt to sysreg define changes 2021-09-11 23:33:01 +08:00
Janne Rosberg
dc54ba924e mpfs/spi: adapt to sysreg define changes 2021-09-11 23:33:01 +08:00
Janne Rosberg
3e6b19dfc5 risc-v/mpfs: add more sysreg defines and fix clock and reset defines 2021-09-11 23:33:01 +08:00
Sara Souza
acf18bd82d risc-v/esp32-c3: refactor the Wi-Fi board logic. 
This commit moves the Wi-Fi initialization to
Wi-Fi specific file and to spiflash initialization.

It also reserves one partition for Wi-Fi use and for general use,
and makes it possible to me mounted by several FS.
 2021-09-09 20:14:04 +08:00
Sara Souza
11068fad1b risc-v/esp32-c3: Enable the allocation of multiple MTD SPI Flash partitions 2021-09-09 20:14:04 +08:00
Jukka Laitinen
1b75b5d5aa Fix compilation of arm protected build 
Correct typos in include/nuttx/arch.h and suppress
"'noreturn' function does return" warning coming from arm_pthread_exit.c

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-09-07 00:31:47 +08:00
Alin Jerpelea
da92258333 arch: k210: remove extra license information 
the Apache license header uses a standard format and the extra information
should be removed.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-08-31 08:20:18 +09:00
Xiang Xiao
b0c782255c libxx: Change CXX_LIBSUPCXX to LIBSUPCXX 
align with other Kconfig(e.g. LIBCXXABI, LIBCXX, UCLIBCXX)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-28 17:14:48 -03:00
zhuyanlin
cd18d1f050 arch:riscv: remove arch atomic, use libc atomic when need 
It is more common for implement in libc/machine

Change-Id: I3da6c3db64adb78c05ddb26d3956817ac6ada93e
 2021-08-28 13:17:30 -03:00
Abdelatif Guettouche
5ff703d5d0 arch/*_testset: Fix few typos. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-25 00:20:20 +08:00
chao.an
68d6dbf86f arch/riscv/assert: enhance the assert dump 
enhance the assert dump to show the all tasks info including backtrace and registers

[    7.617000] [ EMERG] up_assert: Assertion failed at file:rv32im/riscv_exception.c line: 94 task: init
[    7.617000] [ EMERG] riscv_dumpstate: Call Trace:
[    7.617000] [  INFO] [BackTrace| 3|0]:  0x4202001e 0x42007cb4 0x42005782 0x42000fe2 0x403801e2 0x403800e2 0x4200bdd0 0x42009894
[    7.617000] [  INFO] [BackTrace| 3|1]:  0x4200a62e 0x42008e8a 0x4200841e 0x42008320 0x42005ad0 0x42001a56
[    7.617000] [ EMERG] riscv_registerdump: EPC:4200bdd0
[    7.617000] [ EMERG] riscv_registerdump: A0:ffffffff A1:00000010 A2:3fc9a95c A3:00000031 A4:00000009 A5:00000002 A6:00000001 A7:00000074
...
...
[    7.617000] [ EMERG] riscv_showtasks: Tasks status:
[    7.617000] [ EMERG] riscv_taskdump: Idle Task: PID=0
[    7.617000] [ EMERG] riscv_taskdump: Stack Used=596 of 976
[    7.617000] [  INFO] [BackTrace| 0|0]:  0x4200787e 0x3fc94ff0
[    7.617000] [ EMERG] riscv_registerdump: EPC:4200787e
[    7.617000] [ EMERG] riscv_registerdump: A0:00000032 A1:3c1008fa A2:3fc94fa8 A3:00000000 A4:00000101 A5:00000032 A6:00000001 A7:00000074
...
[    7.617000] [ EMERG] riscv_taskdump:
[    7.617000] [ EMERG] riscv_taskdump: hpwork: PID=1
[    7.617000] [ EMERG] riscv_taskdump: Stack Used=292 of 2016
[    7.617000] [  INFO] [BackTrace| 1|0]:  0x420082a6 0x4200328c 0x42001ab4 0x42001a42
[    7.617000] [ EMERG] riscv_registerdump: EPC:420082a6
[    7.617000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fc98718 A2:3fc8307c A3:00000002 A4:00000000 A5:00000000 A6:00000000 A7:00000000
...

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-21 14:58:21 +08:00
chao.an
333191becd riscv/backtrace: add up_backtrace support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-21 14:56:34 +08:00
Xiang Xiao
af72376773 fs: Remove magic field from partition_info_s 
since it is wrong and impossible to return file
system magic number from the block or mtd layer.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-20 09:19:52 -03:00
Antti Vähälummukka
6eb73ced51 arch/risc-v/src/mpfs: Add CorePWM driver 
Add a driver for CorePWM block, which can be instantiated on PolarFire SOC FPGA

This supports 2 CorePWM blocks on the FPGA. One CorePWM block provides 8 PWM output signals
 2021-08-20 08:56:30 -03:00
chao.an
e37d8da074 riscv/common: add CURRENT_REGS declare in RV32 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-18 04:40:38 -07:00
Xiang Xiao
71269811ca mtd: Implement BIOC_PARTINFO for all drivers 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-16 10:08:26 -03:00
Virus.V
5a1de89370 riscv/bl602: Fix that AP cannot be start when STA have been started. 2021-08-16 02:06:59 -07:00
Abdelatif Guettouche
5b350f3a0f arch/*_reprioritizertr.c: Fix typos in comments. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-14 11:19:34 -07:00
Xiang Xiao
d1687418db mtd: Remove the empty MTDIOC_XIPBASE implmentation 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-11 09:50:51 -03:00
Abdelatif Guettouche
054e284785 *_cpustart.c: Fix typos in function description. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-11 11:06:27 +09:00
Sara Souza
af6c311fd1 risc-v/esp32-c3: Complete the support for RWDT 2021-08-10 11:17:15 -03:00
Xiang Xiao
5d1a444812 Replace __attribute__ ((unused)) with unused_code 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
69df58c2e8 Replace __attribute__((no_instrument_function)) with noinstrument_function; 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
007adc7736 Replace all __attribute__((section(x)) with locate_data(x) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
b3f9ffbe72 Replace all __attribute__((aligned(x)) with aligned_data(x) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Sara Souza
cdbfacc1fe risc-v/esp32-c3: Adds systimer support and make rt_timer rely on it 2021-07-27 20:43:34 -07:00
Michal Lenc
9fc806984c adc: add ioctl command to get the number of configured channels 
Number of configured ADC channels is currently only defined in board
level section, typically in xxx_adc.c file. This commit introduces
ioctl command ANIOC_GET_NCHANNELS that returns the number of configured
channels which is determined by the driver code. The change can allow the
applications to be more flexible when it comes to multiple ADC devices
with different number of configured channels.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-07-26 19:45:47 -07:00
Sara Souza
0794991a07 risc-v/esp32-c3: Disable wdt in the start function. 2021-07-26 19:44:30 -07:00
Nathan Hartman
b92aeb8209 Fix various typos 
arch/arm/src/eoss3/eoss3_serial.c:
arch/arm/src/imxrt/hardware/imxrt_flexcan.h:
arch/arm/src/imxrt/imxrt_flexcan.c:
arch/arm/src/imxrt/imxrt_flexpwm.c:
arch/arm/src/imxrt/imxrt_lpi2c.c:
arch/arm/src/kinetis/kinetis_flexcan.c:
arch/arm/src/nrf52/hardware/nrf52_rtc.h:
arch/arm/src/nrf52/nrf52_clockconfig.c:
arch/arm/src/nrf52/nrf52_radio.c:
arch/arm/src/nrf52/nrf52_tim.c:
arch/arm/src/rtl8720c/amebaz_depend.c:
arch/arm/src/s32k1xx/Kconfig:
arch/arm/src/s32k1xx/s32k1xx_flexcan.c:
arch/arm/src/s32k1xx/s32k1xx_lpi2c.c:
arch/arm/src/sama5/hardware/sam_sdmmc.h:
arch/arm/src/sama5/sam_gmac.c:
arch/arm/src/samd5e5/sam_wdt.c:
arch/avr/src/avr32/up_exceptions.S:
arch/avr/src/avr32/up_fullcontextrestore.S:
arch/renesas/src/rx65n/rx65n_dtc.c:
arch/renesas/src/rx65n/rx65n_usbhost.c:
arch/risc-v/src/esp32c3/esp32c3_tickless.c:
boards/arm/stm32h7/stm32h747i-disco/include/board.h:
include/nuttx/lcd/ili9225.h:
libs/libc/stdio/lib_fgetpos.c:
libs/libc/stdio/lib_fseek.c:
libs/libc/stdio/lib_fsetpos.c:

    * Fix typos.
 2021-07-25 18:36:53 -07:00
jordi
f3af6edf93 Kconfig: add quotes in source to clean warnings from setconfig 
To avoid the setconfig warning "style: quotes recommended around xxx in
source xxx"
 2021-07-23 02:32:19 -07:00
Abdelatif Guettouche
e85b119363 arch/: Clean what was made during context in distclean. 
Cleaning during `clean_context` had the issue of remaking everything
when `menuconfig` was issued.  That's because `menuconfig` has a
`clean_context` on its way.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-07-21 16:52:36 -03:00
Gustavo Henrique Nihei
c05feda208 risc-v/esp32c3: Implement MTDIOC_ERASESTATE for SPI Flash driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-07-17 09:00:41 -07:00
Xiang Xiao
98b5724b59 arch: Fix rtcb can't found error 
use the same condition check in declaration and reference

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I7b05316e914708fceeddac394d784ee3720a3c1b
 2021-07-16 12:48:09 -03:00
ChenWen
2abb75fee7 risc-v/esp32c3: Fix some ESP32-C3 Wi-Fi driver issues 2021-07-15 23:20:29 -07:00
Virus.V
063e1d6b74 risc-v/bl602: update wifi firmware and some fixup. 
1. Added check for repeated connection wifi operations.
2. Invoke the carrier on/off operation in the wrong place.
3. The RTC initialization time is incorrect.
4. Reserve 32K I-Cache space in the linker script.
5. Increase the size of the wifi firmware receiving buffer.

Signed-off-by: Virus.V <virusv@live.com>
 2021-07-13 05:12:12 -07:00
Sara Souza
48f2b10ee3 risc-v/esp32-c3: Use systimer 0 to RTOS TICK 2021-07-12 21:03:27 -07:00
Dong Heng
f5eaf82c93 risc-v/esp32c3: Use onexit to free thread private semaphore 2021-07-12 09:38:21 -03:00
Xiang Xiao
76cdd5c329 mm: Remove mm_heap_impl_s struct 
it's more simple to make mm_heap_s opaque outside of mm

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I5c8e435f6baba6d22b10c5f7e8d9191104fb5af2
 2021-07-07 04:25:15 -07:00
Dong Heng
475becac37 risc-v/esp32c3: Add board_ioctl and board_uniqueid 2021-07-05 23:12:17 -05:00
Nathan Hartman
ce20211357 Fix various typos in comments and documentation 
Fix typos in these files:
    * Documentation/components/drivers/character/foc.rst
    * Documentation/guides/cpp_cmake.rst
    * Kconfig
    * arch/arm/src/imxrt/imxrt_lpspi.c
    * arch/arm/src/kinetis/kinetis_spi.c
    * arch/arm/src/kl/kl_spi.c
    * arch/arm/src/lpc31xx/lpc31_spi.c
    * arch/arm/src/nrf52/nrf52_radio.h
    * arch/arm/src/s32k1xx/s32k1xx_lpspi.c
    * arch/arm/src/stm32/Kconfig
    * arch/arm/src/stm32/stm32_adc.c
    * arch/arm/src/stm32/stm32_foc.c
    * arch/arm/src/stm32/stm32_foc.h
    * arch/arm/src/stm32/stm32_pwm.c
    * arch/arm/src/stm32/stm32_spi.c
    * arch/arm/src/stm32f0l0g0/stm32_spi.c
    * arch/arm/src/stm32f7/Kconfig
    * arch/arm/src/stm32f7/stm32_spi.c
    * arch/arm/src/stm32h7/Kconfig
    * arch/arm/src/stm32h7/stm32_allocateheap.c
    * arch/arm/src/stm32h7/stm32_fmc.c
    * arch/arm/src/stm32h7/stm32_fmc.h
    * arch/arm/src/stm32h7/stm32_pwm.c
    * arch/arm/src/stm32h7/stm32_qspi.c
    * arch/arm/src/stm32h7/stm32_spi.c
    * arch/arm/src/stm32l4/stm32l4_pwm.c
    * arch/arm/src/stm32l4/stm32l4_spi.c
    * arch/arm/src/stm32l5/Kconfig
    * arch/arm/src/stm32l5/stm32l5_spi.c
    * arch/renesas/src/rx65n/rx65n_dtc.c
    * arch/renesas/src/rx65n/rx65n_usbdev.c
    * arch/risc-v/src/rv32m1/rv32m1_serial.c
    * boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c
    * boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c
    * boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c
    * boards/arm/stm32h7/nucleo-h743zi2/README.txt
    * boards/risc-v/rv32m1/rv32m1-vega/README.txt
    * boards/sim/sim/sim/scripts/Make.defs
    * drivers/1wire/1wire.c
    * drivers/1wire/1wire_internal.h
    * drivers/lcd/Kconfig
    * drivers/syslog/ramlog.c
    * fs/fat/Kconfig
    * libs/libc/debug/Kconfig
    * libs/libc/machine/Kconfig
    * libs/libc/stdio/lib_libvsprintf.c
    * libs/libc/stdlib/lib_div.c
    * libs/libc/stdlib/lib_ldiv.c
    * libs/libc/stdlib/lib_lldiv.c
    * libs/libdsp/lib_observer.c
 2021-07-04 11:23:26 -05:00
Xiang Xiao
b1f711f790 mm: Move procfs_register_meminfo into common place 
to avoid the code duplication and ensure the consistent behaviour

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-03 09:39:32 -07:00
Dong Heng
4f2df0311d risc-v/esp32c3: Fix some BLE driver issues 
1. remove SMP functions because ESP32-C3 is singal core
2. disable phy_printf in ble adapter when enable Wi-Fi
3. fix BLE character device macro
 2021-07-03 07:28:30 -05:00
Virus.V
5f67d65e9e risc-v/bl602: add efuse driver 
Signed-off-by: Virus.V <virusv@live.com>
 2021-07-02 13:17:39 -05:00
chenwen
31a6da2343 risc-v/esp32c3: Notifies networking layer whether the carrier is available 2021-06-30 23:09:34 -05:00
Virus.V
84100128b2 risc-v/bl602: update wifi firmware version 
Signed-off-by: Virus.V <virusv@live.com>
 2021-06-30 01:08:10 -05:00
xiewenxiang
5fd3eca9c9 riscv/esp32c3: Support BLE sleep mode 2021-06-28 23:14:30 -05:00
xiewenxiang
145d917587 riscv/esp32c3: Add Wi-Fi and BLE coexist 2021-06-28 23:14:30 -05:00
xiewenxiang
8b96edc3a5 riscv/esp32c3: Add esp32c3 BLE driver 2021-06-28 23:14:30 -05:00
Virus.V
8452c571ec risc-v/bl602: BLE firmware adapts to the new framework 
Signed-off-by: Virus.V <virusv@live.com>
 2021-06-28 07:03:04 -05:00
Virus.V
cd50650583 risc-v/bl602: Support AP and STA as independent network interface device 
Signed-off-by: Virus.V <virusv@live.com>
 2021-06-28 07:03:04 -05:00
Abdelatif Guettouche
add18b9592 arch/risc-v/esp32c3: Remove the up_textheap_init function since it's not 
needed anymore.

Implement the up_extraheaps_init function to initialize all separate
heaps.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-26 09:52:43 -05:00
Abdelatif Guettouche
60da4317b9 arch/risc-v/esp32c3: Use the same naming for the RTC heap as ESP32 for 
consistency.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
bdbc9ef04f arch/risc-v/esp32c3_rtc_heap.c: Correct the name of the procfs info 
variable.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-23 08:37:01 +09:00
Liu Han
2dd081ed7d risc-v/esp32c3: Support ESP32-C3 SHA accelerator 2021-06-21 02:41:53 -05:00
chenwen
8648970994 esp32&esp32c3/wifi: Fix the issues of Wi-Fi configuration being overwritten 2021-06-19 08:00:35 -03:00
chenwen
ee3350ed1d risc-v/esp32c3: Disable Wi-Fi reconnect by default 2021-06-19 08:00:35 -03:00
Xiang Xiao
ab974edc84 sched: Identify the stack need to free by TCB_FLAG_FREE_STACK 
instead calling kmm_heapmember or umm_heapmember because:
1.The stack supplied by caller may allocate from heap too
2.It's hard to implement these two function in ASan case

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I196377822b7c4643ab4f29b7c1dc41dcd7c4dab1
 2021-06-18 05:44:41 -07:00
Abdelatif Guettouche
af5e0c620f Rename MODULE_TEXT to TEXT_HEAP as the latter is more generic. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-18 07:14:17 -05:00
Abdelatif Guettouche
79e9347551 arch/risc-v/esp32c3/esp32c3_modtext.c: Prioritise allocation from the 
RTC heap when available.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-18 00:53:42 -05:00
Abdelatif Guettouche
f54804bafc arch/risc-v/esp32c3: Create a separate heap for the RTC memory. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-18 00:53:42 -05:00
Abdelatif Guettouche
7198b3ef4b risc-v/esp32c3/esp32c3_soc.h: Add a function to check if a pointer is 
within the RTC RAM range.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-18 00:53:42 -05:00
Sara Souza
8f59054ef2 risc-v/esp32c3: Adds I2C RESET support via hardware. 2021-06-16 21:22:26 -05:00
Janne Rosberg
673f9519eb risc-v/mpfs: add dma support 2021-06-16 12:22:54 -05:00
Eero Nurkkala
502210e98c riscv/mpfs: add i2c reset handler 
Add reset functionality into the mpfs i2c driver.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-06-16 12:31:36 -03:00
Liu Han
04c805207a risc-v/esp32c3: Support ESP32-C3 efuse 2021-06-16 09:35:09 -03:00
Virus.V
69fce77718 risc-v/bl602: update firmware to fix undefined up_irq_* symbols when linking 
Signed-off-by: Virus.V <virusv@live.com>
 2021-06-15 23:25:16 -05:00
Dong Heng
60fb1adaca riscv: Add inline IRQ process functions 
Remove functions from RISC-V chips.
 2021-06-15 23:25:16 -05:00
Xiang Xiao
2e49e1bc5c mtd: Add MTDIOC_FLUSH IOCTL like MTDIOC_XIPBASE 
since the old design reuse BIOC_FLUSH for
MTD device which make some confusion

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-15 13:26:45 -03:00
Sara Souza
2a7b97c0cd risc-v/esp32-c3: Adds I2C polled support 2021-06-15 10:51:18 -05:00
Liu Han
8eaaf6d462 risc-v/esp32c3: Support ESP32-C3 RSA accelerator 2021-06-14 15:03:11 -03:00
Masayuki Ishikawa
bafac8b560 arch: k210: Fix stack coloring for the idle thread stack 
Summary:
- I noticed that stack coloring for the idle thread stacks does
  not work due to the recent changes
- This commit fixes this issue

Impact:
- k210 only

Testing:
- Tested with both maix-bit (dev board) and QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-12 05:54:08 -05:00
Eero Nurkkala
1bce864ef7 mpfs: add i2c driver 
This adds mpfs i2c driver.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-06-11 21:03:42 -05:00
Eero Nurkkala
fad34e04c4 mpfs: add spi driver 
This adds the SPI driver for the MPFS Icicle board.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-06-11 09:10:03 -05:00
Abdelatif Guettouche
96bcf7678b risc-v/esp32c3_wifi_adapter.c: Remove a config that's only used in 
Xtensa chips.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-11 10:49:52 -03:00
Virus.V
7c20199a61 riscv/bl602:replace syslog to debugging log macros 2021-06-10 08:59:16 -05:00
Xiang Xiao
c0fdddc5d7 arch: Remove all go_nx_start from chip specifc source 
since the idle stack color is done in the common code now

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-10 06:50:41 -07:00
Xiang Xiao
fa0d123f87 arch: Colorize the idle thread stack in an unified way 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Idae8da53e5a4799a8edc0e882f17fd515b70cb14
 2021-06-10 06:50:41 -07:00
Chen Wen
dbf9c87a42 risc-v/esp32c3: Support ESP32-C3 RTC driver 2021-06-10 09:33:04 -03:00
Xiang Xiao
6576306bca arch: Rename xxx_getsp to up_getsp 
All modern desgin support stack pointer and it's also an
important information, so let's standardize this interface.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-09 10:20:02 -07:00
Xiang Xiao
5b2a17b892 Include assert.h in necessary place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-08 13:06:08 -07:00
unixjet
68f19a6290 risc-v/rv32m1: Basic port to rv32m1 ri5cy 2021-06-05 17:25:57 -03:00
Gustavo Henrique Nihei
0b3c2c7603 spi: Refactor SPI Slave interface prefix to sync with I2C Slave 2021-06-05 04:50:34 -07:00
Gustavo Henrique Nihei
27782aca19 risc-v/esp32c3: Include missing debug.h header 2021-06-05 04:50:34 -07:00
Gustavo Henrique Nihei
77dfb39260 risc-v/esp32c3: Uniformize references to CPU interrupt ID 2021-06-04 23:26:13 +01:00
Gustavo Henrique Nihei
f53306f9af risc-v/esp32c3: Ensure internal linkage of interrupt map 2021-06-04 23:26:13 +01:00
Gustavo Henrique Nihei
a2bcffde73 risc-v/esp32c3: Remove unused macros 2021-06-04 23:26:13 +01:00
Abdelatif Guettouche
2d55f2659e riscv/esp32c3: Add module text allocator. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-04 18:08:36 -03:00
Abdelatif Guettouche
778e3ed4ad arch/risc-v/rv32im/riscv_assert.c: Provide dummy definitions of dump 
functions when ARCH_STACKDUMP is not enabled.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-04 12:20:18 -05:00
Abdelatif Guettouche
94ded7a695 arch/riscv/rv32im/riscv_assert.c: Fix preprocessor condition. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-04 12:20:18 -05:00
Janne Rosberg
7b882c3588 risc-v/mpfs: fix ext irq 1-12 
Handle irq numbers 1-12 correctly
 2021-06-04 10:14:58 -05:00
Jani Paalijarvi
ebdc7a06b1 risc-v/mpfs: add MSTimer register offsets and bitmasks 2021-06-04 10:14:58 -05:00
Janne Rosberg
f7cbed0256 risc-v/mpfs: enable up_systemreset() 2021-06-04 10:14:58 -05:00
Janne Rosberg
ec11643394 risc-v/mpfs: add sysreg register defines 
This adds minimal set of sysreg defines for MPFS
 2021-06-04 10:14:58 -05:00
Xiang Xiao
2e54df0f35 Don't include assert.h from public header file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-03 08:36:03 -07:00
Sara Souza
b54be4e946 risc-v/esp32-c3: Add support for HW flow control. 2021-06-01 21:37:27 -05:00
Gustavo Henrique Nihei
24c206b3f8 risc-v/esp32c3: Add DMA support for the SPI Slave controller 2021-06-01 21:37:09 -05:00
Gustavo Henrique Nihei
15a93ae974 risc-v/esp32c3: Remove Master-only settings on SPI Slave driver 2021-06-01 21:37:09 -05:00
Xiang Xiao
d7f96003cf Don't include debug.h from public header file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-01 06:42:02 +09:00
Gustavo Henrique Nihei
1530b0f639 risc-v/esp32c3: Fix overwriting of registered-but-disabled interrupts 2021-05-31 09:15:40 -05:00
Gustavo Henrique Nihei
da78cf78eb risc-v/esp32c3: Remove useless parameter from DMA macro 2021-05-31 09:14:14 -05:00
Gustavo Henrique Nihei
7e15d897bd risc-v/esp32c3: Add driver for SPI Slave controller 2021-05-31 12:54:15 +01:00
chenwen
1d1dd8512f esp32&esp32c3/wifi: Support specific channel and bssid scan 2021-05-31 11:09:19 +01:00
Abdelatif Guettouche
e29da149e3 arch/riscv/src/esp32c3/esp32c3_rt_timer: Fix typos and re-word some 
comments.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-27 05:01:54 -07:00
Abdelatif Guettouche
08aa9ce540 arch/xtensa/src/esp32/esp32_rt_timer: Fix typos and re-word some 
comments.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-27 05:01:54 -07:00
Abdelatif Guettouche
0f3d94e8e8 arch/risc-v/src/esp32c3/esp32c3_rt_timer.h: Add section headers. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-27 05:01:54 -07:00
Virus.V
c6317650f9 risc-v/bl602: Add RTC support 2021-05-26 20:03:19 -03:00
Gustavo Henrique Nihei
1d940b2982 risc-v/esp32c3: Constify DMA descriptor pointer to buffer 2021-05-26 14:05:27 -03:00
Gustavo Henrique Nihei
29cae80533 risc-v/esp32c3: Fix DMA TX Burst being set to input register 2021-05-26 14:05:27 -03:00
Dong Heng
73dcbac09d riscv/esp32c3: Add ESP32-C3 AES driver 2021-05-25 11:02:59 -03:00
Govind Singh
2975050c96 arch/riscv/bl602: Fix typo in i2c driver 
Signed-off-by: Govind Singh <govind.sk85@gmail.com>
 2021-05-25 01:37:28 -05:00
Janne Rosberg
d6205642ab add support for PolarFire SoC and icicle board 
Co-authored-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-05-24 22:55:44 -05:00
Xiang Xiao
001e7c3e76 sched: Don't include nuttx/sched.h inside sched.h 
But let nuttx/sched.h include sched.h instead to
avoid expose nuttx kernel API to userspace.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-05-24 12:11:53 +09:00
Dong Heng
76df958e34 riscv/esp32c3: Support SPI Flash encryption read/write 2021-05-23 08:37:25 -03:00
Huang Qi
f4a0b7aedd libc: Call pthread_exit in user-space by up_pthread_exit 
Drop to user-space in kernel/protected build with up_pthread_exit,
now all pthread_cleanup functions executed in user mode.

* A new syscall SYS_pthread_exit added
* A new tcb flag TCB_FLAG_CANCEL_DOING added
* up_pthread_exit implemented for riscv/arm arch

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-05-21 22:46:52 -06:00
Huang Qi
81a01d089b libc/pthread: Fix comment and document issue 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-05-21 22:46:52 -06:00
Gregory Nutt
bb9b58bdde libc: Move pthread_create to user space 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Change-Id: I5c447d94077debc79158686935f288e4c8e51e01
 2021-05-21 22:46:52 -06:00
Jukka Laitinen
e4fd99682e rv64gc: use PRIx64 format for alert and assert 
This fixes compilation warnings caused by number formatting

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-05-20 05:42:01 -05:00
Jukka Laitinen
e79a45bb93 rv64gc/riscv_assert.c: Fix compilation without CONFIG_DEBUG_ALERT 
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-05-20 05:42:01 -05:00
chenwen
9a99d813fa risc-v/esp32c3: Support ESP32-C3 auto-sleep 2021-05-19 07:00:40 -03:00
Dong Heng
f12de4f7d9 riscv/esp32c3: Add ESP32-C3 ADC driver 2021-05-18 09:20:46 -03:00
Gustavo Henrique Nihei
26a5cb2094 risc-v/esp32c3: Add support for DMA transfers on SPI driver 2021-05-17 13:21:12 +01:00
Gustavo Henrique Nihei
132ffdd28d risc-v/esp32c3: Add burst transfer support for GDMA 2021-05-17 13:21:12 +01:00
Dong Heng
4a7f998c33 riscv/esp32c3: Fix RT timer issues 
1. Enable alarm if there is timer active
2. Wake up main thread to delete timer
3. Wake up main thread when timer is timeout in ISR
 2021-05-16 13:23:43 -05:00
Dong Heng
beed26b6bf riscv/esp32c3: Add ESP32-C3 LEDC(PWM) driver 2021-05-15 08:38:37 -03:00
chenwen
16667930cb risc-v/esp32c3: Support ESP32-C3 PM standby and sleep 2021-05-12 10:15:06 -03:00
Gustavo Henrique Nihei
90a4e8d718 risc-v/esp32c3: Fix DMA channels' interrupt IDs 2021-05-07 16:46:41 -03:00
Dong Heng
bd8e37bb4b risc-v/esp32c3: Add ESP32-C3 (G)DMA driver and testing 2021-05-07 16:46:41 -03:00
Sara Souza
50daf24242 esp32/esp32-c3: Adds two helpers to extract and include a field value 2021-05-05 01:30:03 -07:00
Abdelatif Guettouche
f3a6d80c95 esp32c3/hardware: Include files of the same level by their names only and 
remove unnecessary includes.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-05 01:28:22 -07:00
Sara Souza
b01ddef61b risc-v/esp32-c3: Adds freerun wrapper 2021-05-04 15:22:26 -03:00
Gustavo Henrique Nihei
7ded22fb1a risc-v/k210: Fix SMP interrupt stack size calculation 2021-04-29 19:39:17 -07:00
Gustavo Henrique Nihei
e0da0bf6bd arch/risc-v: Fix interrupt stack alignment 2021-04-29 19:39:17 -07:00
Gustavo Henrique Nihei
f8a36f10c3 arch: Uniformize optimization flag setting across architectures 2021-04-29 19:17:16 -07:00
Gustavo Henrique Nihei
abf039b744 risc-v/rv32im: Set MAXOPTIMIZATION regardless of any debug options 2021-04-29 19:17:16 -07:00
Dong Heng
fcd5648bca riscv/esp32c3: Fix SPI Flash driver internal chip data address error 
"g_rom_flashchip" is not in fixed address between all ESP32-C3's different versions.
 2021-04-28 09:58:16 -05:00
Gustavo Henrique Nihei
edeb16123b risc-v/esp32c3: Uniformize alignment for assembly instructions 2021-04-28 09:55:57 -05:00
Gustavo Henrique Nihei
9e7d3cff92 risc-v/esp32c3: Improve interrupt handler documentation 2021-04-28 09:55:57 -05:00
Gustavo Henrique Nihei
27d32f4309 risc-v/esp32c3: Reorder register restoration on interrupt handler epiloque 2021-04-28 09:55:57 -05:00
Gustavo Henrique Nihei
66a15a6f83 risc-v/esp32c3: Fix wrong references to ESP32 2021-04-28 15:41:30 +01:00
Gustavo Henrique Nihei
7caebdd50f arch/risc-v: Fix stack alignment according to calling convention 
The RISC-V Integer Calling Convention states that the stack pointer
shall always be aligned to a 128-bit boundary upon procedure entry, both
for RV32* and RV64* ISAs (exception to the RV32E ISA, which must follow a
specific convention)
 2021-04-27 23:12:20 -05:00
Gustavo Henrique Nihei
016652f7d7 risc-v/esp32c3: Change ESP32C3_RT_TIMER_TASK_PRIORITY comment into help text 2021-04-27 20:43:07 -06:00
Gustavo Henrique Nihei
9df2179562 risc-v/esp32c3: Uniformize Kconfig alignment and styling 2021-04-27 20:43:07 -06:00
Gustavo Henrique Nihei
1e45a9329b risc-v/esp32c3: Remove inconsistent usage of comment command 2021-04-27 20:43:07 -06:00
Gustavo Henrique Nihei
cd6c29a126 risc-v/esp32c3: Remove redundant dependency 2021-04-27 20:43:07 -06:00