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11922 Commits

Author SHA1 Message Date
kfazz
9e36d42859 Kinetis pwm support, based on kl_ftm driver. 
Initial commit. Compile checked only.
 2016-06-09 13:07:03 -04:00
Gregory Nutt
8c9bc6da79 Trivial changes from review of last PR 2016-06-09 09:39:41 -06:00
Gregory Nutt
2dbd6b3d99 Merged in kfazz/nuttx (pull request #45) 
Teensy clock fixes.
 2016-06-09 09:36:30 -06:00
Gregory Nutt
48c9aa08a3 Merged in marten_svanfeldt/nuttx-public/for_upstream/stm32_dma_fix (pull request #43) 
Fix STM32 DMA code and configuration for STM32F37X chips
 2016-06-09 09:10:13 -06:00
David Sidrane
44ead7f40a Fix email address in file headers 2016-06-09 08:26:14 -06:00
Lok Tep
f12f115598 rename back without f7 2016-06-09 15:48:07 +02:00
kfazz
0c13208d87 Teensy clock fixes. 
The High Gain bit in MCG_C1 was preventing teensy from booting
except after a programming session. The second change doesn't appear
to change any functionality, but complies with restrictions in the k20
family reference manual on FEI -> FBE clock transiions.
 2016-06-09 00:41:01 -04:00
Marten Svanfeldt
1b36526e91 Fix STM32 DMA code and configuration for STM32F37X chips 
Signed-off-by: Marten Svanfeldt <marten@intuitiveaerial.com>
 2016-06-09 05:02:43 +02:00
Gregory Nutt
982982d62b Eliminate some warnings 2016-06-08 09:43:54 -06:00
David Sidrane
4a4f407175 STM32F7: Fix a redefinition warning the DMA header file 2016-06-08 08:29:30 -06:00
David Sidrane
d8ea955d69 Added STM32FF76xxx and STM32FF7xx families 2016-06-08 08:26:26 -06:00
Konstantin Berezenko
3fc7b6f0e5 Add stm32f105r support 2016-06-06 12:52:41 -07:00
Gregory Nutt
f75837a110 Changes from review of the last PR 2016-06-06 13:35:27 -06:00
Gregory Nutt
6b58ed820a Merged in kfazz/nuttx/kinetis (pull request #40) 
Kinetis usb driver
 2016-06-06 12:57:55 -06:00
kfazz
0a4c58e573 First attempt at a usb device controller driver for kinetis. derived from pic32mx usb driver, which uses the same usb controller. 2016-06-06 13:58:07 -04:00
Paul A. Patience
56b018d5db STM32: Fix typo 2016-06-06 12:02:11 -04:00
Gregory Nutt
053ac343fd STM32 PWM: More review changes from last commit; improve handling of unsigned types 2016-06-05 16:01:29 -06:00
Pierre-noel Bouteville
0bd444ae47 Just update duty if frequency is not changed and PSM started. This removeis glitch or blinking when only duty is frequently changed. 2016-06-05 15:35:43 -06:00
Gregory Nutt
af43ce4f46 Update ChangeLog 2016-06-05 15:01:37 -06:00
Lok Tep
88b51683bb bus busy timeout, errata 2016-06-05 11:43:06 +02:00
Gregory Nutt
7671087abc LPC32xx GPIO interrupts: Remove some old logic that should not be there. 2016-06-04 16:36:27 -06:00
Gregory Nutt
1c4d0686c8 LPC43xx: Fill out some missing GPIO interrupt logic 2016-06-04 16:05:36 -06:00
Gregory Nutt
6b84637a5b Update some comments 2016-06-04 13:04:13 -06:00
Gregory Nutt
4965d0dc99 KL and LPC11: Perform similar name change as for STM32: xyz_lowputc -> up_putc 2016-06-04 11:29:27 -06:00
Gregory Nutt
184ca294e8 Rename all references to up_lowgetc 2016-06-04 07:59:02 -06:00
Gregory Nutt
ed1535f188 Changes from review of last PR 2016-06-04 07:52:56 -06:00
Gregory Nutt
8126a3d37d Merged in v01d/nuttx/lpc43-gpio-fixes (pull request #38) 
lpc43 GPIO Interrupts enabled and fixed (not all cases tested)
 2016-06-04 07:46:04 -06:00
Alan Carvalho de Assis
86cfcfd58a Add the up_getc() function to STM32 in order to support the minnsh configuration. 2016-06-04 07:22:45 -06:00
Gregory Nutt
37e8536a88 STM32: Put timer selections in a separate menu 2016-06-04 07:11:05 -06:00
v01d
774e7f9865 lpc43 GPIO Interrupts enabled and fixed (not all cases tested) 2016-06-04 00:28:53 -03:00
Gregory Nutt
34df98d97e Use DEBUG assertions to save space 2016-06-03 14:49:05 -06:00
Gregory Nutt
704fadb0e6 STM32 TIM: Assure that a compilation error will occur if the old timer input clock frequency definitions are used 2016-06-03 14:17:18 -06:00
Gregory Nutt
3ec2386be8 STM32 TIM: There is a TIM17 on some parts too 2016-06-03 14:08:28 -06:00
Gregory Nutt
282edefab3 STM32 TIM: Add hooks for all previously unsupported timers. Also fix some PWM warnings. 2016-06-03 13:51:43 -06:00
Gregory Nutt
c11e923ad4 Fix a cut'n'paste error left from last commit. 2016-06-03 12:11:55 -06:00
Gregory Nutt
910bac65fa STM32 Timer: Generalize and extend calculation of per-timer pre-scaler value. Inspired by original proposal from Pierre-noel Bouteville. 2016-06-03 11:38:59 -06:00
Gregory Nutt
88a41862b5 Revert "STM32 Timer Driver: Change calculation of per-timer pre-scaler value" 
This reverts commit 082d32226b.
 2016-06-03 09:41:17 -06:00
Lok Tep
82cd44dbc5 adc i2c_reset 2016-06-03 17:19:22 +02:00
Pierre-noel Bouteville
082d32226b STM32 Timer Driver: Change calculation of per-timer pre-scaler value 2016-06-03 08:45:22 -06:00
Pierre-noel Bouteville
426e425a55 Correct conditional compilation in STM32 timer cpature logic 2016-06-03 08:41:53 -06:00
Pierre-noel Bouteville
6a2a0bf11f Note reserved bits in STM32 ADC 2016-06-03 08:39:17 -06:00
Pierre-noel Bouteville
94a14de190 Fix EFM32 FLASH conditional compilation 2016-06-03 08:38:11 -06:00
Gregory Nutt
fcdc17056b STM32 F4 RTC: I believe that the F405/407 has only a single alarm. Not sure. 2016-06-02 15:04:23 -06:00
Lok Tep
3bb60966e7 adc copy 2016-06-02 16:17:58 +02:00
Gregory Nutt
82c73e206e STM32 F4 RTC, trivial changes 2016-06-02 07:58:13 -06:00
pkolesnikov
beb6acc798 timer copy 2016-06-02 12:09:42 +02:00
Frank Benkert
90ccba1ad0 SAMV7: MCAN: fix missing unlock of device in mcan_txempty 2016-06-01 10:38:19 -06:00
Gregory Nutt
2f974ffeaf Merged in david_s5/nuttx/upstream_to_greg (pull request #37) 
Fix the Value Line adc IRQ number selection
 2016-05-31 19:18:11 -06:00
Gregory Nutt
82dec4acab STM32F4 RTC: Remove 24 hour limit; Fix calculation of the alarm register (was not including day of the month). Fix a bad shift value 2016-05-31 19:13:21 -06:00
David Sidrane
70f2b47a0d Fix the Value Line adc IRQ number selection 2016-05-31 14:54:04 -10:00
Gregory Nutt
6eac8bf28d Update some comments 2016-05-31 17:31:15 -06:00
Gregory Nutt
15810946b1 Update some comments 2016-05-31 17:28:02 -06:00
Gregory Nutt
8ca5daf2b3 Changes from review of last PR 2016-05-31 15:52:56 -06:00
Gregory Nutt
213c1900b0 Merged in neilh20/anuttx/bugfix_rtcalarm (pull request #36) 
The rtc examples "alarm 10" now runs to completion
 2016-05-31 15:43:36 -06:00
neilh10
639410849e alarm 10 now runs to completion 2016-05-31 14:17:52 -07:00
Gregory Nutt
b80bf20374 Fix another bungle in the last commit 2016-05-31 11:52:40 -06:00
Gregory Nutt
b5c37f0270 LP43: Add support for more than 63 interrupts (not currently needed) 2016-05-31 11:42:21 -06:00
Gregory Nutt
828c898a80 LP43: Add support for more than 63 interrupts (not currently needed) 2016-05-31 11:39:51 -06:00
Gregory Nutt
f06a06952f LPC43xx: 1KB is 1024, not 1025. Noted by phreakuencies. 2016-05-31 06:22:10 -06:00
Pierre-noel Bouteville
39c1e3aba2 Allow to not use all channet in a lower part of PWM 2016-05-30 11:58:22 -06:00
Gregory Nutt
5ef3e3e215 Replace confusing references to uIP with just 'the network' 2016-05-30 11:52:07 -06:00
Gregory Nutt
f65616f872 Replace confusing references to uIP with just 'the network' 2016-05-30 09:16:32 -06:00
Gregory Nutt
815bea77ea i.MX6: Update ECSPI header file 2016-05-29 10:23:06 -06:00
Gregory Nutt
fa10927dcc Stefan Kolb's change to the SAMV7 Oneshot Timer (commit d44ecbcfbb) should also be applied to the SAM3/4 oneshot time since the drivers are identical. Here are the commit commits from Stefan's original change: 
"This is a fix to a problem in the handling of the oneshot timer. Due to a wrong assumption concerning the behavior directly after the start of the timer/counter the function sam_oneshot_cancel(…) calculates the wrong remaining time. The code assumes that the counter register is zero directly after the start of the timer, but this is not true. To start the time/counter a software trigger is invoked, this trigger starts the timer/count and sets the counter register to zero, but the reset of the counter register is not performed instantly. According to the datasheet: “The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock.” Thus the counter is set to zero between 0 and USEC_PER_TICK microseconds after the clock was started.

"In my fix I use the freerun count value to determine if at least one tick passed since the start of the timer and thus if the value of the oneshot counter is correct. I also tried to use the function up_timer_gettime(…) to achieve this but, at least if compiled with no optimization the problem vanishes without using the value of the function, the function call takes too long.

"Another problem treated in the fix is that if the oneshot timer/counter is canceled, we only know the remaining time with a precision of USEC_PER_TICK microseconds. This means the calculated remaining time is between 0 and USEC_PER_TICK microseconds  too long. To fix this I subtract one tick if the calculated remaining time is greater than one tick and otherwise set the remaining time to zero. By doing so the measured times are much more precise as without it."
 2016-05-29 08:25:41 -06:00
Gregory Nutt
9071a22c28 Cosmetic fix to spacing 2016-05-29 08:25:05 -06:00
Gregory Nutt
0b17b1feb3 i.MX6: Add ECSPI configuration logic. Updated ECSPI header files 2016-05-28 17:42:29 -06:00
Gregory Nutt
16cb0a9205 i.MX6: Divide ported i.MX1/L CSPI header file into two header files 2016-05-28 17:10:58 -06:00
Gregory Nutt
13b53d87a9 i.MX6: Add ECSPI header file 2016-05-28 12:23:05 -06:00
Konstantin Berezenko
5c6cd17d46 Add support for SPI 4 and 5 on stm32f411 chips 2016-05-27 11:08:18 -07:00
Gregory Nutt
b4354cf130 Stefan Kolb's change to the SAMV7 Oneshot Timer (commit d44ecbcfbb) should also be applied to the SAMA5 oneshot time since the drivers are identical. Here are the commit commits from Stefan's original change: 
"This is a fix to a problem in the handling of the oneshot timer. Due to a wrong assumption concerning the behavior directly after the start of the timer/counter the function sam_oneshot_cancel(…) calculates the wrong remaining time. The code assumes that the counter register is zero directly after the start of the timer, but this is not true. To start the time/counter a software trigger is invoked, this trigger starts the timer/count and sets the counter register to zero, but the reset of the counter register is not performed instantly. According to the datasheet: “The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock.” Thus the counter is set to zero between 0 and USEC_PER_TICK microseconds after the clock was started.

"In my fix I use the freerun count value to determine if at least one tick passed since the start of the timer and thus if the value of the oneshot counter is correct. I also tried to use the function up_timer_gettime(…) to achieve this but, at least if compiled with no optimization the problem vanishes without using the value of the function, the function call takes too long.

"Another problem treated in the fix is that if the oneshot timer/counter is canceled, we only know the remaining time with a precision of USEC_PER_TICK microseconds. This means the calculated remaining time is between 0 and USEC_PER_TICK microseconds  too long. To fix this I subtract one tick if the calculated remaining time is greater than one tick and otherwise set the remaining time to zero. By doing so the measured times are much more precise as without it."
 2016-05-27 07:58:03 -06:00
Stefan Kolb
d44ecbcfbb This is a fix to a problem in the handling of the oneshot timer. Due to a wrong assumption concerning the behavior directly after the start of the timer/counter the function sam_oneshot_cancel(…) calculates the wrong remaining time. The code assumes that the counter register is zero directly after the start of the timer, but this is not true. To start the time/counter a software trigger is invoked, this trigger starts the timer/count and sets the counter register to zero, but the reset of the counter register is not performed instantly. According to the datasheet: “The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock.” Thus the counter is set to zero between 0 and USEC_PER_TICK microseconds after the clock was started. 
In my fix I use the freerun count value to determine if at least one tick passed since the start of the timer and thus if the value of the oneshot counter is correct. I also tried to use the function up_timer_gettime(…) to achieve this but, at least if compiled with no optimization the problem vanishes without using the value of the function, the function call takes too long.

Another problem treated in the fix is that if the oneshot timer/counter is canceled, we only know the remaining time with a precision of USEC_PER_TICK microseconds. This means the calculated remaining time is between 0 and USEC_PER_TICK microseconds  too long. To fix this I subtract one tick if the calculated remaining time is greater than one tick and otherwise set the remaining time to zero. By doing so the measured times are much more precise as without it.
 2016-05-27 07:51:50 -06:00
Gregory Nutt
3d3b7b5422 EFM32, STM32, TIVA: Allow lower half driver to build if any ADC is selected. Should not depend on CONFIG_ADC. 2016-05-27 06:46:33 -06:00
Lok Tep
c00bb5d4a7 i2c 2016-05-27 00:16:55 +02:00
Gregory Nutt
31ac3f5123 STM32 ADC: Missed on adc_receive 2016-05-26 12:42:34 -06:00
Gregory Nutt
aa05767a00 Add ADC bind method to the Tiva ADC drivers 2016-05-26 12:39:22 -06:00
Gregory Nutt
8f2a660c8b Add ADC bind method to the STM32 ADC drivers 2016-05-26 12:25:54 -06:00
Gregory Nutt
2f5221ed91 Add ADC bind method to the LPC43xx and SAMA5Dx ADC drivers 2016-05-26 12:19:17 -06:00
Gregory Nutt
957634519d Missed a few adc_receive calls in the LPC17xx ADC driver. That design has several. 2016-05-26 12:04:17 -06:00
Gregory Nutt
9d6845b7ec Add ADC bind method to the EFM32 and LPC17xx ADC drivers 2016-05-26 11:57:18 -06:00
Gregory Nutt
783bab6c82 Costmetic changes from review of last PR 2016-05-25 18:04:39 -06:00
Gregory Nutt
0d2698a710 Merged in ziggurat29/nuttx/stm32l4_i2c_lcd_mjkdz_001 (pull request #30) 
get I2C working for STM32L4
 2016-05-25 17:58:19 -06:00
Gregory Nutt
3603dc6218 1-wire: Initialization/uninitialization functions are not use MCU-independent up_ naming. Should use STM32-specific stm32_ naming. These are not globally accessible but only accessible from STM32 board logic. 2016-05-25 17:56:47 -06:00
ziggurat29
003c2c737a get I2C working. some more work regarding clocking computation is needed, as is some inhertited 'todo's from the basis code. but it does work with the devices tested so far. 2016-05-25 18:43:37 -05:00
Paul A. Patience
d31aefe4ef STM32 CAN: Add support for both RX FIFOs 2016-05-25 16:11:18 -04:00
Gregory Nutt
add152bf24 Update README 2016-05-25 14:07:59 -06:00
Gregory Nutt
78e08bbeea Purely cosmetic change from review of last PR 2016-05-25 13:29:01 -06:00
Gregory Nutt
fafc56ae80 Merged in ziggurat29/nuttx/stm32l4_i2c_lcd_mjkdz_001 (pull request #28) 
complete logic in 'create stack' and 'use stack' to support stack coloration.  Fix some booboos breaking compatibility with TLS in libc.
 2016-05-25 13:22:03 -06:00
Gregory Nutt
4afc4964ed SAM34 TWI: Missing semicolon 2016-05-25 13:05:03 -06:00
Gregory Nutt
4a63a7760a STM32: Hook 1-Wire driver into the build system 2016-05-25 12:31:32 -06:00
Gregory Nutt
9ec104834a Remove CONFIG_USARTn_ISUART 2016-05-25 11:21:48 -06:00
Gregory Nutt
c089a2f241 Rename CONFIG_ARCH_HAVE_OTHER_UART to CONFIG_OTHER_UART_SERIALDRIVER 2016-05-25 10:48:33 -06:00
Gregory Nutt
e2e6ce3f1b Rename CONFIG_ARCH_HAVE_SCIn to CONFIG_SCIn_SERIALDRIVER 2016-05-25 10:46:55 -06:00
Gregory Nutt
2a87741e72 Rename CONFIG_ARCH_HAVE_UARTn to CONFIG_UARTn_SERIALDRIVER 2016-05-25 10:45:01 -06:00
Gregory Nutt
249a2e48e5 Rename CONFIG_ARCH_HAVE_USARTn to CONFIG_USARTn_SERIALDRIVER 2016-05-25 10:39:23 -06:00
ziggurat29
05d2036334 complete logic in 'create stack' and 'use stack' to support stack coloration. Fix some booboos breaking compatibility with TLS in libc. 2016-05-25 10:37:38 -05:00
Aleksandr Vyhovanec
52c6cb1799 Fix typographical naming error in STM32 U[S]ART bit defintiions. 2016-05-25 09:04:03 -06:00
Aleksandr Vyhovanec
9a2002a302 1-wire driver based on U[S]ART in single-wire, half-duplex mode. 2016-05-25 08:59:47 -06:00
Frank Benkert
04223a9618 SAMV7: USBHS: Remove disabling of whole usb on suspend 
This fix removes the disabling of the whole USB peripheral on suspend
interrupt. Its enough to freeze the clock instead.

When disabling the whole peripheral, the next wakeup-interrupt comes
up with an disabled clocking. The unfreeze clock has no effect, because
the master clock is disabled. This makes all registers, including the
IDR unwriteable and the IRQ falls in an endless loop blocking the whole
system.

Furthermore the disabling of the peripheral clock prevents hotplugging
or reconnecting the USB.
 2016-05-25 07:20:48 -06:00
pkolesnikov
9ee3fe3f19 clocking for 54mhz 2016-05-25 14:30:47 +02:00
Lok Tep
4c96755219 Merge remote-tracking branch 'origin/master' 2016-05-24 23:23:57 +02:00
unknown
c89a5494b8 spi, copy 2016-05-24 16:57:39 +01:00
Gregory Nutt
317bf064a8 i.MX6: Clean up some initializers 2016-05-24 07:44:36 -06:00
Alexander Vasiljev
ad6f37edfa Adds definitions for the LPC4337jet100 chip. 2016-05-24 07:03:50 -06:00
Gregory Nutt
3a8ff78f87 Restore PR. I have no idea where it went. 2016-05-23 17:45:15 -06:00
Gregory Nutt
e929066042 Fix an error in the last commit 2016-05-23 17:11:36 -06:00
David Sidrane
c41e6d823a Add the up_systemreset interface to the samv7 arch. The approach is slightly different in that: 1) It enables ARCH_HAVE_RESET and allows the user to set if, and for how long, to drive External nRST signal. It also does not contain a default board_reset, as that really should be done in the config's src if CONFIG_BOARDCTL_RESET is defined. 2016-05-23 17:05:02 -06:00
David Sidrane
fca329945b This patch ensures that the TWIHS (i2c) hw get's its clock set when the sequence of 
sam_i2cbus_initialize
sam_i2cbus_uninitialize
sam_i2cbus_initialize

Or twi_reset is called.

I found this a while back in the stm32 family, so there may be more arch-es with this sort of bug. I suppose any driver that has the notion of "do not set the freq if it is already set" could be suspect.
 2016-05-23 13:38:34 -06:00
Alexander Vasiljev
b43fcd6f99 LPC43xx: Add AES support. 2016-05-23 08:03:32 -06:00
pkolesnikov
eb9cfd1255 i2c copy, right include 2016-05-23 15:59:24 +02:00
pkolesnikov
7630b9db5d i2c copy 2016-05-23 15:56:56 +02:00
Gregory Nutt
80d0b2736e Reorder some logic: (1) set initial CPU IDLE task regsters AFTER allocating stack, (2) invalidate cache in CPU start-up BEFORE handling first interrupt. 2016-05-22 15:01:49 -06:00
Steve
a75c48c183 Fix for a minor typo that I introduced somewhere along the way during my testing. This makes the bridge code actually compile… 2016-05-21 17:09:50 -06:00
Gregory Nutt
e47714322e Merged in K-man23/nuttx/stm32f411e-disco (pull request #25) 
Add basic configuration for stm32f411e-disco board with STM32F411VE chip
 2016-05-20 17:54:07 -06:00
Konstantin Berezenko
a2253cdd3e Add basic configuration for stm32f411e-disco board with STM32F411VE chip 2016-05-20 16:38:25 -07:00
Steve
bd3ef36eda SUMMARY 
-------
   This patch enhances networking support for the simulation under Linux.
   Includes updated support for Linux TUN/TAP, and the addition of support for
   Linux bridge devices.

CHANGES
-------
   o Check to see if the d_txavail callback is present before calling it in
     the arp send code.  This prevents a segfault when simulating the telnetd
     daemon with arp send enabled.

   o Adjust the simulation's netdriver_loop() so it will detect and respond to
     ARP requests.

   o Do not attempt to take the tap device's hardware address for use by the
     simulation.  That hardware address belongs to the host end of the link,
     not the simulation end.  Generate a randomized MAC address instead.

   o Do not assign an IP address to the interface on the host side of the TAP
     link.

   + Provide two modes: "host route" and "bridge".

   + In host route mode, maintain a host route that points any traffic for the
     simulation's IP address to the tap device.  In this mode, so long as the
     simulation's IP is a free address in the same subnet as the host, no
     additional configuration will be required to talk to it from the host.
     Note that address changes are handled automatically if they follow the
     rule of if-down/set-address/if-up, which everything seems to.

   + In bridge mode, add the tap device to the specified bridge instance.  See
     configs/sim/NETWORK-LINUX.txt for information and usage examples.  This
     enables much more flexible configurations (with fewer headaches), such as
     running multiple simulations on a single host, all of which can access
     the network the host is connected to.

   o Refresh configurations in configs/sim where CONFIG_NET=y.  They default
     to "host route" mode.

   o Add configs/sim/NETWORK-LINUX.txt

CAVEATS
-------
   - The MAC address generation code is extremely simplistic, and does not
     check for potential conflicts on the network.  Probably not an issue, but
     something to be aware of.

   - I was careful to leave it in a state where Cygwin/pcap should still work,
     but I don't have a Windows environment to test in.  This should be
     checked.

   - I don't know if this was ever intended to work with OS X.  I didn't even
     try to test it there.

NOTES
-----
   - Was able to get telnetd working and simulate nsh over telnet, but only so
     long as listen backlogs were disabled.

     There appears to be a bug in the backlog code where sockets are being
     returned in SYN_RCVD state instead of waiting until they're ESTABLISHED;
     if you perform an immediate send after accepting the connection, it will
     confuse the stack and the send will hang; additionally, the connection
     will never reach ESTABLISHED state.

     Can be worked around by adding a sleep(1) after the accept in telnetd.  I
     don't have the necessary knowledge of the IP stack to know what the
     correct fix is.
 2016-05-20 17:36:14 -06:00
Gregory Nutt
356692d70e SMP: Need to enable FPU on other CPUs as well 2016-05-20 13:35:58 -06:00
Gregory Nutt
07acd5327a SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started. 2016-05-20 12:39:02 -06:00
David Sidrane
916153fb75 Fix build if the config is not updated 2016-05-19 12:44:58 -10:00
Gregory Nutt
e27e87a957 Backing out part of last commit 2016-05-19 15:46:07 -06:00
David Sidrane
8fac871cc9 Adds a JTAG config and ERASE config to Kconfig to set the CCFG_SYSIO SYSIO Pins 
• SYSIO4: PB4 or TDI Assignment
0: TDI function selected.
1: PB4 function selected.
• SYSIO5: PB5 or TDO/TRACESWO Assignment
0: TDO/TRACESWO function selected.
1: PB5 function selected.
• SYSIO6: PB6 or TMS/SWDIO Assignment
0: TMS/SWDIO function selected.
1: PB6 function selected.
• SYSIO7: PB7 or TCK/SWCLK Assignment
0: TCK/SWCLK function selected.
1: PB7 function selected.
• SYSIO12: PB12 or ERASE Assignment
0: ERASE function selected.
1: PB12 function selected.

The thing I did not add is warning or compilation failure, (to save the next guy the hassle), at ALL the driver points that uses the these pins.

I did remove this

  /* To use the USART1 as an USART, the SYSIO Pin4 must be bound to PB4
   * instead of TDI
   */

  uint32_t sysioreg = getreg32(SAM_MATRIX_CCFG_SYSIO);
  sysioreg |= MATRIX_CCFG_SYSIO_SYSIO4;
  putreg32(sysioreg, SAM_MATRIX_CCFG_SYSIO);

in sam_lowputc.c in favor of an #error - because the default is an input TDI and driving it blindly to an output TXD1, would be a contention.
 2016-05-19 14:33:54 -06:00
Gregory Nutt
7f7d4e664c Completely trivial changes from review of last PR 2016-05-19 14:09:00 -06:00
Sebastien Lorquet
ef66f641e9 small fix left from stm32 2016-05-19 21:57:59 +02:00
Sebastien Lorquet
6642898ee4 Merge branch 'master' into can 2016-05-19 21:49:31 +02:00
Sebastien Lorquet
8aae953f67 CAN support for STM32L4 2016-05-19 19:13:04 +02:00
Gregory Nutt
c364faeefc SAM WDT: Rename up_wdginitialize() functions to something more appropriate for the internal OS interface. 2016-05-18 19:47:48 -06:00
Gregory Nutt
5d574549bd stm32f103-minimum: Add schematic; remove unused watchdog driver logic 2016-05-18 15:37:42 -06:00
Gregory Nutt
f454b38d6e ARMv7-A SMP: Allow CONFIG_SMP_NCPUS=1 for testing purposes 2016-05-18 09:17:02 -06:00
Gregory Nutt
72de45b7cf Merged in david_s5/nuttx/upstream_to_greg (pull request #21) 
Fixed Break changes needed CONFIG_SERIAL_TERMIOS to build
 2016-05-17 18:09:23 -06:00
David Sidrane
f444f061d6 Fixed Break changes needed CONFIG_SERIAL_TERMIOS to build 2016-05-17 14:04:51 -10:00
Gregory Nutt
5fc619eb1b Changes from review of last PR 2016-05-17 17:39:27 -06:00
Gregory Nutt
4aeb06a79d Merged in david_s5/nuttx/upstream_to_greg (pull request #20) 
Upstream_to_greg
 2016-05-17 17:30:45 -06:00
David Sidrane
bef5552eba Support BSD compatible breaks on stm32fl4 U[S]ART 2016-05-17 13:09:34 -10:00
David Sidrane
3ffe7c378f Support BSD compatible breaks on stm32f7 U[S]ART 2016-05-17 13:09:34 -10:00
David Sidrane
b11f49e7f1 Support BSD compatible breaks on stm32 U[S]ART 2016-05-17 13:09:34 -10:00
David Sidrane
55d8b0e277 Use the correct register and bit to send an STM32 non-bsd compatible break 2016-05-17 07:55:33 -10:00
Gregory Nutt
fb484a581f All GCC final arch/*/src/Makefiles: Allow --start-group and --end-group to be redefined for the case where GCC is used to link (instead of LD). Suggested by Paul Alexander Patience. 2016-05-17 10:43:15 -06:00
Gregory Nutt
0fe64839db i.MX6: Fix comparison values in system timer setup. Clock was running 3x too fast. 2016-05-17 10:08:06 -06:00
Gregory Nutt
4c08492c0f i.MX6: Fix a bit setting in the timer configuration 2016-05-17 07:21:18 -06:00
Gregory Nutt
e6728bac29 Cortex-A9 GIC: Add an interface to set interrupt edge/level trigger 2016-05-16 14:42:55 -06:00
Gregory Nutt
4feeb0c2b4 Cortex-A9 GIC: Some fixes that I don't fully understand but do indeed give me serial interrupts 2016-05-16 12:50:35 -06:00
Gregory Nutt
a0cdbcb58f Update README 2016-05-16 08:44:18 -06:00
Gregory Nutt
a3f3cc12c0 Update some comments; Fix grammatic error in ChangeLog. 2016-05-13 17:36:08 -06:00
Gregory Nutt
faca2fb1e7 ARMv7-A/i.MX6: Add logic to handle allocation of CPU IDLE thread stacks more efficiently 2016-05-13 11:39:42 -06:00
Gregory Nutt
d14d84c1a6 ARMv7M/i.MX6: Implement CPUn n=1,2,3 startup logic 2016-05-13 09:11:55 -06:00
Gregory Nutt
e5388ad127 i.MX6: Need to set VBAR register for each CPU 2016-05-12 15:32:53 -06:00
Gregory Nutt
70782b0f14 ARMv7-A i.MX6: More SMP logic. Still untested. 2016-05-12 15:04:46 -06:00
Gregory Nutt
99e695398c Rename up_boot to arm_boot 2016-05-12 13:42:49 -06:00
Gregory Nutt
ba4ae6fdc4 Cosmetic fixes to last commit 2016-05-12 13:42:48 -06:00
David Sidrane
8a4e185c84 Kconfig edited online with Bitbucket 2016-05-12 18:50:43 +00:00
Gregory Nutt
7887b2d164 i.MX6: Add SRC register definition header file 2016-05-12 12:23:07 -06:00
Gregory Nutt
c00e3e55dc Fix several places in DMA logic where a spurious semicolon causes bad conditional logic 2016-05-11 17:42:59 -06:00
Gregory Nutt
f64f7407ba SAMDL DMAC: Fix several places in DMA logic where a spurious semicolon causes bad conditional logic 2016-05-11 17:30:04 -06:00
Gregory Nutt
f07ea1bb94 SAM (all): Fix several places in DMA logic where a spurious semicolon causes bad conditional logic 2016-05-11 17:26:59 -06:00
David Sidrane
8517a303a5 sam_xdmac.c edited online with Bitbucket 2016-05-11 23:13:24 +00:00
Gregory Nutt
f69b7d41db Merged in young-mu/nuttx/developing (pull request #15) 
Fix a bug of GPIO falling-edge interrupt for tiva
 2016-05-08 01:40:56 -06:00
Gregory Nutt
5c1c5079ea Cosmetic changes from review of last PR 2016-05-08 01:40:31 -06:00
Gregory Nutt
0143b3869a Merged in ziggurat29/nuttx/stm32l4_update_rtc_impl (pull request #14) 
Stm32l4_update_rtc_impl
 2016-05-08 01:24:09 -06:00
Young
863db15b56 Fix a bug of GPIO falling-edge interrupt for tiva 2016-05-08 13:54:51 +08:00
ziggurat29
48fc8b9dd7 problem with resetting backup domain clears clocking options set up before in *rcc.c 
use INITS flag to avoid magic reg value to detect power up reset state of rtc
correct a problem clearing interrupt flags (they weren't) which prevented an alarm from ever being used more than once per reset cycle
 2016-05-07 11:35:08 -05:00
Stefan Kolb
da1fc98a51 Fix a copy and paste error concerning the CAN driver. In the file sam_matrix.h the define SAM_MATRIX_CAN0_OFFSET is set to the wrong value. 
Error is only triggered if the global variable g_mcan0_msgram is located in RAM at an address beyond 0x20400000 + 0x0000ffff. In this case all send CAN messages have the length zero and the CAN-ID is zero as well.
 2016-05-06 04:02:28 -06:00
Gregory Nutt
050f544782 Fix typo in variable name in serial BREAK logic. Review other serial implementations for similar naming problems. 2016-05-05 11:30:47 -06:00
ziggurat29
4e57c36a8c when setting an alarm, ensure that the respective alarm triggered flag is reset, because the alarms are edge-triggered interrupts 2016-05-05 11:47:58 -05:00
ziggurat29
0d659de226 fix nasty bug in ISR handler, where interrupt was not properly acknowleged (write to CR instead of ISR, as intended). Also, minor, set the LSI prescaler values more appropriately (though not critical since LSI is so low precision anyway). 2016-05-05 11:39:19 -05:00
ziggurat29
e0371de24d correct the RTC_ALRMR_ENABLE value, it needs to ignore the date/dow component since that is not set. Also, the prescaler value for HSE (which presumes 1 MHz, anyway) had transposed digits. 2016-05-05 11:28:41 -05:00
ziggurat29
67b1f89159 address thread safety in lower half driver with a driver mutex acquired/released in public api 2016-05-05 11:22:09 -05:00
ziggurat29
273680a6e9 update RTC implementation to include the various alarm related stuff recently added to STM32 arch 2016-05-05 11:16:00 -05:00
ziggurat29
dedcbeba2e add unique id function to arch, modded board to support unique id boardctl 2016-05-03 11:09:23 -05:00
Gregory Nutt
a95e426d35 Costmetic changes from last PR 2016-04-30 09:04:38 -06:00
ziggurat29
2fe0565437 added support for HSE and MSI clocks, and auto trim of MSI to LSE (needed for USB). 2016-04-29 22:13:32 -05:00
ziggurat29
31870b22f5 booboo in config sanity check; wasn't preventing insanity 2016-04-29 07:29:17 -05:00
ziggurat29
31e7f6fd00 add configuration options to allow SRAM2 to be used for heap, or not at all, and to zero-init it on OS start, or not at all. 2016-04-26 10:12:13 -05:00
ziggurat29
1218ee5f51 bug in binding peripheral to dma channel; inverted sense of a bitmask 2016-04-25 10:27:02 -05:00
ziggurat29
8d4dccb3b9 add DMA support to QSPI; tested. Updated Kconfig to more cleanly present the options and defaults. 2016-04-24 16:28:30 -05:00
ziggurat29
0f8dc3e7b4 fixed missing DMA peripheral selection and some header defines, updated various comments to be accurate 2016-04-24 16:23:47 -05:00
Gregory Nutt
aed10e0e49 Cosmetic changes from last PR 2016-04-23 12:51:46 -06:00
Gregory Nutt
0d3a0bf603 Merged in ziggurat29/nuttx/stm32l4_qspi_004 (pull request #5) 
add QSPI memory mapped mode support.  tested.  QSPI may enter and exit memory mapped mode; while in effect, other operations (e.g. command, memory) will fail with -EBUSY.
 2016-04-23 12:46:19 -06:00
ziggurat29
8c0c70ab12 add QSPI memory mapped mode support. tested. QSPI may enter and exit memory mapped mode; while in effect, other operations (e.g. command, memory) will fail with -EBUSY. 2016-04-23 11:54:03 -05:00
Marco Krahl
8b36a83df1 stm32: fix wrong FSCM pin mapping for stm32f42x 2016-04-22 07:27:00 -06:00
Gregory Nutt
2cb52786b6 STM32F7: Add dummy stm32_spi.h header file to workaround some compilation issues. Suggest by Martin Davey. 2016-04-20 06:49:21 -06:00
Gregory Nutt
4e04b3e931 Correct configuration of GPIO pin interrupts on Kinetis K60. Fromo mrechte. 2016-04-20 06:41:51 -06:00
Gregory Nutt
b8ee28cb57 lpc4357fet256_pinconfig.h has wrong ethernet pins configuration (slow slew rate, somewhere inbuffer should be used). From Vytautas Lukenskas 2016-04-20 06:37:26 -06:00
Frank Benkert
885cd812e6 SAME70: USBHS device workaround for errata; EP7 does not support DMA on some parts 2016-04-20 06:22:04 -06:00
Gregory Nutt
8bcb5f0251 Cosmetic changes from review of last PR 2016-04-19 07:11:18 -06:00
ziggurat29
ca6cb85456 QSPI interrupt driven mode is now implemented 2016-04-19 06:55:12 -05:00
Gregory Nutt
26ba3a2b96 Cosmetic changes from review of last PR 2016-04-18 06:50:45 -06:00
Gregory Nutt
c5cce5603e Merged in ziggurat29/nuttx/stm32l4_qspi_002 (pull request #2) 
basic support for QSPI in STM32L4; verified via 'examples/media'
 2016-04-18 06:30:28 -06:00
ziggurat29
499fea73ec basic support for QSPI in STM32L4; verified via 'examples/media' 2016-04-17 21:08:25 -05:00
Gregory Nutt
aa64214877 FB: Add a display number to the framebuffer planeinfo structure 2016-04-17 10:08:27 -06:00
Gregory Nutt
46846c0c24 Framebuffer driver: Add a display number to each interface in order to support multiple displays 2016-04-14 12:23:15 -06:00
Sebastien Lorquet
bef518095f Fix the STM32L4 SPI driver. That SPI driver is quite different. They now handle frames of arbitrary size between 4 and 16 bits. It was broken before a new bit has to be set (rx fifo threshold) to handle <= 8-bit transactions. If not set, the default is 16-bit packed >=8-bit frames and the RXNE bit is never set (it is set when 16-bits are received). weird things as always. 
This also add 8-bit access routines to the data register, because a 16-bit access to the data register when the frame size is below 9 bits is interpreted as a packed dual frame exchange.
 2016-04-13 17:21:49 -06:00
Gregory Nutt
99d981c3fc Kinetis SDHC: May work queue dependencies clearer 2016-04-12 09:07:25 -06:00
Stefan Kolb
fec1931def SAMv7 Kconfig: Correct range of SAMV7_PROGMEM_NSECTORS 2016-04-11 06:21:04 -06:00
Gregory Nutt
b3a177618f Oops: Forgot to add file in previous commit 2016-04-10 09:11:50 -06:00
Kha Vo
e0a4221fe0 ARMv7-M: Add an IAR version of the test'n'set assembly file 2016-04-10 09:11:49 -06:00
Sergei Ustinov
8a5bf3c230 STM32 DAC output buffers correct enable. 2016-04-10 08:51:59 -06:00
Gregory Nutt
48106e605a Merge in arch/ submodule 2016-04-10 07:49:41 -06:00
Gregory Nutt
a031fc1a88 Remove submodules 2016-04-09 12:36:05 -06:00
Gregory Nutt
3045f4910e Update submodules 2016-04-04 10:55:25 -06:00
Sebastien Lorquet
8f15af280a Sort DMA by function; Fix one misnamed definition. 2016-04-04 09:49:44 -06:00
Gregory Nutt
dc71a47df6 RTC: Fix some configuration issues when RTC_ALARM is disabled 2016-04-04 09:24:27 -06:00
Gregory Nutt
b4fc040783 RTC: Fix some compile issues when RTC_ALARM is disabled 2016-04-04 09:24:06 -06:00
Gregory Nutt
8a076d4c09 Eliminate a warning 2016-04-04 08:30:03 -06:00
Gregory Nutt
1e4674e535 STM32 RTC alarm: Use modifyreg32 for consistency 2016-04-04 08:28:01 -06:00
Gregory Nutt
1ea7b48677 RTC lower half was missing call to F4 alarm cancel function 2016-04-04 08:23:09 -06:00
Gregory Nutt
531b9f6626 STM32 RTC alarm: remove some if 0ed out logic. 2016-04-04 08:16:53 -06:00
Gregory Nutt
19aa5880e7 STM32 RTC Alarm: Add Neil's alarm cancellation logic 2016-04-04 08:15:48 -06:00
Gregory Nutt
4fbd79d1a8 rtc.h: Needs to include signal.h and time.h to avoid compile errors in certain contexts 2016-04-03 13:35:01 -06:00
Gregory Nutt
65dc922a2e STM32 RTC: Fix compile errors for STM32 F1 2016-04-03 13:26:29 -06:00
Gregory Nutt
a44b0798e2 RTC driver: Needs to initialize state structure to zero on initalization 2016-04-03 12:40:25 -06:00
Gregory Nutt
a573617f33 Costmetic renaming 2016-04-03 12:38:02 -06:00
Gregory Nutt
ae95f6cdfd RTC: Fix some errors when RTC debug is enabled 2016-04-03 09:52:25 -06:00
Gregory Nutt
9f0df8180a STM32 RTC: Fix some errors when RTC debug is enabled 2016-04-03 09:52:08 -06:00
Gregory Nutt
6b3b12ee0a STM32 RTC: Move the logic to set a relative alarm from the low level RTC driver up higher into the RTC device driver lower half. 2016-04-03 09:22:02 -06:00
Gregory Nutt
1135ce804d RTC: Extend interface by adding a method to set the alarm relative to the current time 2016-04-02 18:18:48 -06:00
Gregory Nutt
e904d98915 STM32 RTC: Add implementation of logic to set the alarm relative to the current time 2016-04-02 18:17:46 -06:00
Gregory Nutt
1767b21d3c Update submodules 2016-04-02 17:42:00 -06:00
Gregory Nutt
a609880839 STM32 F4 RTC: Add support for setting alarm via driver 2016-04-02 17:38:19 -06:00
Gregory Nutt
d46156c2ba Merge branch 'master' of https://bitbucket.org/nuttx/arch 2016-04-02 14:48:59 -06:00
Gregory Nutt
0fccd81eff cosmetic update 2016-04-02 14:58:01 -06:00
Gregory Nutt
29f1c90b82 Eliminate a warning 2016-04-02 14:48:51 -06:00
Gregory Nutt
0723226bda RTC: Further simplications of the RTC driver interface; Add sample implem. 2016-04-02 13:55:58 -06:00
Gregory Nutt
9bc38d19d9 RTC: Further simplications of the RTC driver interface; Add sample implementation of alarms for F1 2016-04-02 13:54:18 -06:00
Gregory Nutt
5fdefa1aad Minor cleanup of STM32 alarm stuff 2016-04-02 13:11:57 -06:00
Gregory Nutt
58d6624f29 RTC: Simplify the RTC driver interface. Way too much stuff in that interface and it is not fully implemented anywhere. 2016-04-02 13:01:02 -06:00
Gregory Nutt
476301e5a4 STM32: Adapt the lower half RTC driver to the new, simplified interface 2016-04-02 12:58:47 -06:00
Neil Hancock
5ac54013d2 STM32 F4: Add a custom RTC driver 2016-04-02 10:46:10 -06:00
Gregory Nutt
ab3f9b764e Update ChangeLog 2016-04-02 08:16:28 -06:00
Aleksandr Vyhovanec
472115eda9 ARMv7-M: Add support for the IAR compiler 2016-04-02 08:14:09 -06:00
Gregory Nutt
bd2da2f543 ARMv7-M: Add toolchain option to select the IAR tools. Move ARMv7-M assembly language into a gnu/ subdirectory. Makefile selects iar/ or gnu/ directory based upon tool configuration 2016-04-02 07:53:52 -06:00
Aleksandr Vyhovanec
29ab0fb991 STM32: Add support for the IAR compiler 2016-04-02 06:58:55 -06:00
Aleksandr Vyhovanec
3770b69572 Update compiler.h to support IAR compiler 2016-04-02 06:24:36 -06:00
Frank Benkert
2234d7d8e5 SAMV7: USBHS: make the last patch also working for non-control-endpoints 2016-04-02 06:12:27 -06:00
Gregory Nutt
02978c797a i.MX6: Straighten up some glock gating 2016-04-01 14:52:17 -06:00
Gregory Nutt
84b399136e GIC: Level or edge sensitive interrupt? 2016-04-01 13:26:57 -06:00
Gregory Nutt
f698f3dcbe ARMv7-A GIC: Fix another initialization errors 2016-04-01 08:53:43 -06:00
Gregory Nutt
ddc1b88027 ARMv7-A GIC: Fix some initialization errors 2016-04-01 08:40:51 -06:00
Gregory Nutt
855c9a5225 ARMv7-A GIC: Move debug logic to a separate file; fix some errors in debug logic. 2016-04-01 06:58:49 -06:00
Gregory Nutt
37cacc6178 ARMv7 GIC: Fix some formatting errors in GIC debug output 2016-03-31 18:26:15 -06:00
Gregory Nutt
a6fff34ec6 Update TODO list 2016-03-31 18:02:51 -06:00
Gregory Nutt
70683d08bc i.MX6: Add GIC debug output 2016-03-31 17:25:04 -06:00
Frank Benkert
d1065e876f SAMV7: USBHS: Reset the TXIN bit not before new data was written or all requests are completed. 2016-03-31 14:20:36 -06:00
Sebastien Lorquet
6d96f24d98 Enable RNG interrupts only when needed. 2016-03-31 13:43:00 -06:00
Gregory Nutt
af027f2a18 Update submodules 2016-03-31 13:37:04 -06:00
Gregory Nutt
29cae97367 i.MX6: Fix several problems with peripheral pin configuration 2016-03-31 13:36:06 -06:00
Gregory Nutt
9a9566faba i.MX6 Add more debug instrumentation; Fix setting of CCM register. 2016-03-31 10:49:35 -06:00
Gregory Nutt
756e6050e4 ARMv7-A: Need to set bits in the ICDDCR to enable forwarding of interrupts 2016-03-31 09:18:55 -06:00
Gregory Nutt
12064b276a ARMv7-A: Fix an error in GIC initialization 2016-03-31 08:05:12 -06:00
Gregory Nutt
9b81319fb1 i.MX6: OCRAM should be cacheable 2016-03-31 07:25:30 -06:00
Gregory Nutt
bbbb615c31 Remove references to VSN from README; update ChangeLog 2016-03-30 18:13:45 -06:00
Gregory Nutt
eb6fbc3059 Trivial changes from review of last PR 2016-03-30 14:44:29 -06:00