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Author SHA1 Message Date
Jan Charvat
0d9d2f4bf8 boards/risc-v/esp32c3: ESP32C3 TWAI (CAN) controller bringup for DevKitM-1. 
Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
 2022-04-15 22:55:26 +08:00
Jan Charvat
6ec86361a8 arch/riscv/esp32c3: ESP32C3 TWAI (CAN) controller included into Kconfig. 
Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
 2022-04-15 22:55:26 +08:00
Jan Charvat
e28584131d arch/riscv/esp32c3: ESP32C3 TWAI (CAN) controller driver. 
Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
 2022-04-15 22:55:26 +08:00
Jan Charvat
0fa1541a80 arch/riscv/esp32c3: esp32c3_twai.h TWAI (CAN) controller registers provided by Espressif. 
File provided by Abdelatif Guettouche

Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
 2022-04-15 22:55:26 +08:00
Huang Qi
a94c865791 arch/risc-v: Use fs status definition from csr.h 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-15 19:41:31 +08:00
Petro Karashchenko
09b3fb25ab drivers: remove unimplemented open/close/ioctl interfaces 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-04-15 16:56:25 +08:00
Xiang Xiao
6041a2f0db boards/esp32_twai: Remove arm_arch.h from comment 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-15 11:50:02 +03:00
Xiang Xiao
382b6d3b6f boards/arm/a1x: Remove the check CONFIG_ARCH_FPU around arm_fpuconfig 
forget in below change:
commit df5a8a53ae
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date:   Tue Apr 12 03:18:46 2022 +0800

    arch/arm: Move FPU initialization to common place

    Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-14 23:09:42 +03:00
Richard Tucker
1b13d1b440 arch/arm/src/sam34/Kconfig: fix typo in device name 2022-04-15 02:22:01 +08:00
Richard Tucker
de66e18d6f arch/arm/src/sam34/sam_hsmci.c: SAM3X GPIO setup 2022-04-15 02:22:01 +08:00
Richard Tucker
929556d750 arch/arm/src/sam34/sam_hsmci: DMA also present on SAM3X chips 2022-04-15 02:22:01 +08:00
Richard Tucker
be0bcac91b arch/arm/src/sam34/sam_hsmci.c: DMA setup before write is required 2022-04-15 02:22:01 +08:00
Richard Tucker
bc7f4b2375 arch/arm/src/sam34/sam_hsmci.c: delay required after sending command 2022-04-15 02:22:01 +08:00
chao.an
dc961baaea arm/armv7-[a|r]: move fpu save/restore to assembly handler 
Save/Restore FPU registers in C environment is dangerous practive,
which cannot guarantee the compiler won't generate the assembly code
with float point registers, especially in interrupt handling

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-14 22:33:10 +08:00
Xiang Xiao
f14eed6432 vfs/fcntl: Minor style fix 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-14 17:21:25 +03:00
liuhaitao
05cc6fb610 fs/fcntl: add O_APPEND flag judge in fcntl 
Signed-off-by: liuhaitao <liuhaitao@xiaomi.com>
 2022-04-14 17:21:25 +03:00
Xiang Xiao
bb1e81eb95 driver/mmcsdio: do not hold the semaphore in idle thread too 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-14 17:12:10 +03:00
chao.an
062010c660 driver/mmcsdio: do not hold the semaphore on interrupt context 
so we can do the full dump to mmc/sd card in the panic case

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-14 17:12:10 +03:00
Alan C. Assis
c232be541c Add SPIRAM to ESP32-S2 2022-04-14 22:10:23 +08:00
anjiahao
a66e8f20ee libc/string:add LICENSE info 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-14 21:46:12 +08:00
haopengxiang
fa9ad9b398 libc/string:delete small to big endian marco 
avoid byte alignment
Signed-off-by: haopengxiang <haopengxiang@xiaomi.com>
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-14 21:46:12 +08:00
chao.an
c3cefe6da2 libc/string: Use Byte-Shift algorithm for very long needles 
Reference here:
https://github.com/taleinat/byteshift_strstr

Signed-off-by: chao.an <anchao@xiaomi.com>
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-14 21:46:12 +08:00
Ville Juven
47945e83b2 MPFS: Set correct interrupt per mode (M-/S-mode) for mtimer 2022-04-14 16:36:06 +03:00
Xiang Xiao
a94b7b9cca arm/rtl8720c: Remove up_getsp which is already implemented in arch/arm/arch.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-14 16:35:52 +03:00
chao.an
b3d47e246f arch/stack_color: correct the stack top of running task 
This PR to ensure the stack pointer is locate to the stack top

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-14 16:48:19 +08:00
chao.an
0c79ad9d8d arch/[arm|sparc]: replace INT32_ALIGN_* to STACK_ALIGN_* 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-14 16:48:19 +08:00
Ville Juven
c2b69cc2c9 RISC-V: mtimer register via SBI when S-mode is in use 
Cannot access the memory mapped registers directly when the kernel
runs in S-mode, must forward the access to SBI.
 2022-04-14 16:43:34 +08:00
Ville Juven
3d6ab5c804 RISC-V: Add SBI glue logic 
Currently only stubs for mtime handling added, with a gentle reminder
that the actual implementation is still missing.
 2022-04-14 16:43:34 +08:00
Xiang Xiao
701bbaac74 sched/environ: Ensure tg_envp terminated by double '\0' 
so we can compute the whole environ string length from it

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-14 07:49:00 +03:00
zhanghongyu
4c693239c0 fix: usrsock iovec_do skip empty iov 
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
 2022-04-14 02:47:31 +08:00
zhanghongyu
f60480a5db rpmsg_usrsock: Support the wireless ioctl which contain pointer 1/2 
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
 2022-04-14 02:47:31 +08:00
anjiahao
a191d9bc3c sched/pthread_create:fix bug,delete data_sem 
if a pthread set attr is detach,and when call pthread_create,
new thread exit quikly,new thread's tcb be free,then pthread_create
use new thread's tcb will crash.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-14 01:42:16 +08:00
Abdelatif Guettouche
a5c64adbe4 arch/Kconfig: Move the DUMP_ON_EXIT option out of the Bring-up group. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-13 21:59:23 +08:00
Abdelatif Guettouche
6d12ee19e2 arch: Move the DUMP_ON_EXIT logic after nxtask_exit. 
Otherwise we will try to dump the state of the current task, however the
exit handler has already started doing some cleanup and invalidated its
group.  Accessing the group from dumponexit will crash.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-13 21:59:23 +08:00
Abdelatif Guettouche
d6c952c56f arch: Fix compile error when enabling CONFIG_DUMP_ON_EXIT 
"error: incompatible types when assigning to type 'struct filelist *' from type 'struct filelist'
   filelist = tcb->group->tg_filelist;"

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-13 21:59:23 +08:00
Ville Juven
190e3aded3 MPFS: Use riscv_exception_attach like the others do 
Exception / fault handling goes to unexpected ISR, fix by setting the
common ISR handlers like all other RISC-V platforms do.
 2022-04-13 21:56:21 +08:00
Ville Juven
2b29dec5e0 MPFS: Fix mtimecmp address 
MTIMECMP0 was incorrect
 2022-04-13 21:56:21 +08:00
Xiang Xiao
4b9c74514d drivers/power: Remove activity_governor.h and greedy_governor.h 
since they aren't really used anymore

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-13 15:38:46 +03:00
zhuyanlin
5cc4f22b43 power/governor: Remove the duplicated function prototype 
since they are declared include/nuttx/power/pm.h by:
commit 5ce181e6b7
Author: zhuyanlin <zhuyanlin1@xiaomi.com>
Date:   Mon Feb 14 15:32:40 2022 +0800

    power:govorner: add govorner to per domain.

    For mult domains scene,,
    activity and greety can be used at same time.
    Let user to select domain governor.

    Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>

and add static const to g_pmgovernor

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-04-13 15:38:46 +03:00
Huang Qi
f5cf35784e arch/risc-v: Correct format of 32-bit insn in misaligned handler 
FIx:
Format specifies type 'unsigned long' but the argument has type 'uint32_t' (aka 'unsigned int')

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-13 18:33:36 +08:00
Huang Qi
898d789a5f arch/risc-v/riscv_misaligned: Correct sw source register 
If source register of sw instruction is x0, we must point it to a constant zero
since in NuttX's context,
value of index 0 is EPC.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-13 18:33:36 +08:00
Ville Juven
370152f3ba RISC-V: Move mhartid to own assembly macro+function 
Hartid and cpuindex are not the same thing. Hartid is needed regardless
of SMP, for external interrupt handling etc.

SMP needs cpuindex which might not be index == hartid, so both are
needed. IMO it is clearer to provide separate API for both.

Currently the implementation of up_cpu_index is done a bit lazily,
because it assumes hartid == cpu index, but this is not 100% accurate,
so it is still missing some logic.
 2022-04-13 12:00:40 +02:00
anjiahao
e6f77aeb9a libc/lib_strptime:change code format & add notes 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-13 10:16:42 +08:00
Xiang Xiao
96ea9b71ed libc/strptime: fix warning unused-value 
warning: value computed is not used [-Wunused-value]
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-13 10:16:42 +08:00
anjiahao
6d3f14d41d libc/strptime:_conv_num skip space 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-13 10:16:42 +08:00
liuhaitao
366c25682c libc/time: add strptime porting support 
lib_strptime.c copies from android bionic/libc/tzcode.

Signed-off-by: liuhaitao <liuhaitao@xiaomi.com>
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-13 10:16:42 +08:00
Jukka Laitinen
dbc163f1b0 fs/vfs/fs_truncate.c: Use ioctl to truncate on non-mountpoint inode 
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2022-04-13 09:40:18 +08:00
chao.an
0d7ea348d5 arm/armv8-m: indicating no low-overhead-loop predication by default 
Fix usage fault on clang version 13.0.0 (-Ofast):
------------------------------------------------------------------
| arm_hardfault: Hard Fault escalation:
| arm_usagefault: PANIC!!! Usage Fault:
| arm_usagefault:  IRQ: 3 regs: 0x3c58c510
| arm_usagefault:  BASEPRI: 00000080 PRIMASK: 00000000 IPSR: 00000003 CONTROL: 00000004
| arm_usagefault:  CFSR: 00020000 HFSR: 40000000 DFSR: 00000000 BFAR: 01608050 AFSR: 00000000
| arm_usagefault: Usage Fault Reason:
| arm_usagefault:  Invalid state
| up_assert: Assertion failed at file:armv8-m/arm_usagefault.c line: 113 task: lpwork
| backtrace:
| [ 2] [<0x2c58124a>] up_backtrace+0xa/0x2e2
| [ 2] [<0x2c56f7cc>] sched_dumpstack+0x28/0x66
| [ 2] [<0x2c580cd0>] up_assert+0x62/0x254
| [ 2] [<0x2c56ab8a>] _assert+0/0xa
| [ 2] [<0x2c55575a>] nxsched_add_prioritized+0x38/0xa2
| [ 2] [<0x2c555894>] nxsched_add_blocked+0x2e/0x44
| [ 2] [<0x2c580748>] up_block_task+0x2a/0x96
| [ 2] [<0x2c5569ea>] nxsem_wait+0x64/0xb4
| [ 2] [<0x2c556a40>] nxsem_wait_uninterruptible+0x6/0x10
| [ 2] [<0x2c559b9a>] work_thread+0x1c/0x48
-------------------------------------------------------------------

usage fault on 0x2c55575a:

------------------------------------
|2c555722 <nxsched_add_prioritized>:
|; {
|2c555722: 80 b5         push  {r7, lr}
|...
|2c55575a: 2f f0 17 c0   le  0x2c555732 <nxsched_add_prioritized+0x10> @ imm = #-44
|...
------------------------------------

Arm v8-M Architecture Reference Manual:

C2.4.103 LE, LETP

B3.28 Low overhead loops:

An INVSTATE UsageFault is raised if a LE instruction is executed and FPSCR.LTPSIZE does not read as four.
When a new floating-point context is created and FPCCR.ASPEN is set to zero it is the responsibility of software
to correctly initialize FPSCR.LTPSIZE.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-13 09:39:22 +08:00
chao.an
ff210e1c2d arch/stack_color: correct the end address of stack color 
The different optimization of compilers will cause ambiguity in
obtaining sp through up_getsp() in arm_stack_color(), if compile
with clang and enable the optimization flag (-Ofast), up_getsp()
call will be earlier than push {r0-r9,lr}, the end address of color
stack will overlap with saved registers.

Compile line:
clang --target=arm-none-eabi -c "-Ofast" -fno-builtin -march=armv8.1-m.main+mve.fp+fp.dp \
-mtune=cortex-m55 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -D__NuttX__ -common/arm_checkstack.c -o  arm_checkstack.o

Assembler code:
llvm-objdump -aS arm_checkstack.o
------------------------------------
|00000000 <arm_stack_color>:
|;   start = INT32_ALIGN_UP((uintptr_t)stackbase);
|       0: c2 1c         adds  r2, r0, #3
|       2: 22 f0 03 02   bic r2, r2, #3
|;   end   = nbytes ? INT32_ALIGN_DOWN((uintptr_t)stackbase + nbytes) :
|       6: 19 b1         cbz r1, 0x10 <arm_stack_color+0x10> @ imm = #6
|       8: 08 44         add r0, r1
|       a: 20 f0 03 00   bic r0, r0, #3
|       e: 00 e0         b 0x12 <arm_stack_color+0x12> @ imm = #0
|;   __asm__
|      10: 68 46         mov r0, sp                               <--- fetch the sp before push {r7 lr}
|      12: 80 b5         push  {r7, lr}                           <--- sp changed
|;   nwords = (end - start) >> 2;
|      14: 80 1a         subs  r0, r0, r2
|      16: 80 08         lsrs  r0, r0, #2
|; }
|      18: 08 bf         it  eq
|      1a: 80 bd         popeq {r7, pc}
|      1c: 4b f6 ef 63   movw  r3, #48879
|      20: cd f6 ad 63   movt  r3, #57005
|      24: a0 ee 10 3b   vdup.32 q0, r3
|;   while (nwords-- > 0)
|      28: 20 f0 01 e0   dlstp.32  lr, r0
|;       *ptr++ = STACK_COLOR;                                    <--- overwrite
|      2c: a2 ec 04 1f   vstrw.32  q0, [r2], #16
|      30: 1f f0 05 c0   letp  lr, 0x2c <arm_stack_color+0x2c> @ imm = #-8
|; }
|      34: 80 bd         pop {r7, pc}
------------------------------------

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-13 09:37:54 +08:00
Xiang Xiao
df5a8a53ae arch/arm: Move FPU initialization to common place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-12 23:35:06 +03:00