Commit Graph

211 Commits

Author SHA1 Message Date
chao an
563125fde3 make/archive: Use the full path name when matching or storing names in the archive
This pr will avoid targets with the same name can not be archive in the same library

Signed-off-by: chao an <anchao@xiaomi.com>
2023-08-26 01:21:10 +08:00
Anner J. Bonilla
24e45d071e Pinephone Pro port just nsh
Pinephone Pro port just nsh

Status:
booting till GICD / IRQ issue

style cleanups

start to fix style checks

revert offset

whitespaces

revert a64 bringup file

prob last cleanup

more cleanups

remove dts

move changes from a64 hardware specific folders to rk3399

undo common changes (except head.s)

revert gitignore

missing irq.h and rk3399_serial.c need to finish cleaning them up

WIP

add source for load address

make debug print hex again add board include

Pinephone Pro port just nsh

Status:
booting till GICD / IRQ issue

style cleanups

start to fix style checks

revert offset

whitespaces

revert a64 bringup file

prob last cleanup

more cleanups

remove dts

move changes from a64 hardware specific folders to rk3399

undo common changes (except head.s)

revert gitignore

missing irq.h and rk3399_serial.c need to finish cleaning them up

WIP

add source for load address

remove ccache, add board memory map

remove board reset
2023-08-24 11:16:31 +08:00
cuiziwei
1a8027d625 nuttx/arch:add -Wno-psabi to Toolchain.defs
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2023-08-22 01:33:30 +08:00
qinwei1
630b5f32a2 arm64: IMX8 MEK board support
Summary

   Support for imx8qm MEK evaluate board

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-08-21 14:23:05 +08:00
qinwei1
30354e5767 arm64: IMX8 platform (Cortex-A53) support
Summary

   Support for imx8 platform, this is a very initialize version

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-08-21 14:23:05 +08:00
qinwei1
5b7267bf66 arm64: remove unnecessary trace interface
Summary
    this is a old implement for Arm64 trace but will failed
compile when enable CONFIG_SCHED_INSTRUMENTATION_SWITCH
    remove it since it will never use for trace framework

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-08-21 09:49:02 +08:00
hujun5
f1b6cf78da arch/arm: add CONFIG_ARCH_TRUSTZONE_SECURE to some code
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-08-21 00:06:25 +08:00
hujun5
a96c6f1abf arch/arm: Add the secure handling to gic
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-08-21 00:06:25 +08:00
Xiang Xiao
7bb563dfe9 arch/arm: Remove CONFIG_ARCH_TRUSTZONE_BOTH related stuff
represent tee by CONFIG_ARCH_TRUSTZONE_SECURE instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-08-21 00:06:25 +08:00
chenrun1
709301cbfd hostfs:support SEEK_CUR
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2023-08-19 01:48:48 +08:00
Xiang Xiao
14563aa48c arch/armv7r: Sync gic/timer with armv7-a and armv8-a
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-08-14 14:51:01 -03:00
Xiang Xiao
bd30d1a4d5 arch: Move trustzone related setting to common place
to share the security setting between arm32 and arm64

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-08-13 08:43:01 +02:00
wangming9
c928acc9ff perf: The new configuration supports hardware performance counting
Adding the CONFIG_ARCH_PERF_EVENTS configuration to enable
hardware performance counting,solve the problem that some platform
hardware counting support is not perfect, you can choose to use
software interface.

This is configured using CONFIG_ARCH_PERF_EVENTS, so weak_functions
are removed to prevent confusion

To use hardware performance counting, must:
1. Configure CONFIG_ARCH_PERF_EVENTS, default selection
2. Call up_perf_init for initialization

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-12 02:20:44 +08:00
liaoao
dffab1e0c6 qemu: add devicetree support for arm64
Signed-off-by: liaoao <liaoao@xiaomi.com>
2023-08-11 00:46:50 +08:00
qinwei1
37e69cdeb0 arch/arm64: enable for arm64 virt to choice CPU core
Summary
    Qemu virt board can choice CPU core with boot parameter
and we need to add Konfig option for choice
    the change do this

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-08-10 20:48:19 +08:00
qinwei1
d8e1022b6f arm64: add hostfs support
Sumary
   add hostfs support for arm64, it's a copy
from arm32.

Note:
   it's not support for opendir and readdir, command
like ls will not work.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-08-10 17:58:34 +08:00
wangming9
f4e33e488d arch/arm64: Fixed arm64 backtrace support for other processes
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-10 13:35:59 +08:00
wangbowen6
9aa57b6c53 virtio: add virtio framework in NuttX
1. virtio devics/drivers match and probe/remote mechanism;
2. virtio mmio transport layer based on OpenAmp (Compatible with both
   virtio mmio version 1 and 2);
3. virtio-serial driver based on new virtio framework;
4. virtio-rng driver based on new virtio framework;
5. virtio-net driver based on new virtio framework
   (IOB Offload implementation);
6. virtio-blk driver based on new virtio framework;
7. Remove the old virtio mmio framework, the old framework only
   support mmio transport layer, and the new framwork support
   more transport layer and this commit has implemented all the
   old virtio drivers;
8. Refresh the the qemu-arm64 and qemu-riscv virtio related
   configs, and update its README.txt;

New virtio-net driver has better performance
Compared with previous virtio-mmio-net:
|                        | master/-c | master/-s | this/-c | this/-s |
| :--------------------: | :-------: | :-------: | :-----: | :-----: |
| qemu-armv8a:netnsh     |  539Mbps  |  524Mbps  | 906Mbps | 715Mbps |
| qemu-armv8a:netnsh_smp |  401Mbps  |  437Mbps  | 583Mbps | 505Mbps |
| rv-virt:netnsh         |  487Mbps  |  512Mbps  | 760Mbps | 634Mbps |
| rv-virt:netnsh_smp     |  387Mbps  |  455Mbps  | 447Mbps | 502Mbps |
| rv-virt:netnsh64       |  602Mbps  |  595Mbps  | 881Mbps | 769Mbps |
| rv-virt:netnsh64_smp   |  414Mbps  |  515Mbps  | 491Mbps | 525Mbps |
| rv-virt:knetnsh64      |  515Mbps  |  457Mbps  | 606Mbps | 540Mbps |
| rv-virt:knetnsh64_smp  |  308Mbps  |  389Mbps  | 415Mbps | 474Mbps |
Note: Both CONFIG_IOB_NBUFFERS=64, using iperf command, all in Mbits/sec
      Tested in QEMU 7.2.2

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
2023-08-10 03:39:39 +08:00
zhangyuan21
79242cc1e7 arm64: set cpuid according to mpidr
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-08-03 03:19:19 -07:00
zhangyuan21
dc55205ee5 arch/arm64: get_cpu_id according to the correct affinity level
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-08-03 03:19:19 -07:00
yanghuatao
51240c658f fix warning: [-Wunknown-pragmas]
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:33: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   33 | #pragma clang diagnostic push
      |
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:34: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   34 | #pragma clang diagnostic ignored "-Wpadded"
      |
In file included from /mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/types.h:4,
                 from /mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/IBase.h:4,
                 from android/hidl/base/1.0/BaseAll.cpp:1:
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:40: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   40 | #pragma clang diagnostic pop
      |
In file included from /mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/IBase.h:4,
                 from android/hidl/base/1.0/BaseAll.cpp:1:
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/types.h:188: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
  188 | #pragma clang diagnostic push
      |
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/types.h:189: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
  189 | #pragma clang diagnostic ignored "-Wc++17-extensions"
      |
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/types.h:195: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
  195 | #pragma clang diagnostic pop
      |
CXX:  LightRefBase.cpp In file included from base/HidlSupport.cpp:18:
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:33: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   33 | #pragma clang diagnostic push
      |
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:34: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   34 | #pragma clang diagnostic ignored "-Wpadded"
      |
In file included from base/HidlSupport.cpp:18:
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:40: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   40 | #pragma clang diagnostic pop

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2023-08-03 00:52:53 -07:00
zhangyuan21
8f39ba6ae4 arch: update g_running_tasks when context switch occurred
When supporting high-priority interrupts, updating the
g_running_tasks within a high-priority interrupt may be
cause problems. The g_running_tasks should only be updated
when it is determined that a task context switch has occurred.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-08-01 09:35:18 -07:00
Bowen Wang
28cb5e7984 arm64: add kasan support for arm64
Add kasan compiler option in arm64 Toolchain.defs

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2023-07-31 05:45:46 -07:00
zhangyuan21
f9cab5b9dc arch/arm64: add ARM64_DCACHE_DISABLE and ARM64_ICACHE_DISABLE config
Enable dcache and icache when ARM64_DCACHE_DISABLE and ARM64_ICACHE_DISABLE
disabled at __start.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-07-31 05:33:23 -07:00
Bowen Wang
d24622888f arm64_backtrace: use running_task if arch_get_current_tcb return NULL
In the init phase of the OS, arch_get_current_tcb return NULL. Enable
the memory backatrace default will crash in backtrace function.

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2023-07-31 04:52:49 -07:00
dongjiuzhu1
14446677d3 arch/arm64: default select ARCH_HAVE_SETJMP
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2023-07-28 20:57:26 -07:00
hujun5
68187b68af arch: move [enter|leave]_critical_section
move [enter|leave]_critical_section to the same place for easy to understand
and call matching

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-07-27 11:34:09 +02:00
guoshichao
3524f4b9ce libs/libc/fork: add lib_fork implementation
1. add lib_fork api in libs/libc, we need a fork() api to implement the
fork relative method, such as pthread_atfork
2. rename the assembly fork entry function name to up_fork(), and rename
the up_fork() to arch specific name, such as
sim_fork()/arm_fork()/mips_fork() etc.

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2023-07-26 10:41:52 +02:00
Xiang Xiao
46b25b3849 arch: Compute the array size by nitems
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-07-26 09:33:38 +02:00
Xiang Xiao
f3269a6caa sched: Rename DEBUG_TCBINFO to ARCH_HAVE_TCBINFO
and select if the arch support to define g_tcbinfo variable

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-07-26 09:33:38 +02:00
anjiahao
d5347d8915 arm64:fix ostest failed to run
The reason for the failure is incorrect sp,
resulting in the failure to restore the register

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-07-25 16:37:49 -03:00
anjiahao
8abf803a1d arm64:Need to store native sp pointer to tcb
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-07-23 21:59:35 -07:00
anjiahao
ceb6bb6650 arm64:support arm64 for tcb info
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-07-23 21:59:35 -07:00
chao an
4b94dc3092 toolchain/gcc: fix linker error if enable STACK_CANARIES/LTO at same time
If -fstack-protector-all is enabled, gcc linker will need GCC
SSP(Stack Smashing Protector) support, Since the implement of SSP
is related to the OS, most of embedded toolchain does not provide
ssp support, so an error will be reported when linking:

enable CONFIG_LTO_FULL && CONFIG_STACK_CANARIES

arm-none-eabi/bin/ld: cannot find -lssp_nonshared: No such file or directory
arm-none-eabi/bin/ld: cannot find -lssp: No such file or directory

https://github.com/gcc-mirror/gcc/blob/master/gcc/gcc.cc#L983-L985

Since nuttx has already implemented SSP related hook functions,
so in this PR, we filter out this option in the link phase to ensure that
the implementation of lssp/lssp_nonshared will not be referenced

Signed-off-by: chao an <anchao@xiaomi.com>
2023-07-21 01:13:34 +08:00
zhangyuan21
b7216d54ff arm64: Use the correct cpu id for fpu idle task init
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-07-14 01:17:02 +08:00
simbit18
b0965ab963 Fix nuttx coding style
Remove TABs
Fix indentation
Fix Multi-line comments
Fix Comments to the Right of Statements.
2023-07-14 01:16:06 +08:00
zhangyuan21
601202ee4a arm64: Use the correct aff in up_affinity_irq function
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-07-14 01:13:01 +08:00
guoshichao
c33d1c9c97 sched/task/fork: add fork implementation
1. as we can use fork to implement vfork, so we rename the vfork to
fork, and use the fork method as the base to implement vfork method
2. create the vfork function as a libc function based on fork
function

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2023-07-12 02:27:37 +08:00
yanghuatao
4d9f67940c nuttx/toolchain: Add macro _LDBL_EQ_DBL to nuttx/arch/arm64/src/Toolchain.defs
Fix goldfish build toolchain math library error:
/mnt/yang/vela_Goldfish/nuttx/include/libcxx/cmath:454:9: error: 'nexttowardf' has not been declared in '::'
  454 | using ::nexttowardf;
      |         ^~~~~~~~~~~
/mnt/yang/vela_Goldfish/nuttx/include/libcxx/cmath:472:9: error: 'acosl' has not been declared in '::'
  472 | using ::acosl;
      |         ^~~~~
/mnt/yang/vela_Goldfish/nuttx/include/libcxx/cmath:473:9: error: 'asinl' has not been declared in '::'
  473 | using ::asinl;
      |         ^~~~~

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2023-07-11 00:44:45 +08:00
Masayuki Ishikawa
9861d49cd4 arch: arm64: Add arm64_gic_raise_sgi() for SMP
Summary:
- I noticed that arm64_gic_raise_sgi() is not implemented for
  GICv2 which is used for SMP + hypervisor such as qemu + kvm.
- This commit fixes this issue

Impact:
- None

Testing:
- Tested with qemu-7.1 + kvm (linux) and qemu-7.1 + hvf (macOS)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-06-30 16:10:26 +08:00
Masayuki Ishikawa
745f443cbf arch: arm64: Fix to access psci with hypervisor
Summary:
- I noticed that pcsi version can not be obtained with qemu + kvm.
- Also, pci_detect hangs with qemu + hvf.
- This commit fixes this issue by using hvc (hypervisor call).

Impact:
- None

Testing:
- Tested with qemu-7.1 + kvm (linux) and qemu-7.1 + hvf (macOS)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-06-30 16:10:26 +08:00
Masayuki Ishikawa
cf6a134684 arch: arm64: Do not set cntfrq_el0 in qemu_boot.c
Summary:
- During testing with qemu + kvm, I noticed that nuttx hangs
  when setting cntfrq_el0. With qemu + kvm, it starts from
  EL1 because we can not specify virtualization=on
- However, I noticed that it works without setting cntfrq_el0
- This commit fixes this issue

Impact:
- None

Testing:
- Tested with qemu-7.1 (both with kvm and without kvm)
- NOTE: to work with kvm, GICv2 must be used.

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-06-29 20:11:29 +08:00
zhangyuan21
6f8cb7edd3 arch/arm64: Save FPU context when a context switch occurs in SMP mode
In SMP mode, the fpu owner may switch from core0 to core1,
so it is necessary to force saving the FPU context when a
context switch occurs.

This PR fixed the crash issue mentioned in #8799.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-06-13 13:23:28 +09:00
Peter Bee
59450bf9a9 arch/arm64: use adrp instead adr in bss init code
To support address offset larger than 1MB

Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
2023-06-02 11:02:14 -03:00
Masayuki Ishikawa
ec788d9398 arch: fvp-v8r: Fix warning when configuring fvp-armv8r:nsh_smp
Summary:
- I noticed that ./tools/configure.sh fvp-armv8r:nsh_smp shows
  warning: (ARCH_CHIP_FVP_R52 && ARCH_CHIP_FVP_R82) selects ARMV8R_HAVE_GICv3 which has unmet direct dependencies (ARCH_ARM && ARCH_ARMV8R)
- I think ARMV8R_HAVE_GICv3 is only used for aarch32.
- This commit fixes this issue.

Impact:
- None

Testing:
- Tested with nsh_smp on FVP

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-06-02 12:08:27 +08:00
zhangyuan21
9b882b46be arch/arm64: move sgi attach and enable to gic init
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-21 09:58:34 -03:00
zhangyuan21
f8b5fd2a9a arch/arm64: send sgi with correct aff and target list
armv8r and armv8a have different process affinity,
and sgi affinity needs to be able to adapt all of them.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-21 09:58:34 -03:00
qinwei1
ea98e5a92e arm64: gicv3 add arm64_gic_irq_trigger to set irq type
Summary
    For ARM64, it need to set IRQ type(EDGE or LEVEL). it's specific
 for ARM64 PPI or SPI.
    The change add arm64_gic_irq_trigger to set IRQ type

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-05-21 09:58:34 -03:00
qinwei1
ca6cdd16e9 arm64: gicv3 add up_affinity_irq/up_trigger_irq/up_prioritize_irq
Summary
  add up_affinity_irq/up_trigger_irq/up_prioritize_irq for gicv3
these interface is necessary for some drivers

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-05-21 09:58:34 -03:00
qinwei1
28a354f276 arm64: gicv3, add power up sequence for gc600/gc700
Summary:
   GICR_PWRR is a IMPLEMENTATION-DEFINED register for gc700/gc600, which
is following gic v3 and v4.
   Please check GICR_PWRR define at TRM of GIC600/GIC700 for more detail

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-05-21 09:58:34 -03:00
Xiang Xiao
7990f90915 Indent the define statement by two spaces
follow the code style convention

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-21 09:52:08 -03:00
zhangyuan21
36acd4fce5 arch/arm64: .bss initialization using assembly language
The compiler will optimize boot_early_memset to memset,
but memset in libc cannot be used before MMU is enabled.
Therefore, assembly language is used to implement the
initialization of bss to avoid this problem.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-19 21:38:07 -07:00
zhangyuan21
548424713b arch/arm64: Each core initializes its own idle stack in SMP
When the MMU/MPU of core0 is enabled while those of other cores are not,
it is unsafe to operate the idle stack simultaneously. The idle stack
of other cores will be flushed by the contents in the cache of core0,
therefore it is necessary to initialize the idle stack and let each
core handle it on its own.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-19 17:41:48 +08:00
zhangyuan21
4466c3d6e9 arm64/cache: Support unalign cache clean.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-18 15:45:42 +03:00
Xiang Xiao
7dc0d70092 arch: Save sigdeliver into xcp in the case of signal self delevery
to avoid the infinite recusive dispatch:
*0  myhandler (signo=27, info=0xf3e38b9c, context=0x0) at ltp/testcases/open_posix_testsuite/conformance/interfaces/sigqueue/7-1.c:39
*1  0x58f1c39e in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:167
*2  0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*3  0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049334) at signal/sig_dispatch.c:115
*4  0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049334) at signal/sig_dispatch.c:435
*5  0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*6  0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*7  0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*8  0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049304) at signal/sig_dispatch.c:115
*9  0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049304) at signal/sig_dispatch.c:435
*10 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*11 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*12 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*13 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf40492d4) at signal/sig_dispatch.c:115
*14 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf40492d4) at signal/sig_dispatch.c:435
*15 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*16 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*17 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*18 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf40492a4) at signal/sig_dispatch.c:115
*19 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf40492a4) at signal/sig_dispatch.c:435
*20 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*21 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*22 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*23 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049274) at signal/sig_dispatch.c:115
*24 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049274) at signal/sig_dispatch.c:435
*25 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*26 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*27 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*28 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049244) at signal/sig_dispatch.c:115
*29 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049244) at signal/sig_dispatch.c:435
*30 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*31 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-17 11:53:18 -06:00
Lee Lup Yuen
4ed48c33e9 arm64/a64: Add support for Multiple UART Ports
Currently only Port UART0 is supported for Allwinner A64. This PR adds support for all UART Ports: UART1 to UART4. (Except R-UART, which is a special low-power UART)

This is required for the upcoming LTE Modem Driver (Quectel EG25-G) for PINE64 PinePhone, which uses UART3. [(Details here)](https://lupyuen.github.io/articles/lte2)

The code was adapted from the NuttX UART Driver for Allwinner A1X: [`a1x_serial.c`](https://github.com/apache/nuttx/blob/master/arch/arm/src/a1x/a1x_serial.c)

`arch/arm64/src/a64/a64_serial.c`: Added ports UART1 to UART4, based on [`a1x_serial.c`](https://github.com/apache/nuttx/blob/master/arch/arm/src/a1x/a1x_serial.c)

`arch/arm64/src/a64/a64_serial.h`: Added IRQs for UART1 to UART4. Moved UART Base Addresses to `a64_memorymap.h`

`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added UART Base Addresses for UART0 to UART4

`arch/arm64/src/a64/Kconfig`: Added UART1 to UART4 to Allwinner A64 Peripheral Selection menu

`boards/arm64/a64/pinephone/configs/lcd/defconfig`, `lvgl/defconfig`, `nsh/defconfig`, `sensor/defconfig`: Fixed `UART1_SERIAL_CONSOLE` to `UART0_SERIAL_CONSOLE`
2023-05-11 09:41:18 +02:00
simbit18
2909260f91 arch/arm64/Kconfig: Fix help attribute
Replace help => ---help---
2023-05-10 22:51:11 +08:00
hujun5
6e71527af2 arch/arm64: 64 bit platform compile error reported
compile error log:
common/arm64_arch_timer.c: In function 'arm64_tick_max_delay':
common/arm64_arch_timer.c:178:12: error: conversion from 'long unsigned int' to 'clock_t' {aka 'unsigned int'} changes value from '18446744073709551615' to '4294967295' [-Werror=overflow]
  178 |   *ticks = UINT64_MAX;
      |            ^~~~~~~~~~

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-10 09:06:59 +02:00
hujun5
7f4cb3057a arch/arm64: merge serial_pl011.c and qemu_serial.c
At present, the serial drivers qemu_serial.c and serial_pl011.c on the fvp-v8r and qemu platforms in arm64 are duplicated
and need to be merged. The plan is to place them under the drivers\serial directory to create a common code module,
so that both fvp-v8r and qemu can use the same code.
In the future, if new platforms use pl011 serial ports, they can also be directly reused

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-10 09:06:59 +02:00
qinwei1
2eac660ff6 arm64: Updating ARCH_EARLY_PRINT support
Summary:
  Keeping this option out of depend on any common serial.
Using the option, need to implement xxx_lowputc.S/c.
  You can also logging the booting message through rewriting
fake arm64_lowputc with other debug method (eg semihosting,
ARM debug channel etc).

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-05-09 21:00:48 +08:00
chao an
25bce71b14 arm64/makefile: preprocess link script to make configure more flexibly
1. arm64/makefile: preprocess link script to make configure more flexibly
2. arm64/EXTRA_LIBS: link all staging library

Signed-off-by: chao an <anchao@xiaomi.com>
2023-05-09 20:48:33 +08:00
hujun5
0f243bde33 arch: fix the issue of asynchronous signal processing
in SMP, signal processing cannot be nested, we use xcp.sigdeliver to identify whether there is currently a signal being processed, but this state does not match the actual situation
One possible scenario is that signal processing has already been completed, but an interrupt occurs, resulting in xcp.sigdeliver not being correctly set to NULL,
At this point, a new signal arrives, which can only be placed in the queue and cannot be processed immediately
Our solution is that signal processing and signal complete status are set in the same critical section, which can ensure status synchronization

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-08 09:11:14 +02:00
hujun5
6bf989159e system/signal: in interrupting the context, regs modify logic error
In the interrupt context, we should first save the interrupt context and modify the interrupt register
to execute the signal processing program immediately after exiting the current interrupt

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-07 20:33:46 +08:00
zhangyuan21
841b178782 assert: show stacks with the sp from regs
1. Get the value of sp from dump regs when an exception occurs,
   to avoid getting the value of fp from up_getsp and causing
   incomplete stack printing.
2. Determine which stack the value belongs to based on the value
   of SP to avoid false reports of stack overflow

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-05 13:40:04 +08:00
zhangyuan21
884be2bdb9 assert: Distinguish between assert and exception
CURRENT_REGS may change during assert handling, so pass
in the 'regs' parameter at the entry point of _assert.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-03 14:49:32 +08:00
hujun5
6063c0516e cpu: in SMP pthread_cancel occasionally deadlock
In smp when cpu0 calls up_cpu_resume to release the cpu1 lock, another locked cpu1 did not execute immediately,
and soon cpu0 called up_cpu_resume again, now cpu1 unable to respond to the interrupt at this time, resulting in a deadlock.
Our solution is to restore cpu1 execution from asynchronous to synchronous to ensure that cpu1 is restored.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-04-23 23:33:09 +08:00
qinwei1
c4f3f8801f arm64: Support for FPU profiling with procfs
Summary:

   To reduce the count of FPU context switching will result at a
performance improve with system. it need to balance between
the using of FPU and counts of FPU trap
   the PR submit a base method to see performance counts for
the FPU with NuttX procfs
   Please read README.txt at chapter of FPU Support and Performance
for more information

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-04-22 01:38:21 +08:00
zhangyuan21
dfcba925e7 arch/arm64: add cache enable and disable function
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:22:04 +08:00
zhangyuan21
652fc7648e arch/arm64: Fixed error in getting cache size when there was no mmu
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:22:04 +08:00
zhangyuan21
41f83a0271 arch/arm64: change up_saveusercontext to assembly code
minidump will backtrace failure when use C code to save user context,
because the stack push operation in C code can disrupt the stack information.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:11:00 +08:00
hujun5
ab0b3336c4 arch/arm64:Suppot tickless mode
1 Similar to Linux and zephyr, all implementations are in arm64_arch_timer.c

2 Arm64 tickless is turned off by default. If it needs to be turned on, you need to configure the switch CONFIG_SCHED_TICKLESS ON

3 The implementation strategy for tick/tickless is to use the timer inside the CPU and implement the timer driver based on the ARCH_TIMER framework.

4 We implemented tick_* Callback functions to adapt to the driven interface to avoid time format conversion overhead

5 In arm64_tick_cancel func,The remaining time that is not used, so this value can be ignored without reading the corresponding register to obtain the remaining cycles

6 Currently, tick/tickless can takes effect in SMP and non SMP mode, ostest can pass.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-04-22 01:08:04 +08:00
zhangyuan21
c00498c164 arch/arm: update running task when context switch occurred
The text describes an issue related to the running task in code.
The running task is only used when calling the _assert function
to indicate the task that was running before an exception occurred.
However, the current code only updates the running task during
irq_dispatch, which is suitable for ARM-M architecture but not
for ARM-A or ARM-R architecture, because their context switches
are not done through irq handler. Therefore, if the following
process is followed, the value of the running task will be incorrect:

1. task1 is running, this_task()=task1
2. do_irq is executed, setting running task()=task1
3. task1 switches to task2
4. task2 is running and generates a data abort
5. In the data abort, the _assert function is called,
   and the running task obtained is still task1, but
   the actual task that generated the exception is task2.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 10:14:05 +09:00
zhangyuan21
f5f0af4f9c arch/arm64: fixed backtrace skip calc error
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 02:53:02 +08:00
zhangyuan21
2c599bb9e6 arch/arm64: call PANIC in arm64_fatal_error
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 02:53:02 +08:00
zhangyuan21
e4ae2b48b8 arch/arm64: Obtaining the correct fp pointer
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 02:53:02 +08:00
zhangyuan21
024b13f3ed arch/arm: enable eoimode only select CONFIG_XXX_GIC_EOIMODE
On a GICv2 implementation, setting GICC_CTLR.EOImode to 1 separates
the priority drop and interrupt deactivation operations.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-11 08:54:45 +02:00
zhangyuan21
c239d19df0 nuttx: add more dependent header file
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-11 09:13:32 +03:00
wangming9
a7fc26124d arch/arm64: the arm64 perf interface supports pmu
Summary:
- Support arm64 pmu api, Currently only the cycle counter function is supported.
- Using ARM64 PMU hardware capability to implement perf interface, modify all
  perf interface related code.
- Support for pmu init under smp.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-04-10 16:23:49 -03:00
wangming9
75760a9fdb arch/arm64: Adds custom chip option
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-04-10 16:23:49 -03:00
Xiang Xiao
bc3e6c84e1 arch: Rename up_[early]serialinit to [arm64|riscv|x86_64][early]serialinit
The naming standard at:
https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+Architecture%2C+MCU%2C+and+Board+Interfaces
requires that all MCU-private function begin with the name of the architecture, not up_.

follow the change from: https://github.com/apache/nuttx/pull/930

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-03-27 12:35:04 +03:00
ligd
bb281eedfa cache: add up_get_xcache_linesize() support
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-03-20 17:17:22 +08:00
qinwei1
e3f0f86514 arm64: add arm64_serialinit/arm64_earlyserialinit
Summary:

   add arm64_serialinit/arm64_earlyserialinit function prototype
to arm64_internal.h as common function for arm64 based chip.
   Testing with ostest in SP and SMP

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-05 09:44:51 +08:00
Xiang Xiao
454921eac7 arch/boards: Rename up_lowputc to [arm64|renesas]_lowputc
follow other arch coding style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-03-04 11:08:00 +02:00
qinwei1
d2d954f691 arm64: ARMv8-r(Cortex-R82) support( add FVP platform )
Summary:
   Adding virtual evaluate platform FVP. This FVP board configuration
will be used to emulate generic ARM64v8-R (Cotex-R82)series hardware
platform and provide support for these devices:

 - GICv3 interrupt controllers for ARMv8-r
 - PL011 UART controller(FVP)

Note:
1. ostest is PASSED at fvp ( single core and SMP)
2. the FVP tools can be download from ARM site, please check FVP
  board readme.txt

TODO: merge PL011 UART driver to common place

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-02 13:33:15 +08:00
qinwei2004
fa359e355c Update arm64_head.S 2023-03-01 13:23:48 +08:00
qinwei1
518eb4076e arm64: ARMv8-r(Cortex-R82) support(mpid fix)
Summary
  Different ARM64 Core will use different Affn define, the mpidr_el1
value is not CPU number, So we need to change CPU number to mpid
and vice versa, the patch change the mpid define into platform

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
d5c6b8a94b arm64: add 64-bit time for all arm64 platform
Summary
  For ARM64 architecture, the arch timer is 64-bit,
the CONFIG_SYSTEM_TIME64 need to be enabled just like
x86_64 and risc-v 64

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
4cb5ff3353 arm64: ARMv8-r(Cortex-R82) support(add ARCH_SET_VMPIDR_EL2 option)
Summary

   VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID.
From architecture manual of AArch64, the behave is:
  -reading register MPIDR_EL1 in EL2, it's return real MPIDR_EL1
  -reading register MPIDR_EL1 in EL1, it's return VMPIDR_EL2
  So since NuttX for SMP is running at EL1 to read MPIDR_EL1 for
  identify CPU id, it's need to set VMPIDR_EL2 to MPIDR_EL1 for
  every CPU at boot EL2 stage.
  For some platform, the bootloader or hypervisor will do that at
  the EL2 stage, but not all.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
0841f4dbaa arm64: ARMv8-r(Cortex-R82) support
Summary:

  Adding armv8-r(Cortex-R82) support and modify some common code to
fit the change, the change including:

1. ARM Single Security State Support, ARMv8-R support only single
   security state, and some GIC configure need to change and fit
2. For ARMv8-R, only have EL0 ~ EL2, the code at EL3 is not necessary
   and system register for EL3 is not accessible(gcc will failed when
   access these registers)
3. add base MPU configure for the platform.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
4240723b78 arm64: add ARCH_EARLY_PRINT support
Summary:
  The aarch64 have EL0~El3 execute level and NS/S (security state),
the NuttX should be execute at EL1 in NS(ARmv8-A) or S(ARmv8-R)
state. but booting NuttX have different ELs and state while with
different platform, if NuttX runing at wrong ELs or state it will
be not normal anymore. So we need to print something in arm64_head.S
to debug this situation.
Enabling this option will need to implement up_earlyserialinit and
up_lowputc functions just you see in qemu, if you not sure,
keeping the option disable.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
e5564a9872 arm64: PSCI config support
Summory
   This Power State Coordination Interface (PSCI) defines a standard
interface for power management. the PCSI need to implement handling
firmware at EL2 or EL3 for ARM64. the PSCI maybe not applicable
for arm core without PCSI firmware interface implement.
  Add configure option for it.

Note:
1. ostest is PASSED at qemu and fvp ( single core and SMP)

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
Xiang Xiao
2c5f653bfd Remove the tail spaces from all files except Documentation
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-26 13:24:24 -08:00
Xiang Xiao
8b4ecac6c2 libc: Move math library from libs/libc/math to libs/libm/libm
to prepare the support of other implementation e.g.:
https://github.com/JuliaMath/openlibm
https://gitlab.com/gtd-gmbh/libmcs

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-23 10:40:07 +02:00
Fotis Panagiotopoulos
85ceb7920e Typo fixes. 2023-02-17 11:17:11 -03:00
chao an
3a0fdb019d nuttx: replace all ARRAY_SIZE()/ARRAYSIZE() to nitems()
Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-09 20:05:44 +08:00
Ville Juven
9ac3e841da group_addrenv: Fix call to group_addrenv for targets that don't need it 2023-02-09 00:14:52 +08:00
Ville Juven
f4b82b6405 sched/addrenv: Remove up_addrenv_restore
The function is not relevant any longer, remove it. Also remove
save_addrenv_t, the parameter taken by up_addrenv_restore.

Implement addrenv_select() / addrenv_restore() to handle the temporary
instantiation of address environments, e.g. when a process is being
created.
2023-02-08 02:51:23 +08:00
Nathan Hartman
5f9cb6faf4 drivers/serial: Fix docstrings on UART interrupt handlers 2023-02-07 04:41:36 +08:00
Gustavo Henrique Nihei
e6b204f438 nuttx: Use MIN/MAX definitions from "sys/param.h"
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-02-01 23:47:44 +08:00
yinshengkai
3f97a87162 tools: add separate flags parameter for COMPILE/COMPILEXX
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2023-01-31 13:42:33 +08:00