Commit Graph

1621 Commits

Author SHA1 Message Date
Devansh Purohit
0ffbff84d1 Changed ESP32S3 Chip names based on their configuration and added ESP32S3_CUSTOM chip module
As suggested in PR:12530, changed the default names of ESP32S3WROOM chips to ESP32S3WROOM1N4,
ESP32S3WROOM2N16R8, ESP32S3WROOM2N32R8, ESP32S3MINI1N8.
Also regenerated all the defconfigs for board configurations.
Added a custom ESP32S3 module for custom flash configurations.
Declared ESP32S3_PSRAM_8M variable with prompt
2024-06-21 17:55:42 +08:00
Devansh Purohit
16d14218fc ESP32S3 bootloader.mk file has a typo error. In the file CONFIG_ESP32S2_MCUBOOT_VERSION config variable is declared, while the correct config variable for esp32s3 bootloader.mk file is CONFIG_ESP32S3_MCUBOOT_VERSION which is defined in the .config file when the config is generated for ESP32S3-devkit board. 2024-06-16 23:36:54 +08:00
Neale Ferguson
73b15a87dc Fix SHMODULEFLAGS so that we link dynamically correctly
* arch/risc-v/src/common/Toolchain.defs
  arch/xtensa/src/lx6/Toolchain.defs
  arch/xtensa/src/lx7/Toolchain.defs
  - Define SHMODULEFLAGS etc. for sotest/dynload
  - Add --entry=__start to SHMODULEFLAGS

* boards/arm64/qemu/qemu-armv8a/scripts/Make.defs
  boards/sim/sim/sim/scripts/Make.defs
  - Define SHMODULEFLAGS etc. for sotest/dynload
2024-06-12 23:21:16 -03:00
Tiago Medicci Serrano
480ad6b631 esp: Make the legacy bootloader (IDF bootloader) option visible
This commit enables users to select the legacy bootloader (IDF
bootloader) in `menuconfig` directly. Please note, that this is a
legacy option intended to support devices already deployed and it
isn't recommended for new designs.
2024-06-12 16:11:56 +08:00
Almir Okato
4178f3ede4 esp32s2: remove legacy bootloader support
Deprecate Legacy Boot for ESP32-S2.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-06-04 18:53:14 -03:00
Almir Okato
16f8966fa9 esp32s2: add simple boot support
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.

This commit also removes deprecated code and makes this bootloader
configuration as default for esp32s2 targets and removes the need
for running 'make bootloader' command for it.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-06-04 18:53:14 -03:00
YAMAMOTO Takashi
b3513c0811 esp32s2/esp32s3 textheap: do not require RTC heap
Unlike esp32, kmm memory is executable.
2024-05-24 21:31:42 +08:00
YAMAMOTO Takashi
1ee279c292 nuttx kconfig: rename a few recently-added options
from:
ARCH_TEXT_HEAP_SEPARATE_DATA_ADDRESS
ARCH_TEXT_HEAP_WORD_ALIGNED_READ

to:
ARCH_HAVE_TEXT_HEAP_SEPARATE_DATA_ADDRESS
ARCH_HAVE_TEXT_HEAP_WORD_ALIGNED_READ
2024-05-21 01:11:44 +08:00
YAMAMOTO Takashi
d196f800b0 Add a few optional text heap APIs to support esp32s3
esp32s3's Internal SRAM 1 and External Memory have two separate mappings
for instructions and data.
2024-05-21 01:11:44 +08:00
yinshengkai
20ebe0e64c Replace all asserts in kernel code with ASSERT
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-05-17 10:18:16 -03:00
Tiago Medicci Serrano
a00fbbeb9f espressif: Add option to disable the GIT_DEPTH to pull submodules
By default, submodules are cloned with `--depth=1`. This continues
to be true if `DISABLE_GIT_DEPTH` environment variable is not
defined (and it is not defined by default). But, if defined the
submodules will be fully cloned (without the `--depth` parameter).
2024-05-17 19:10:46 +08:00
simbit18
fb31f06a2f Fix Kconfig style
Remove spaces from Kconfig files
Add TABs
Replace help => ---help---
Add comments
2024-05-17 19:06:11 +08:00
YAMAMOTO Takashi
5df4925672 esp32s3_textheap.c: fix range checks
While there constants are commented as "First and last words of the
D/IRAM region", the _HIGH addresses are actually not in the corresponding
region.
2024-05-15 10:45:10 -03:00
Gao Feng
10c8c39426 xtensa/esp32s3: pending interrupt should be clear while disable GPIO IRQ 2024-05-15 10:36:04 -03:00
Tiago Medicci Serrano
8a37d1ff1c espressif: Minor changes to keep consistency between sources
This commits replicates some changes on files that were originally
written for other Espressif SoCs and inspired new implementations.
Eventually, these new implementations were improved and this commit
replicates these changes on the original sources.
2024-05-14 22:10:45 +08:00
YAMAMOTO Takashi
3a4560ed40 esp32s3: make textheap return i-bus address consistently
Perform I-D translation for extram as well.

Also, use macros from soc.h.
2024-05-14 00:30:21 +08:00
YAMAMOTO Takashi
ab7805062d esp32s3/esp32s2: Fix D_I_BUS_OFFSET
It seems like a wrong copy-and-paste from esp32c3.
Actually, internal memory mapping varies among processors.

esp32s3: lightly tested with wamr aot
esp32s2: not tested (i have no hardware access)
2024-05-13 18:12:21 +08:00
Tiago Medicci Serrano
bc4a020146 Revert "esp32s3: give ESP32S3_APP_FORMAT_LEGACY a prompt"
This reverts commit 2295fa818d.
2024-05-10 01:44:02 +08:00
hujun5
5cee996588 up_putc: int up_putc, enter_critical_section may be called
before kernel has been iniitialized,we use spin_lock_irqsave to replace.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-05-09 13:45:02 +08:00
chenwen@espressif.com
3a9d163aae esp32_c3/pm: Fix assert issue in PM mode
1. Adjust code to avoid PM wakelock->count less than or equal to 0.
    2. Fix some document format issues.

Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-05-07 15:45:32 +08:00
nuttxs
8d3d93e001 Add ESP32-S3 ADC driver 2024-05-07 01:12:05 +08:00
simbit18
0e67a79b94 fix nxstyle
corrected comments in C89 style
2024-05-03 14:15:56 -03:00
YAMAMOTO Takashi
c4f199e929 esp32s3: add a variation with 32MB flash 2024-05-01 23:34:12 +08:00
Eren Terzioglu
622abe0230 arch/xtensa: Fix esp32s3 build warnings 2024-04-30 15:47:39 -03:00
YAMAMOTO Takashi
2295fa818d esp32s3: give ESP32S3_APP_FORMAT_LEGACY a prompt
So that users can enable it.
This fixes a regression in "esp32s3: add simple boot support".
2024-04-30 17:26:12 +08:00
Philippe Leduc
3dc6b4c9bd Add basic support for locales in order to C++ streams to build and work for simple cases (POSIX / C locale).
Fix build with C++ GCC toolchain
2024-04-29 17:34:10 +08:00
Tiago Medicci Serrano
dab1621442 esp32s3: use common espressif code instead of chip-specific.
Most of the functions used to describe the SoCs capabilities are
available for all Espressif's chips. This commit uses this set of
common functions and remove outdated functions that perform the
same operations in a chip level.
2024-04-25 13:43:15 +08:00
chenwen@espressif.com
9735abab36 xtensa/esp32s3: Fix static_assert compilation error 2024-04-25 13:43:15 +08:00
chenwen@espressif.com
ea5583b112 xtensa/esp32s3: Support ESP32-S3 PM standby and sleep.
1. pm configuration demonstrates the use of power management present on the ESP32-S3.
   2. You can use the pmconfig command to test the power management, for details look at
      ``Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst``

Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-04-25 13:43:15 +08:00
Almir Okato
d098c1dc87 esp32s3: add simple boot support
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.

This commit also removes deprecated code and makes this bootloader
configuration as default for esp32s3 targets and removes the need
for running 'make bootloader' command for it.

Other related fix, but not directly to Simple Boot:
- Instrumentation is required to run from IRAM to support it during
initialization. `is_eco0` function also needs to run from IRAM.
- `rtc.data` section placement was fixed.
- Provide arch-defined interfaces for efuses, in order to decouple
board config level from arch-defined values.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-04-17 19:43:05 +08:00
Omar
01aeeaeac6 ESP32S3 I2S GPIO selection master/slave hase same range for BCLK,WS pin 2024-04-10 15:00:45 +08:00
Omar
4c744f1c0e ESP32S3 configuring gpio pin 19 or 20 ( USB_D+/- ) for any purposes 2024-04-10 15:00:45 +08:00
Omar
b864522b65 ESP32S3 I2S BCLK, WSPIN, DINPIN, DOUTPIN pin range changed to 0 48 2024-04-10 15:00:45 +08:00
Xiang Xiao
4ea2aeff6b arch: Remove xxx_intstack_top and xxx_intstack_alloc
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-04-09 16:59:00 -03:00
ligd
4e725ecd44 arch: color the intstack for all the CPUs
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-04-09 16:59:00 -03:00
ligd
3844efb5b8 stack: update up_get_intstackbase API to support cpu id
For crash dump all the CPU intstack

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-04-09 16:59:00 -03:00
simbit18
9967989b02 Fix Kconfig style
Remove spaces from Kconfig files
Remove TABs
Add comments
2024-04-09 10:49:23 +08:00
chenwen@espressif.com
5b83af1607 xtensa/esp32s3: Fix duplicate definition warnings
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-04-03 23:12:43 +02:00
Tiago Medicci Serrano
9520edeb16 espressif/rmt: Fix minor issues regarding formatting and comments
This commit only fix minor issues regarding formatting and comments
2024-04-02 14:50:59 -03:00
Tiago Medicci Serrano
5ba40d083a esp32/rmt: Use the Espressif`s common RMT driver.
This commit implements the common RMT driver (already available for
the other Espressif's xtensa-based devices) for ESP32.
This allows us to have a proper separation between the lower and
upper-half drivers and use the 'ws2812' example to drive WS2812 RGB
LEDs.
2024-04-02 14:50:59 -03:00
Tiago Medicci Serrano
6b73782c27 esp32: Remove outdated/unnecessary code
These functions are no more used directly by NuttX. There is no
need to keep them.
2024-04-02 14:50:59 -03:00
Tiago Medicci Serrano
4b3b22cbeb esp32/rmt: Remove outdated RMT driver
The new common RMT driver - already available for ESP32-S2 and
ESP32-S3 - will be implemented in another commit for ESP32.
2024-03-29 16:14:27 +08:00
Tiago Medicci Serrano
573e1a255f esp32s3/[ble/wifi]: Improve code compatibility between SoCs
Introduces a couple of minor changes to make it easier to keep the
code update between different Espressif's SoCs.
2024-03-29 16:14:27 +08:00
Tiago Medicci Serrano
2f8e0c7fd4 esp32s3/ble: Rearrange types, data and functions order
This commit just rearranges the order of the types, data and
functions without modifying them. This is done to make it look more
similar with ESP32's ble adapter and ease maintanence.
2024-03-29 16:14:27 +08:00
Tiago Medicci Serrano
62fbb7f03a esp32s3/ble: Update the name of the interrupt status flags
In order to avoid confusion with other interrupt status flags used
by the system and the common source, rename it to be more specific.
2024-03-29 16:14:27 +08:00
Tiago Medicci Serrano
c07f8ab312 esp32s3: use common espressif code instead of chip-specific.
Most of the functions used to set the peripherals are available for
all Espressif's chips. This commit uses this set of functions and
remove outdated functions that perform the same operations in a
chip level.
2024-03-29 16:14:27 +08:00
Tiago Medicci Serrano
09464ff9bc esp32/[ble/wifi]: Update the wireless drivers
This commit updates the Wi-Fi and the BLE driver of ESP32. Most of
the changes rely on using the common sources and header files for
xtensa-based Espressif's SoCs.

The new Wi-Fi driver supports WPA3-SAE for both Station and SoftAP
mode. BLE's coexistence mode was enhanced according to the latest
libraries.

Please note that other sources required minor changes in order to
be compatible with the common sources.
2024-03-29 16:14:27 +08:00
Tiago Medicci Serrano
007dd34ce8 esp32s3/spiflash: Fix error to pause the other CPU during operation
Whenever a SPI flash operation will take place, it's necessary to
disable the cache and run no code from the flash. This includes
pausing the other CPU (when `CONFIG_SMP=y`). This commit prevents
an error to occur when the CPU core is evaluated before the task
is increased to the max priority.
2024-03-29 16:14:27 +08:00
Tiago Medicci Serrano
78fbc2fc64 esp32/spiflash: Fix error to pause the other CPU during operation
Whenever a SPI flash operation will take place, it's necessary to
disable the cache and run no code from the flash. This includes
pausing the other CPU (when `CONFIG_SMP=y`). This commit prevents
an error to occur when the CPU core is evaluated before the task
is increased to the max priority.
2024-03-29 16:14:27 +08:00
chenwen@espressif.com
ffc7442af2 xtensa/esp32s3: Add ESP32-S3 AES driver
1. Support AES-128/AES-256 encryption and decryption

Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-03-28 09:34:04 +08:00