This commit ensures that RTC data is properly allocated in the RTC
segment in the linker. This fixes the reported problem about using
the legacy bootloader and RTC.
There are 2 CMake compile errors during the protected build mode. One is forget to add library for nuttx_user, another is the wrong macro used when compile wqueue.
Signed-off-by: pangzhen1 <pangzhen1@xiaomi.com>
After the number of threads exceeds the array size, it will not be displayed.
Any number of threads can be displayed using dynamic adaptation
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
This PR configures the BL808 MMU to cache the the User Text, Data and Heap. We enable the T-Head MMU Flags for Shareable, Bufferable and Cacheable, as explained in the previous PR: https://github.com/apache/nuttx/pull/13199
This PR fixes the Slow Memory Access for NuttX Apps on Ox64 BL808 SBC: https://github.com/apache/nuttx/issues/12696. With this fix, Ox64 NuttX CoreMark jumps from 19 to 1,104. (Close to Buildroot Linux CoreMark)
Modified Files:
`arch/risc-v/Kconfig`: Enabled `ARCH_MMU_EXT_THEAD` for BL808 SoC.
In protected build mode, the syscall returns without setting correct value for the CONTROL register, which causes the userspace threads working in privileged mode after syscall.
Signed-off-by: pangzhen1 <pangzhen1@xiaomi.com>
* Fix nxstyle check so it does not report error on comments on the same
line as if statements
* Rework if statement checks
* Report warning instead of error for is statements check fail
This PR configures the T-Head MMU to cache the the User Text, Data and Heap. We enable the MMU Flags for Shareable, Bufferable and Cacheable, as explained in this article: https://lupyuen.github.io/articles/plic3#appendix-mmu-caching-for-t-head-c906
This PR fixes the Slow Memory Access for NuttX Apps on BL808 and SG2000 SoCs: https://github.com/apache/nuttx/issues/12696. With this fix, SG2000 NuttX CoreMark jumps from 21 to 2,423. (Close to SG2000 Debian CoreMark)
We introduce a Kconfig Option: `ARCH_MMU_EXT_THEAD` ("System Type > Enable T-Head MMU extension support"). Enabling this Kconfig Option will configure the T-Head MMU to cache the User Text, Data and Heap.
This PR enables the MMU cache for only SG2000 SoC (Milk-V Duo S SBC). The next PR will apply the same settings to BL808 SoC (Pine64 Ox64 SBC).
Modified Files:
`arch/risc-v/Kconfig`: Added Kconfig Option `ARCH_MMU_EXT_THEAD` that will configure the T-Head MMU. Enabled `ARCH_MMU_EXT_THEAD` for SG2000 SoC.
`arch/risc-v/src/common/riscv_mmu.h`: Set the T-Head MMU Flags (Shareable, Bufferable and Cacheable) for User Text, Data and Heap, if `ARCH_MMU_EXT_THEAD` is enabled
`arch/risc-v/src/common/riscv_addrenv.c`: Extended the MMU Flags from 32 bits to 64 bits, to accommodate the T-Head MMU Flags
`arch/risc-v/src/common/riscv_exception.c`: Extended the MMU Flags from 32 bits to 64 bit, to accommodate the T-Head MMU Flags. This code is enabled only for MMU Paging (`CONFIG_PAGING`).
Summary:
- I noticed that nfsmount does not work due to the recent
changes on sockaddr_storage alignment.
- This commit fixes this issue.
Impact:
- None
Testing:
- Tested with sabre-6quad:netnsh_smp (QEMU)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
purpose:
To improve the real-time performance of the system, we prefer to perform
as few operations as possible within the interrupt function.
We have designed an interrupt thread for each interrupt,
where all the operations that are not necessary to be handled
in the interrupt function are delegated to be processed by the interrupt thread.
Up_enable_irq will be invoked after isrthread started.
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
-machine virt,virtualization=on,gic-version=3 \
-net none -chardev stdio,id=con,mux=on -serial chardev:con \
-mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Currently concerns only arm.
tools/ci/testlist/msys2.dat:
At the moment I only added the board nucleo-l152re:nsh
.github/workflows/build.yml:
Enabled cmake for msys2
Prior to this commit, i2c and at24 may be used uninitialized on line
113, 117, 129, and 143 when gd32_at24_wr_test() is called the second
time because these two variables are not static. I don't think making
them static is the correct fix because i2c is released at the end of
this function. Fixed by removing the `if (!initialized)` condition
surrounding the initialization of i2c and at24, making them initialized
at every call to this function.
Signed-off-by: Mingjie Shen <shen497@purdue.edu>
"ioexpander/gpio.c", line 529: warning #186-D: pointless comparison of
unsigned integer with zero
if (pintype < GPIO_INPUT_PIN || pintype >= GPIO_NPINTYPES)
^
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
Description:
Example to interact with KEY button and user external button connected to PA1.
For KEY button pull-up resistor is active, board schematic does not show any pull-up or pull-down resistor.
Results: Example working as expected.
BlackPill PWM example
Description:
PWM example using PB0 - Timer3 - Channel 3
Create default configuration for the example.
Controlling_RGB_LED
Description: Controlling a RGB LED on NuttX for Black Pill board [STM32F411]
Note: Example currently not working as expected.
Add TUNSETCARRIER ioctl, then we may change the carrier state of TUN dynamically. Note that we don't need an ioctl for getting carrier, it can be done by SIOCGIFFLAGS already.
Ref: https://github.com/torvalds/linux/blob/v6.10/drivers/net/tun.c#L3374-L3380
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
since not all Armv7-m platform support double-precision floating
operations, so we add an extra option that help those specific platform
could define the single-precision floating operations.
for example, qemu-mps platform(armv7-m) support double-precision
floating operations, so we do not need to open
CONFIG_ARM_FPU_SINGLE_HARDWARE build options;
but for fc7300 platform(armv7-m) only support single-precision floating
operations, so if we pass "-fhard" build option to "ghs" compiler, then
the following instruction will be generated:
vcvt.f64.s32 d9, s18
which will fail to execute on fc7300 platform.
with "-fsingle" build option, the "ghs" compiler will generate hardware
instruction for single-precision floating operation, and generate
software instruction for double-precision floating operation.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
To support greenhill compilation, LDFLAGS removes the code that adds -T through addprefix to ARCHSCRIPT(greenhill requires a space between -T and ldscript files, but addprefix didn't do it). However,if we modified like this, when ARCHSCRIPT has more than one ldscript, the -T is only added to the first ldscript, but not to the following ldscripts, which results in a warning when linking.
To solve this problem, we can just add a space after $(SCRIPT_OPT) when using addprefix, instead of deleting addprefix.
Signed-off-by: pangzhen1 <pangzhen1@xiaomi.com>
