15 Commits

Author	SHA1	Message	Date
Gregory Nutt	12775801c9	Add support for delivery of use-mode signals in the kernel build.	2014-09-02 15:58:14 -06:00
Gregory Nutt	e11679acf8	Rename CONFIG_NUTTX_KERNEL to CONFIG_BUILD_PROTECTED; Partially integrate new CONFIG_BUILD_KERNEL	2014-08-29 14:47:22 -06:00
Gregory Nutt	8dd679e875	ARMv7-A: Add SYSCALL handling logic	2014-08-28 14:52:14 -06:00
Gregory Nutt	cb8e081dba	Mostly cosmetic use of uintptr_t to hold addresses instead of uint32_t	2014-08-26 10:44:10 -06:00
Gregory Nutt	699a54a022	Misc changed to get the SAMA5 ELF configuration with address environments working	2014-08-25 13:28:13 -06:00
Gregory Nutt	8907616478	Cortex-A/SAMA5 address environment support is code complete (untested)	2014-08-25 11:18:32 -06:00
Gregory Nutt	95c79c675c	Add addrenv.h; First cut at Cortex-A address environment structures; Add configuration options to setup address enviornment	2014-08-24 09:57:53 -06:00
Gregory Nutt	0a134f0158	Need to enable FIQ in initial task state; Improve H32/64 test in IRQ handling	2014-06-21 09:55:09 -06:00
Gregory Nutt	c68d2532be	SAMA5D4: Add support for secure/FIQ interrupts; SAIC supports need to be be enabled unconditionally	2014-06-20 18:16:41 -06:00
Gregory Nutt	25d4ff745b	More trailing whilespace removal	2014-04-13 16:22:22 -06:00
Gregory Nutt	8695c89aa4	SAMA5: Modification of some CPSR-related inline functions	2013-07-31 09:11:24 -06:00
Gregory Nutt	b75a0cf8be	Add ARMv7-A irqdisable() inline function	2013-07-30 11:37:09 -06:00
Gregory Nutt	cb3f394d53	Improve some ARMv7-A/M floating point register save time; Add floating point register save logic for ARMv7-A	2013-07-23 17:52:06 -06:00
Gregory Nutt	ca9b52b07f	SAMA5/Cortex-A: Improve irqsave/restore inlines + add irqenable. Add skeleton file for SAMA5 interrupt management. Also change from last commit that was left in the editor	2013-07-21 17:08:40 -06:00
Gregory Nutt	28a90ba46d	Some initial frame for Cortex-A5 support. No much yet	2013-07-18 15:20:47 -06:00