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18858 Commits

Author SHA1 Message Date
Ville Juven
75afe491ad RISC-V: Prepare for CONFIG_BUILD_KERNEL 
- Thread context prior to system call needs to be preserved
- Allocate a kernel heap
 2022-03-18 18:20:12 +08:00
Ville Juven
195705d11f MPFS: Create centralized module for PLIC address handling 
Reduce complexity and copy-paste amount by implementing a module
to handle calculating PLIC offsets.
 2022-03-18 18:20:12 +08:00
Ville Juven
745f00e77d MPFS: Use riscv_mhartid to obtain hartid 
Preparation for S-mode, read mhartid via function call instead of
directly from the machine mode register
 2022-03-18 18:20:12 +08:00
Ville Juven
f8ffcbbf36 MPFS: Remove definition and reference to MPFS_PLIC_CTRL 
The register does not exist. c906 implementation has it, but MPFS does not.
 2022-03-18 18:20:12 +08:00
Ville Juven
0f91eab626 MPFS: Protected mode, fix MMU mapping 
The mapped vaddr was wrong, don't want to map the page tables, but
the user space area (start of .text) instead.
 2022-03-18 18:20:12 +08:00
Ville Juven
9269a86d00 RISC-V: Add common data memory and instruction barriers 2022-03-18 18:20:12 +08:00
chao.an
19119a9c43 arch/arm: set the SP to stack top 
fix the stack imbalance

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-18 07:56:51 +09:00
Abdelatif Guettouche
5085f854d0 esp32(s3)_start.c: In SMP mode, don't disable APP CPU at startup. It starts in a 
disabled state and if OpenOCD is used this will clear OpenOCD configuration.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-17 14:33:32 -03:00
Abdelatif Guettouche
b98676f8be esp32(s3)_cpustart.c: Don't reset app CPU if it was already configured by 
OpenOCD.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-17 14:33:32 -03:00
Abdelatif Guettouche
b10c8955cf arch/Kconfig: Don't depend on Xtensa for the SUPPRESS_CLOCK_CONFIG 
option.  This config was probably added in the early bring up of the
ESP32 chip. At that point the clock config was suppressed and we relied
on the bootloader.  Now we can configure the clock from NuttX.

The option itself is still useful and can be used for any other
architecture or chip.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-17 14:33:12 -03:00
Xiang Xiao
c2a1d0f5ae procfs: Remove mallinfo from struct procfs_meminfo_entry_s 
let's call mm_mallinfo directly

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-17 13:59:03 -03:00
Gustavo Henrique Nihei
baa09aa999 risc-v/esp32c3: Remove deprecated option for disabling atomics support 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-17 23:40:29 +08:00
Huang Qi
807304f283 arch/risc-v: Rework riscv_get_newintctx 
Some fields of mstatus were marked as Reserved Writes Preserve Values, Reads Ignore Values (WPRI),
so we must keep its origin value with addition flags.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-17 15:43:30 +08:00
Petro Karashchenko
c3bae60c57 drivers/can: optimize can driver reader side 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-17 15:43:15 +08:00
Gustavo Henrique Nihei
39e9a17e60 xtensa/esp32s3: Apply style fixes throughout serial driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-16 19:06:39 -03:00
Gustavo Henrique Nihei
0dc2930403 xtensa/esp32s3: Remove code for not yet supported USB-Serial Driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-16 19:06:39 -03:00
Gustavo Henrique Nihei
57273ad994 xtensa/esp32s3: Fix IRQ setup hardcoded to CPU 0 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-16 19:06:39 -03:00
Huang Qi
9cc0a609bd arch/risc-v: Correct stack coloration in riscv_cpu_boot 
In smp system riscv_cpu_boot run in idle task so there is a overlap with the origin coloration range and in used stack.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-16 14:12:45 +02:00
SPRESENSE
c05ace557f arch: cxd56xx: Fix critical section in serial transmission 
Fix an issue that the serial transmission buffers are corrupted because
serial transmission are not protected by critical section in non-smp mode.
 2022-03-16 20:23:41 +09:00
Petro Karashchenko
985829190e arch/arm/samv7/sam_tc: implement timer driver support 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-16 03:19:57 +08:00
Eero Nurkkala
c38d547900 risc-v/mpfs: usb: fix ep0 stall/resume and rx reads 
Fix EP0 stall and resume properly. EP0 wasn't clearly addressed
on stall / resume operations.

Also fix data reads that provide garbage for the first request.
It has always random data as it's completed prior to any read
operation.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2022-03-16 00:59:25 +08:00
Ville Juven
e843c441de RISC-V: Fix nasty bug in PMP region test 
The end address was not handled correctly, it is not a part of a mapped
region.
 2022-03-15 18:59:20 +02:00
Matthew Trescott
8c471db932 Corrections to Tiva KConfig 2022-03-15 11:32:31 -04:00
Matthew Trescott
bc80bbddc7 Add Tiva CAN driver 2022-03-15 11:32:31 -04:00
chao.an
81130bc692 arch/arm: remove unused arm_copyfullstate/arm_copyarmstate 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-15 23:03:51 +09:00
chao.an
7b9978883c arch/arm: optimize context switch speed 
The current context save implementation saves registers of each task
to xcp context, which is unnecessary because most of the arm registers are
already saved in the task stack, this commit replace the xcp context with
stack context to improve context switching performance and reduce the tcb
space occupation of tcb instance.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-15 23:03:51 +09:00
Petro Karashchenko
b04447d066 timer_lowerhalf: minor improvements 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-15 10:30:48 +08:00
Xiang Xiao
b6bc460b2c arch: Make the comment and definition of CONFIG_SYS_RESERVED correctly 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-14 22:51:00 +02:00
chao.an
ea42981cc6 syscall/names: export the syscall name in STUB module 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 21:37:53 +02:00
chao.an
d398ffb930 arm/armv7-a/r: unified syscall registers dump 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 21:37:53 +02:00
chao.an
22e71e2d71 board/sim: add support of custom optimization level 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 23:25:26 +08:00
Abdelatif Guettouche
d21d02c65d xtensa_panic.S: Save exception cause and vaddr into the user frame. 
This area is what's passed later to assert and be used to dump the
state.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 19:54:30 +08:00
Abdelatif Guettouche
a9e3b5ae37 xtensa_panic.S: A2 is already saved by the caller, no need to save it 
here again.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 19:54:30 +08:00
chao.an
7c02432f0e arm/armv7-a/r: set the default CPU mode to System 
In SVC mode, the banked register will be inconsistent with the user mode register:

arch/arm/src/armv7-a/arm_vectors.S

 276   .globl  arm_syscall
 277   .globl  arm_vectorsvc
 278   .type arm_vectorsvc, %function
 279
 280 arm_vectorsvc:
...
 286   sub   sp, sp, #XCPTCONTEXT_SIZE        // < SVC mode SP
...
 308   stmia   r0, {r13, r14}^                // < USR mode SP/LR
...

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 4
[    2.200000] [ 4] [ ALERT]   R0: 00000004 80001229 00000001 80202018 00000000 00000000 00000000 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 802027d0 1080f710 1080f710
[    2.200000] [ 4] [ ALERT] CPSR: 00000073
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 1 80202018 1 80202018 0 0 0 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 802027d0 1080f710 80001229
[    2.200000] [ 4] [ ALERT] CPSR: 00000070

SVC SP is 0x80202708
USR SP is 0x802027d0
0x802027d0 - 0x80202708 should be XCPTCONTEXT_SIZE

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 51
[    2.200000] [ 4] [ ALERT]   R0: 00000033 00000000 80202780 00000000 00000000 00000000 00000000 80202710
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 80202710 800039d5 800039b2
[    2.200000] [ 4] [ ALERT] CPSR: 00000070
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 2b 0 80202780 0 0 0 0 80202710
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 10843d80 800039d5 10801425
[    2.200000] [ 4] [ ALERT] CPSR: 00000073

SVC SP is 0x80202708
USR SP is 0x80202710
SP overlap in SVC and USR mode

This commit change the default CPU mode to System and ensure the consistency of SP/LR in USR/SYS mode during syscall.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 19:54:53 +09:00
Xiang Xiao
54e630e14d arch: Merge up_arch.h into up_internal.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-14 09:32:17 +02:00
Xiang Xiao
e800f54bfd arch/mpfs: Don't include nuttx header file in mpfs_opensbi.c 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-14 09:32:17 +02:00
Abdelatif Guettouche
cff3d9df7b arch/xtensa: Fix some indentations. 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
6fa4a42e34 xtensa/: Save A3 as part of the regular context saving. 
It was separate because the syscal handler was using it before calling
_xtensa_context_save.  The order of operations has now changed and we
can save A3 with the rest of the context.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
4d1bb20f8c xtensa_user_handler.S: In syscall handler store context before 
continuing the rest of the syscall handling.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
5305f76b1d xtensa_context.S: Use Zephyr's version of spilling the window register 
file.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
2445de173d xtensa_dumpstate.c: Don't dump temporary registers. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
4786963ee2 xtensa_context.S: No need to save A2 before calling 
_xtensa_save_context.  It uses CALL0, in this case A1 is callee saved
and we can it directly.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
2dcbf28f15 xtensa_context.S: A1 should be restored by the caller not 
xtensa_context_resotred. Here it was being restored twice.
Remove the one in xtensa_context_restore.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
5bd2e97a27 xtensa_context.S: Fix the type of _xtensa_context_restore. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
e9018b29bf xtensa_context.S: Remove the CALL0 ABI version of xtensa_context_switch 
as it's the same as the Window ABI now.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Xiang Xiao
c96c96a399 drivers: Merge the common driver initialization into one place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-13 11:24:48 -03:00
Xiang Xiao
ea614090cd arch/risc-v: Change hex number to low case in csr.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-13 10:17:25 +02:00
Xiang Xiao
f94093bc2e arch/ceva: Move the idle stack initialization to up_initial_state 
to follow other arch's implementation

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-13 00:28:05 +02:00
Xiang Xiao
1a7f49eeb3 arch/z[80|16]: Move up_getsp declaration to arch.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 19:21:59 +02:00
Gustavo Henrique Nihei
7ede285cfe xtensa/esp32s3: Add support for RT-Timer based on Systimer peripheral 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-12 15:27:30 +02:00