Commit Graph

20644 Commits

Author SHA1 Message Date
Ville Juven
20623d7369 sem/sem_init: Change sem_xxx -> nxsem_xxx in kernel modules
Use the kernel space api nxsem_xxx when inside the kernel.
2023-04-25 13:41:51 +02:00
zhangyuan21
6605f95133 l2cc: Do not repeat disabling the cache when the cache is already disabled
When l2cc is already in disable state, performing a disable operation
again will flush incorrect cache data to memory

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-25 15:36:10 +08:00
zhangyuan21
69fd539886 arch/armv7ar: use robust code sequences for cache maintenance
Invalidate operations at DDI0246H_l2c310_r3p3_trm:
If there is a stale entry in the L2 cache, the system enables the invalidation of
the L1 cache. But before the controller invalidates the L2 cache, it allocates a
line from the L2 cache to an L1 cache.

The robust code sequence for invalidation with a non-exclusive cache arrangement is:
1. InvalLevel2 Address ; forces the address out past level 2
2. CACHE SYNC ; Ensures completion of the L2 inval
3. InvalLevel1 Address ; This is broadcast within the cluster
4. DSB ; Ensure completion of the inval as far as Level 2.

This sequence ensures that, if there is an allocation to L1 after the L1 invalidation, the data
picked up is the new data and not stale data from the L2

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-25 15:35:37 +08:00
Masayuki Ishikawa
fb6bef2c2d arch: imx6: Add support for AR8031 gigabit ethernet phy
Summary:
- This commit adds AR8031 gigabit ethernet phy for the
  sabre-6quad board.

Impact:
- None

Testing:
- Tested with sabre-6quad:netnsh_ar8031 (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-04-25 11:45:19 +08:00
Masayuki Ishikawa
dc914f43ea arch: imx6: Fix CONFIG_IMX_ENET_ENHANCEDBD related code
Summary:
- This commit applies the changes from imxrt
- See 3a4542f3c4

Impact:
- imx6 ethernet with d-cache

Testing:
- Tested with imx6_with_ar8031 (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-04-25 11:45:19 +08:00
Petro Karashchenko
3e3670af77 arch/xtensa/esp32: fix wrong enabled BLE interrupts
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-04-24 09:35:58 -07:00
Petro Karashchenko
0c28094059 arch/xtensa/esp32: fix crash in BLE startup
ROM symbols provided by linker are placeholders for addresses
and not a pure addresses, so we need to read data pointed by
ROM symbols instead of using those as pure addresses.

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-04-24 09:35:58 -07:00
Petro Karashchenko
d50ec662be arch/risc-v/esp32c3: Change the linker generated symbols from uint32_t to uint8_t *
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-04-24 09:35:58 -07:00
chao an
b8780fe906 arch/arm: relax compiler check for workaround with "GCC 12.2"
1. relax compiler check for workaround with "GCC 12.2"
2. export GCCVER to environment

Signed-off-by: chao an <anchao@xiaomi.com>
2023-04-24 19:00:52 +03:00
zhangyuan21
d7de93f906 arch/arm: Resolving warnings for assembly instructions
arm/arm_saveusercontext.S:61: Warning: duplicated register (r14) in register list

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-24 23:49:33 +08:00
Xiang Xiao
51dc67ad5f fs: Add g_ prefix for all global file_operations instances
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-04-24 16:13:29 +02:00
Huang Qi
3d3a86ae53 arch/sim: Move up_textheap_xxx to common place
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-04-24 19:37:15 +08:00
Huang Qi
97f8817d6b arch/sim: Implement host_freeheap for windows
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-04-24 19:37:15 +08:00
Huang Qi
70395f49b2 arch/sim: Implement text heap
If CONFIG_MM_CUSTOMIZE_MANAGER enabled on sim, malloc/mmap is bypassed to glibc, so the memory allocated without execution permisson.

For this case, CONFIG_ARCH_USE_TEXT_HEAP can be used.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-04-24 10:29:20 +08:00
YAMAMOTO Takashi
0066bf80d2 esp32: enable LIBC_ARCH_ATOMIC
fixes a build issue in https://github.com/apache/nuttx-apps/pull/1723
2023-04-24 10:12:57 +08:00
hujun5
6063c0516e cpu: in SMP pthread_cancel occasionally deadlock
In smp when cpu0 calls up_cpu_resume to release the cpu1 lock, another locked cpu1 did not execute immediately,
and soon cpu0 called up_cpu_resume again, now cpu1 unable to respond to the interrupt at this time, resulting in a deadlock.
Our solution is to restore cpu1 execution from asynchronous to synchronous to ensure that cpu1 is restored.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-04-23 23:33:09 +08:00
zhanghongyu
50488ac8f3 sim: multi netdevice forward issue when ll_guardsize not 14
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2023-04-23 10:37:50 +03:00
zhanghongyu
37644c8818 Revert "sim: multi netdevice forward issue when ll_guardsize not 14"
This reverts commit a69c6c1dac.
2023-04-23 10:37:50 +03:00
raiden00pl
d416ead27c arch/nrf52: reimplement I-Cache control operations in nrf52_start.c 2023-04-22 01:42:01 +08:00
raiden00pl
c70c178a7d arch/nrf52: nvmc and flash should depends on ALLOW_BSD_COMPONENTS=y 2023-04-22 01:42:01 +08:00
zhanghongyu
a69c6c1dac sim: multi netdevice forward issue when ll_guardsize not 14
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2023-04-22 01:41:01 +08:00
Zhe Weng
f21742899f net/netdev: Use upper half of netdev to simplify sim driver
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
2023-04-22 01:41:01 +08:00
Stuart Ianna
4cae98674d litex: Support for kernel build with vexriscv-smp. 2023-04-22 01:40:32 +08:00
qinwei1
c4f3f8801f arm64: Support for FPU profiling with procfs
Summary:

   To reduce the count of FPU context switching will result at a
performance improve with system. it need to balance between
the using of FPU and counts of FPU trap
   the PR submit a base method to see performance counts for
the FPU with NuttX procfs
   Please read README.txt at chapter of FPU Support and Performance
for more information

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-04-22 01:38:21 +08:00
raiden00pl
bd9bfa9302 arch/nrf53: add RPMSG HCI controller support 2023-04-22 01:37:24 +08:00
Fotis Panagiotopoulos
873abcb9ab stm32_eth: Added error handling for abnormal interrupts. 2023-04-22 01:30:48 +08:00
Lucas Saavedra Vaz
bdfe31e850 boards/xtensa/esp32: Add ESP32-PICO-KIT support 2023-04-22 01:23:13 +08:00
zhangyuan21
dfcba925e7 arch/arm64: add cache enable and disable function
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:22:04 +08:00
zhangyuan21
652fc7648e arch/arm64: Fixed error in getting cache size when there was no mmu
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:22:04 +08:00
raiden00pl
cc7826df4d arch/nrf52: add QSPI support 2023-04-22 01:12:27 +08:00
zhangyuan21
41f83a0271 arch/arm64: change up_saveusercontext to assembly code
minidump will backtrace failure when use C code to save user context,
because the stack push operation in C code can disrupt the stack information.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:11:00 +08:00
zhangyuan21
1e726a914a arch/arm: change up_saveusercontext to assembly code
minidump will backtrace failure when use C code to save user context,
because the stack push operation in C code can disrupt the stack information.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:11:00 +08:00
hujun5
ab0b3336c4 arch/arm64:Suppot tickless mode
1 Similar to Linux and zephyr, all implementations are in arm64_arch_timer.c

2 Arm64 tickless is turned off by default. If it needs to be turned on, you need to configure the switch CONFIG_SCHED_TICKLESS ON

3 The implementation strategy for tick/tickless is to use the timer inside the CPU and implement the timer driver based on the ARCH_TIMER framework.

4 We implemented tick_* Callback functions to adapt to the driven interface to avoid time format conversion overhead

5 In arm64_tick_cancel func,The remaining time that is not used, so this value can be ignored without reading the corresponding register to obtain the remaining cycles

6 Currently, tick/tickless can takes effect in SMP and non SMP mode, ostest can pass.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-04-22 01:08:04 +08:00
David Sidrane
ac6ad45045 stm32l5:pinmap Add suffix to all pins and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings and
   all pins should have had suffixes to allow any pins attributes to
   be set. This is board dependent.

   This change adds CONFIG_STM32L5_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps with suffixes.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, CONFIG_STM32L5_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set CONFIG_STM32L5_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
7e48b58993 stm32wb:pinmap Add suffix to all pins and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings and
   all pins should have had suffixes to allow any pins attributes to
   be set. This is board dependent.

   This change adds CONFIG_STM32WB_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps with suffixes.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, CONFIG_STM32WB_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set CONFIG_STM32WB_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
a8093281c4 stm32f0l0g0:stm32f0{3|5|7|9}x_pinmap & stm32g0_pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
   This is board dependent.

   This change adds CONFIG_STM32F0G0L0_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps without speeds.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, CONFIG_STM32F0G0L0_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set CONFIG_STM32F0G0L0_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
77cf6ce273 stm32l4:stm32l4x{3|4|5|6|r}xx_pinmap pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
   This is board dependent.

   This change adds CONFIG_STM32L4_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps without speeds.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, CONFIG_STM32L4_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set CONFIG_STM32L4_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
1ece250b18 stm32:stm32f10{0|2|3{c|r|v|z}|5{r|v}|7v}_pinmap refactor
replace all GPIO_MODE_xxMHz with GPIO_MODE_2MHz provide GPIO_ADJUST_MODE
    and add legacy pinmap

    For the stm32F1 pinmaps should not have contained GPIO_MODE_50MHz settings
    on all pins. Speed is board dependent.

    This change adds CONFIG_STM32_USE_LEGACY_PINMAP to allow for
    lazy migration to using pinmaps that can have the GPIO_MODE_xxMHz set.

    The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
    The tools will take a board.h, and use all the defconfigs with the legacy
    pinmap and output the required changes that one needs to make to a board.h
    file.

    Eventually, CONFIG_STM32_USE_LEGACY_PINMAP will be deprecated and the legacy
    pinmaps removed from NuttX.

    Any new boards added should set CONFIG_STM32_USE_LEGACY_PINMAP=n and
    fully define the pins in board.hf1
2023-04-19 09:58:11 +02:00
David Sidrane
ee6fb7880b stm32:stm32l15xxx pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
   This is board dependent.

   This change adds CONFIG_STM32_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps without speeds.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, STM32_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set STM32_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
5d025d5d50 stm32:stm32g4xx{c|k|r|m|v|q} pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
   This is board dependent.

   This change adds CONFIG_STM32_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps without speeds.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, STM32_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set STM32_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
98cd82f905 stm32:stm32f3{0|3|7}xxx pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
   This is board dependent.

   This change adds CONFIG_STM32_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps without speeds.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, STM32_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set STM32_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
35258a26c0 stm32:stm32f20xxx pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
   This is board dependent.

   This change adds CONFIG_STM32_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps without speeds.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, STM32_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set STM32_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
39c5931462 stm32:f4/f412 pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
   This is board dependent.

   This change adds CONFIG_STM32_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps without speeds.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, STM32_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set STM32_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
1ce84fff01 stm32f7:pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
   This is board dependent.

   This change adds CONFIG_STM32F7_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps without speeds.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, STM32F7_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set STM32F7_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
14a0e08386 stm32h7:pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
  This is board dependent.

  This change adds CONFIG_STM32H7_USE_LEGACY_PINMAP to allow for
  lazy migration to using pinmaps without speeds.

  The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
  The tools will take a board.h file and a legacy pinmap and outut the required
  changes that one needs to make to a board.h file.

  Eventually, STM32H7_USE_LEGACY_PINMAP will be deprecated and the legacy
  pinmaps removed from NuttX.

  Any new boards added should set STM32H7_USE_LEGACY_PINMAP=n and
  fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
c5f7620c42 stm32u5:stm32u585xx_pinmap Fix typo 2023-04-19 09:58:11 +02:00
David Sidrane
7e171da63f stm32wl5:pinmap Fix typo 2023-04-19 09:58:11 +02:00
zhangyuan21
c00498c164 arch/arm: update running task when context switch occurred
The text describes an issue related to the running task in code.
The running task is only used when calling the _assert function
to indicate the task that was running before an exception occurred.
However, the current code only updates the running task during
irq_dispatch, which is suitable for ARM-M architecture but not
for ARM-A or ARM-R architecture, because their context switches
are not done through irq handler. Therefore, if the following
process is followed, the value of the running task will be incorrect:

1. task1 is running, this_task()=task1
2. do_irq is executed, setting running task()=task1
3. task1 switches to task2
4. task2 is running and generates a data abort
5. In the data abort, the _assert function is called,
   and the running task obtained is still task1, but
   the actual task that generated the exception is task2.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 10:14:05 +09:00
chao an
899be58905 sim/win/hostfs: set O_BINARY for windows hostfs as default
Since the initial default setting in MSVC is text mode ( O_TEXT ):

https://learn.microsoft.com/en-us/cpp/c-runtime-library/text-and-binary-mode-file-i-o?view=msvc-170

In order to unify the translation behavior with unix,
1. set O_BINARY for hostfs as default
2. enable default text mode if the application specifies flag O_TEXT

Signed-off-by: chao an <anchao@xiaomi.com>
2023-04-19 02:55:15 +08:00
zhangyuan21
f5f0af4f9c arch/arm64: fixed backtrace skip calc error
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 02:53:02 +08:00
zhangyuan21
2c599bb9e6 arch/arm64: call PANIC in arm64_fatal_error
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 02:53:02 +08:00
zhangyuan21
e4ae2b48b8 arch/arm64: Obtaining the correct fp pointer
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 02:53:02 +08:00
chao an
49c863f238 sim/win/hostuart: only read key event from console
This commit will detect input events and filter out events(mouse/window/etc) other than key

Signed-off-by: chao an <anchao@xiaomi.com>
2023-04-19 02:52:16 +08:00
Dong Heng
45bba6e761 xtensa/esp32: ESP32 not use IMEM in user heap mode 2023-04-18 11:03:55 -03:00
yinshengkai
b705d9b1d5 sim: switch working directory
If this option is enabled, the working path of nuttx will be modified to the folder where the nuttx file is located.

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2023-04-17 16:48:52 +08:00
raiden00pl
642358e68f stm32h7/rcc: make VOS0 configurable from board.h also for stm32h7x7xx
Over-drive can be forced to a given state by adding define to the
board.h configuration file:

   #define STM32_VOS_OVERDRIVE 1 - force over-drive enabled,
   #define STM32_VOS_OVERDRIVE 0 - force over-drive disabled,
   #undef STM32_VOS_OVERDRIVE    - autoselect over-drive by the default RCC logic
2023-04-17 04:23:40 -04:00
raiden00pl
876b7a5e8e stm32h7/rcc: make VOS0 configurable from board.h
It seems that over-drive is not required for ULPI but it can be a workaround solution for boards with poor signal integration.
Higher core voltage means faster clock signal edges, which may be sufficient to synchronize the high-speed clock and data on poorly designed boards.

Over-drive can be forced to a given state by adding define to the
board.h configuration file:

   #define STM32_VOS_OVERDRIVE 1 - force over-drive enabled,
   #define STM32_VOS_OVERDRIVE 0 - force over-drive disabled,
   #undef STM32_VOS_OVERDRIVE    - autoselect over-drive by the default RCC logic
2023-04-17 04:23:40 -04:00
Ville Juven
b982c1747b sched/addrenv: Miscellaneous clean-up and fixes
- Remove the temporary "saved" variable when temporarily changing MMU
  mappings to access another process's memory. The fact that it has an
  address environment is enough to make the choice
- Restore nxflat_addrenv_restore-macro. It was accidentally lost when
  the address environment handling was re-factored.
2023-04-15 13:21:48 +09:00
Tiago Medicci Serrano
869aee6a78 xtensa/sigdeliver: fix signal deliver when task is running
The Inter-Processor Interrupt that pauses the other CPU generates
a level-1 interrupt which sets the PS.EXCM. This level-1 interrupt
is treated as an Exception and the bit PS.EXCM bit is automatically
reset on return from Exception. However, this is not the case here
because we are changing the execution to the signal trampoline.
Restoring the PS register with the PS.EXCM bit set would cause any
other exception to deviate execution to the DEC (double exception
vector), avoiding it to be treated correctly. According to the
xtensa ISA: "The process of taking an interrupt does not clear
the interrupt request. The process does set PS.EXCM to 1, which
disables level-1 interrupts in the interrupt handler. Typically,
the PS.EXCM is reset to 0 by the handler, after it has set up the
stack frame and masked the interrupt." Clean the saved PS.EXCM to
1) avoid an exception from being properly treated and 2) avoid
interrupts to be masked while delivering the signal.
2023-04-15 08:19:30 +09:00
chenwen@espressif.com
8df0a4d9ef xtensa/esp32: Add support for universal mac addresses
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2023-04-13 09:43:30 -03:00
chao an
3f05df3fbb sim/win/hosttime: calculate sec/ms independently to avoid overflow
In the previous implementation, PerformanceCounter would cause overflow
after running for a long time, This commit will separate the calculation
of the sec/ms part to avoid this issue, Reference:

https://github.com/cygwin/cygwin/blob/main/winsup/cygwin/clock.cc#L194-L217

Signed-off-by: chao an <anchao@xiaomi.com>
2023-04-12 08:38:34 +02:00
zhangyuan21
024b13f3ed arch/arm: enable eoimode only select CONFIG_XXX_GIC_EOIMODE
On a GICv2 implementation, setting GICC_CTLR.EOImode to 1 separates
the priority drop and interrupt deactivation operations.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-11 08:54:45 +02:00
zhangyuan21
c239d19df0 nuttx: add more dependent header file
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-11 09:13:32 +03:00
wangming9
a7fc26124d arch/arm64: the arm64 perf interface supports pmu
Summary:
- Support arm64 pmu api, Currently only the cycle counter function is supported.
- Using ARM64 PMU hardware capability to implement perf interface, modify all
  perf interface related code.
- Support for pmu init under smp.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-04-10 16:23:49 -03:00
wangming9
75760a9fdb arch/arm64: Adds custom chip option
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-04-10 16:23:49 -03:00
raiden00pl
5e5fcd8076 fix copy-paste errors for d356ad633f 2023-04-10 03:21:36 -07:00
Petro Karashchenko
665a8e5b93 arch/arm/samv7: fix operation of TC8 and TC11
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-04-07 12:28:45 -03:00
Petro Karashchenko
4f3faded71 arch/arm/samv7: fix comment in freerun timer
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-04-07 12:28:45 -03:00
Gustavo Henrique Nihei
8e83379b84 risc-v/espressif: Initialize HR Timer where it is required
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-07 12:27:56 -03:00
Gustavo Henrique Nihei
ebe4ab8894 risc-v/espressif: Add support for RTC subsystem
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-07 12:27:56 -03:00
Tiago Medicci Serrano
b6e92fa16d esp32s3/wifi: call softAP callback when Wi-Fi driver TX is done
In one of the previous code revision, the '#ifdef' for calling the
softAP callback was thrown away.
2023-04-06 20:58:58 +03:00
Dong Heng
a51e102a41 xtensa/esp32: Make asprintf and lib_free corresponding 2023-04-06 20:57:19 +03:00
Tiago Medicci Serrano
00c3463426 arch/xtensa: Remove FAR qualifier for Xtensa-specific files
This PR intends to remove all references to the FAR qualifier from
Xtensa files. FAR is defined as nothing on both architectures.
2023-04-06 14:36:26 -03:00
Gustavo Henrique Nihei
38861f6154 risc-v/espressif: Use spinlock APIs for defining critical sections
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-06 14:35:36 -03:00
raiden00pl
d356ad633f {stm32,stm32f7,stm32h7,stm32l4,efm32}/otg: rasie an assertion if IN request is not possible to transfer
Otherwise, a request will never be transferred and there is no
information to the user that something is wrong.
For example, when using default values for TXFIFO in HS mode,
USBMSC will never work because the maximum request len is 512B
which is lower than the default TXFIFO size for IN EP.
2023-04-06 19:30:53 +03:00
Gustavo Henrique Nihei
ac746fd87f risc-v/espressif: Add support for Tickless mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-06 19:29:23 +03:00
raiden00pl
62ff3f484e {stm32f7,stm32h7,stm32l4}/sdmmc: callback support requires HPWORK 2023-04-06 18:10:59 +03:00
pengyiqiang
961b86642a sim_x11eventloop: fix X11 event accumulation
sim_x11events should process all x11 events in each event loop,
otherwise it will cause events to accumulate in the queue and affect the interaction.

Signed-off-by: pengyiqiang <pengyiqiang@xiaomi.com>
2023-04-06 10:24:17 -03:00
Masayuki Ishikawa
5e7d48f4b0 arch: k210: Fix k210 timer on QEMU 6.1 or later
Summary:
- I noticed that 'sleep 1' on nsh took 10 seconds on QEMU-6.1,
  though the old version (e.g. QEMU-5.2) works correctly.
- I think we should implement PLL for the QEMU environment.
  However, this fix works as a tentative solution.

Impact:
- K210 on QEMU only

Tested
- Tested with QEMU-7.1

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-04-06 00:54:08 -07:00
Gustavo Henrique Nihei
8be8aab9bb risc-v/espressif: Panic if CPU interrupt allocation fails
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-05 16:52:07 -03:00
Gustavo Henrique Nihei
7aecd751f0 risc-v/espressif: Add support for Oneshot Timer
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-05 16:51:34 -03:00
Gustavo Henrique Nihei
31d68f2dd3 risc-v/espressif: Add support for Periodic Timers
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-05 16:51:34 -03:00
raiden00pl
1ace09cf10 stm32h7/otgdev: FS transceiver must be enabled if OTGFS enabled 2023-04-05 13:34:09 -03:00
Tiago Medicci Serrano
89b966a4f5 esp32/wifi: notify networking layer about the carrier status 2023-04-05 10:26:27 -03:00
Tiago Medicci Serrano
eb01b66978 esp32/wifi: fix typos, goto and macro definitions 2023-04-05 10:26:27 -03:00
Tiago Medicci Serrano
49d43a35b9 esp32/wifi: set Wi-Fi driver parameters only when needed
This commit fixes #7857 and #7193 by saving Wi-Fi parameters and
set them at once, avoiding unknown behaviors of the Wi-Fi driver.

This commit also enables setting the auth of the STA/softAP modes
while connecting to/providing the wireless network.
2023-04-05 10:26:27 -03:00
raiden00pl
83cdaeb593 stm32h7/otg: add support for external ULPI 2023-04-04 09:25:00 -07:00
raiden00pl
f89d2be99f stm32h7/rcc: OTGHS ULPI works only in VOS0
This is not documented by ST at all but otherwise ULPI is dead.
2023-04-04 09:25:00 -07:00
raiden00pl
d76b7c20ad stm32h7: update ULPI pins 2023-04-04 09:25:00 -07:00
yinshengkai
cafd3af160 arch/boards: fix stm32f411-mininum:nsh compilation failure after enabling IRQMONITOR 2023-04-03 09:05:21 +02:00
raiden00pl
71d7028c4a stm32h7/stm32_sdmmc.c: fix compilation 2023-04-02 17:20:17 -04:00
Huang Qi
7f27129896 tools: Move Rust relative settings to Rust.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-04-01 16:45:11 +03:00
Gustavo Henrique Nihei
ffef83c9a1 risc-v/espressif: Add High Resolution Timer driver
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-01 10:40:04 -03:00
GD32-MCU
6a799fef6c add littlefs support for gd32f450zk-eval board 2023-04-01 10:38:16 -03:00
Huang Qi
5d4e4b1919 tools/riscv: Map extensions to certain cpu model for LLVM based toolchain
RISCV has a modular instruction set. It's hard to define cpu-model to support all toolchain.
For Zig, cpu model is this formal: generic_rv[32|64][i][m][a][f][d][c]
For Rust, cpu model is this formal: riscv[32|64][i][m][a][f][d][c]
So, it's better to map the NuttX config to LLVM builtin cpu model, these models supported by
all LLVM based toolchain.
Refer to : https://github.com/llvm/llvm-project/blob/release/15.x/llvm/lib/Target/RISCV/RISCV.td
These models can't cover all implementation of RISCV, but it's enough for most cases.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-03-31 16:55:15 -03:00
Gustavo Henrique Nihei
5081cef2c9 risc-v/espressif: Add Hardware RNG support
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-31 22:01:39 +03:00
Gustavo Henrique Nihei
cf90fa62b2 risc-v/espressif: Add support for System Reset
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-31 22:00:17 +03:00
Gustavo Henrique Nihei
c1efa8c85a risc-v/espressif: Fix include path for brownout.h
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-31 22:00:17 +03:00
raiden00pl
9bd865301c nrf52: add usb support 2023-03-30 09:28:55 -03:00
Ville Juven
fc44cbdbdb arch/risc-v: Set Supervisor User Memory (access) for idle process too
This has been a long issue for me as it results in random crashes when
asynchronous events occur when the idle process is active.

The problem is that the kernel cannot access user memory, because the CPU
status prevents it.
2023-03-29 10:53:09 -03:00
Stuart Ianna
01b0305ab5 risc-v: SV32 MMU support for qemu-rv. 2023-03-29 22:15:19 +09:00
Huang Qi
536739d2da tools: Export LLVM style arch info for non-c language
Current Toolchain.defs set the compile flags directly, it's OK for
target specified gcc toolchain.

But some LLVM based toolchains (Rust/Zig etc) use single toolchain to handle all supported paltform.

In this patch, arch level Toolchain.defs export standard LLVM style arch flags, and let <Lang>.defs to map them into internal style,

This will simplify the intergration of non-c language.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-03-29 09:26:38 -03:00
raiden00pl
d23759d457 arch/nrf53: add tickless support 2023-03-28 19:43:35 -03:00
raiden00pl
f9f41bbd95 arch/nrf53: add RTC support 2023-03-28 19:43:35 -03:00
raiden00pl
bcecf2023f arch/nrf53: add GPIOTE support 2023-03-28 19:43:19 -03:00
raiden00pl
74b0e8c2c8 arch/nrf53: rename nrf53_gpioe.h to nrf53_gpiote.h 2023-03-28 19:43:19 -03:00
Gustavo Henrique Nihei
f462be5365 risc-v/espressif: Fix NULL-dereferencing in WDT interrupt handling
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-28 22:39:00 +03:00
Alan Carvalho de Assis
c5145257fe esp32: Add Ai-Thinker ESP32-A1S module 2023-03-28 20:58:36 +03:00
Gustavo Henrique Nihei
6647f194db risc-v/espressif: Update revision of esp-hal-3rdparty
Small cleanup, no added features.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-28 14:43:40 -03:00
Xiang Xiao
bc3e6c84e1 arch: Rename up_[early]serialinit to [arm64|riscv|x86_64][early]serialinit
The naming standard at:
https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+Architecture%2C+MCU%2C+and+Board+Interfaces
requires that all MCU-private function begin with the name of the architecture, not up_.

follow the change from: https://github.com/apache/nuttx/pull/930

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-03-27 12:35:04 +03:00
Petro Karashchenko
6c6a54b0c9 ld: fix warning reported by GCC 12 linker
warning: nuttx has a LOAD segment with RWX permissions

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-03-27 12:38:28 +08:00
chao an
0eae218b49 arm/chip/sdio/muxbus: comment all undefined symbols
comment all undefined symbols to avoid build break if CONFIG_SDIO_MUXBUS enabled

Signed-off-by: chao an <anchao@xiaomi.com>
2023-03-26 13:04:48 -03:00
Lwazi Dube
21ffb4de72 boards/sama5d3-xplained: Make hot plugging more reliable. 2023-03-26 13:03:21 -03:00
Lucas Saavedra Vaz
6227cd4fd4 boards/xtensa/esp32s2-kaluga-1: Add touch pad support 2023-03-26 12:59:37 -03:00
raiden00pl
2ddc96ff66 arch/stm32/stm32.h: do not include stm32_usbdev.h if not supported 2023-03-25 23:41:32 -07:00
raiden00pl
68f6fb2edd {stm32,stm32l4,stm32f0l0g0}/otg: move STM32_NENDPOINTS definitions to header files
This value is useful for users when initializing a USB composite device in a board-specific logic
2023-03-25 23:41:32 -07:00
raiden00pl
2c97c76577 nrf53_clockconfig.c: add comment about oscillator configuration 2023-03-25 22:24:36 +02:00
raiden00pl
1d4d008564 nrf53: UART1 available only on the app core 2023-03-25 22:24:36 +02:00
raiden00pl
bca927e203 nrf52/nrf53/sdc: define BLE max connection if NET_BLUETOOTH=n 2023-03-25 22:24:36 +02:00
raiden00pl
620c6cfd58 nrf52/nrf53: lowputc: fix compilation if flow control enabled 2023-03-25 22:24:36 +02:00
raiden00pl
3571ff3c54 arch/nrf53: add SAADC support 2023-03-25 18:37:51 +02:00
liuxuanfu
87852e8cbe arch/arm/src/stm32/hardware: Fix register define 2023-03-24 14:55:09 -03:00
liuxuanfu
945e4c6d81 arch/arm/src/stm32/hardware: Add stm32g4 rcc apb1 timer enable compatibility 2023-03-24 14:55:09 -03:00
raiden00pl
a1aecd7369 {stm32/stm32l4/stm32f7/stm32h7/efm32}/otgdev: remove invalid use of the priv field for EP
This field is for use in the class driver, not in the controller logic
2023-03-24 09:13:05 -07:00
raiden00pl
13a96c7eb7 {stm32f7,stm32h7}/otg: fix compilation for USBDEV when USB_DEBUG=y 2023-03-24 08:16:06 -07:00
Dong Heng
663b4c4f34 xtensa/esp32: Tasks use PSRAM as stack can do SPI flash read/write/erase/map/unmap 2023-03-23 09:26:09 -03:00
Matthias Grob
d1113110f3 armv7-m irq: avoid uninitialized warning/error
arm-none-eabi-gcc 12.2.0 gives the following warnings:
error: 'primask' is used uninitialized
error: 'primask' may be used uninitialized

We use Werror and the file is indirectly included in different
places. I suggest telling the compiler to ignore these warnings
since primask is initialized on the first assembly line.

This is the only problem I encountered so far when upgrading the compiler.
2023-03-23 04:02:43 -07:00
SPRESENSE
e317af0a84 arch: cxd56xx: Fix SPI transfer without DMA
SPI transfers are dynamically determined to use DMA or not.
The flag to judge is removed in a previous simple refactoring commit.
Revert the logic and fix an issue that SPI transfer fails.
2023-03-23 08:34:29 +01:00
Xiang Xiao
901cd599b1 arch: Remove MIN macro definition
use the definition from sys/param.h instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-03-22 17:26:37 -03:00
Petro Karashchenko
33a4a61cfb arch/xtensa/esp32: Workaround -Wmaybe-uninitialized warning with "GCC 12.2"
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-03-21 21:59:30 -03:00
jturnsek
1d7383d4a1 imxrt_flexpwm independent output B support added 2023-03-21 21:03:39 +02:00
Lwazi Dube
84a3ddd79b boards/sama5d3-xplained: Fix OHCI clock.
Choose a divider value that matches the description provided within
the same header file.
Include stddef.h to fix compiler errors because NULL is not defined.
Make logs print protocol, vid and pid consistently, (decimal hex hex).
2023-03-21 14:08:03 -03:00
Gustavo Henrique Nihei
d4e6d9ab77 xtensa/esp32: Update bootloader patch to recent ESP-IDF version
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-20 21:14:00 +01:00
Shoukui Zhang
947100c5b8 sim: Fix iic/spi bus open failed
when CONFIG_SIM_I2CBUS or CONFIG_SIM_SPI enabled,the iic/spi
bus will report open failed

Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2023-03-20 14:17:35 +01:00
xinbingnan
14d1f3b995 sim_linuxi2c: fix snprintf parameter
use `sizeof` instead of constant number

Signed-off-by: xinbingnan <xinbingnan@xiaomi.com>
2023-03-20 10:18:44 +01:00
ligd
bb281eedfa cache: add up_get_xcache_linesize() support
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-03-20 17:17:22 +08:00
Xiang Xiao
673a4aabf5 arch: Set the default value of ARCH for x86_64
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-03-20 09:16:44 +01:00
Lwazi Dube
f5575b1b85 boards/sama5d3-xplained: Add reboot support.
The peripheral reset flag was added to speed up the reboot.
Rebooting takes too long (15 seconds) if this flag is not set.
2023-03-20 09:13:37 +01:00
zhangyuan21
cf56e4113a arch: remove unnecessary sem_setprotocol code
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-03-17 16:53:19 -03:00
Gustavo Henrique Nihei
e205d790ee risc-v/espressif: Fix inconsistencies in IRQ interface documentation
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-17 16:51:52 -03:00
dongjiuzhu1
baa10ee047 sim/uart_ioctl: return -ENOTTY for cmd which don't support
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2023-03-17 11:48:58 -03:00
Tiago Medicci Serrano
7b807a8540 esp32-esp32c3/wifi: remove naming inconsistencies
* Remove the 'COEXISTENCE' suffix from Wi-Fi's STA + SoftAP mode.
Coexistence usually refers to Wi-Fi + BLE, instead of Wi-Fi's
operation mode;
* Remove commented debug code;
* Remove outdate function descriptions;
2023-03-16 19:07:25 +01:00
Tiago Medicci Serrano
0ca7ede228 esp32s3/wifi: fix ability to connect to open networks 2023-03-16 19:07:25 +01:00
Tiago Medicci Serrano
8ac74e5540 esp32s3/wifi: fix driver parameter setting only when needed 2023-03-16 19:07:25 +01:00
Tiago Medicci Serrano
d4b11a960f esp32s3/wifi: add support to softAP (softAP and softAP + STA mode) 2023-03-16 19:07:25 +01:00
raiden00pl
0976cddd03 arch/nrf52/nrf52_tickless_rtc.c: fix tickless operations - ostest fail without this change 2023-03-15 22:34:07 +01:00
raiden00pl
33b19e967c arch/nrf52/nrf52_tickless_rtc.c: check configuration 2023-03-15 22:34:07 +01:00
raiden00pl
93ac27ff63 arch/nrf53: add PWM support 2023-03-15 22:08:27 +01:00
raiden00pl
c2abd16dd7 arch/nrf53: add pwm register defintions 2023-03-15 22:08:27 +01:00
Gustavo Henrique Nihei
b864f37613 risc-v/espressif: Add Watchdog support on top of MWDT0
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-14 23:55:35 +01:00